wifi_Example - wifi test

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wifi test

Dependencies: X_NUCLEO_IKS01A2 mbed-http

easy-connect/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp@0:24d3eb812fd4, 2018-09-05 (annotated)

Committer:: JMF
Date:: Wed Sep 05 14:28:24 2018 +0000
Revision:: 0:24d3eb812fd4

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
JMF	0:24d3eb812fd4	1	/*
JMF	0:24d3eb812fd4	2	* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
JMF	0:24d3eb812fd4	3	* SPDX-License-Identifier: Apache-2.0
JMF	0:24d3eb812fd4	4	* Licensed under the Apache License, Version 2.0 (the License); you may
JMF	0:24d3eb812fd4	5	* not use this file except in compliance with the License.
JMF	0:24d3eb812fd4	6	* You may obtain a copy of the License at
JMF	0:24d3eb812fd4	7	*
JMF	0:24d3eb812fd4	8	* http://www.apache.org/licenses/LICENSE-2.0
JMF	0:24d3eb812fd4	9	*
JMF	0:24d3eb812fd4	10	* Unless required by applicable law or agreed to in writing, software
JMF	0:24d3eb812fd4	11	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
JMF	0:24d3eb812fd4	12	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
JMF	0:24d3eb812fd4	13	* See the License for the specific language governing permissions and
JMF	0:24d3eb812fd4	14	* limitations under the License.
JMF	0:24d3eb812fd4	15	*/
JMF	0:24d3eb812fd4	16	#include "NanostackRfPhyMcr20a.h"
JMF	0:24d3eb812fd4	17
JMF	0:24d3eb812fd4	18	#ifdef MBED_CONF_NANOSTACK_CONFIGURATION
JMF	0:24d3eb812fd4	19
JMF	0:24d3eb812fd4	20	#include "ns_types.h"
JMF	0:24d3eb812fd4	21	#include "platform/arm_hal_interrupt.h"
JMF	0:24d3eb812fd4	22	#include "nanostack/platform/arm_hal_phy.h"
JMF	0:24d3eb812fd4	23	#include <string.h>
JMF	0:24d3eb812fd4	24	#include "rtos.h"
JMF	0:24d3eb812fd4	25
JMF	0:24d3eb812fd4	26	/* Freescale headers which are for C files */
JMF	0:24d3eb812fd4	27	extern "C" {
JMF	0:24d3eb812fd4	28	#include "MCR20Drv.h"
JMF	0:24d3eb812fd4	29	#include "MCR20Reg.h"
JMF	0:24d3eb812fd4	30	#include "MCR20Overwrites.h"
JMF	0:24d3eb812fd4	31	}
JMF	0:24d3eb812fd4	32
JMF	0:24d3eb812fd4	33
JMF	0:24d3eb812fd4	34	#define RF_BUFFER_SIZE 128
JMF	0:24d3eb812fd4	35
JMF	0:24d3eb812fd4	36	/Radio RX and TX state definitions/
JMF	0:24d3eb812fd4	37	#define RFF_ON 0x01
JMF	0:24d3eb812fd4	38	#define RFF_RX 0x02
JMF	0:24d3eb812fd4	39	#define RFF_TX 0x04
JMF	0:24d3eb812fd4	40	#define RFF_CCA 0x08
JMF	0:24d3eb812fd4	41
JMF	0:24d3eb812fd4	42	#define RF_MODE_NORMAL 0
JMF	0:24d3eb812fd4	43	#define RF_MODE_SNIFFER 1
JMF	0:24d3eb812fd4	44
JMF	0:24d3eb812fd4	45	#define RF_CCA_THRESHOLD 75 /* -75 dBm */
JMF	0:24d3eb812fd4	46
JMF	0:24d3eb812fd4	47	#define RF_TX_POWER_MAX 0
JMF	0:24d3eb812fd4	48
JMF	0:24d3eb812fd4	49	/* PHY constants in symbols */
JMF	0:24d3eb812fd4	50	#define gPhyWarmUpTime_c 9
JMF	0:24d3eb812fd4	51	#define gPhySHRDuration_c 10
JMF	0:24d3eb812fd4	52	#define gPhySymbolsPerOctet_c 2
JMF	0:24d3eb812fd4	53	#define gPhyAckWaitDuration_c 54
JMF	0:24d3eb812fd4	54
JMF	0:24d3eb812fd4	55	#define gCcaED_c 0
JMF	0:24d3eb812fd4	56	#define gCcaCCA_MODE1_c 1
JMF	0:24d3eb812fd4	57
JMF	0:24d3eb812fd4	58	#define gXcvrRunState_d gXcvrPwrAutodoze_c
JMF	0:24d3eb812fd4	59	#if !defined(TARGET_KW24D)
JMF	0:24d3eb812fd4	60	#define gXcvrLowPowerState_d gXcvrPwrHibernate_c
JMF	0:24d3eb812fd4	61	#else
JMF	0:24d3eb812fd4	62	#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
JMF	0:24d3eb812fd4	63	#endif
JMF	0:24d3eb812fd4	64
JMF	0:24d3eb812fd4	65	/* MCR20A XCVR states */
JMF	0:24d3eb812fd4	66	typedef enum xcvrState_tag{
JMF	0:24d3eb812fd4	67	gIdle_c,
JMF	0:24d3eb812fd4	68	gRX_c,
JMF	0:24d3eb812fd4	69	gTX_c,
JMF	0:24d3eb812fd4	70	gCCA_c,
JMF	0:24d3eb812fd4	71	gTR_c,
JMF	0:24d3eb812fd4	72	gCCCA_c,
JMF	0:24d3eb812fd4	73	}xcvrState_t;
JMF	0:24d3eb812fd4	74
JMF	0:24d3eb812fd4	75	/* MCR20A XCVR low power states */
JMF	0:24d3eb812fd4	76	typedef enum xcvrPwrMode_tag{
JMF	0:24d3eb812fd4	77	gXcvrPwrIdle_c,
JMF	0:24d3eb812fd4	78	gXcvrPwrAutodoze_c,
JMF	0:24d3eb812fd4	79	gXcvrPwrDoze_c,
JMF	0:24d3eb812fd4	80	gXcvrPwrHibernate_c
JMF	0:24d3eb812fd4	81	}xcvrPwrMode_t;
JMF	0:24d3eb812fd4	82
JMF	0:24d3eb812fd4	83
JMF	0:24d3eb812fd4	84	/RF Part Type/
JMF	0:24d3eb812fd4	85	typedef enum
JMF	0:24d3eb812fd4	86	{
JMF	0:24d3eb812fd4	87	FREESCALE_UNKNOW_DEV = 0,
JMF	0:24d3eb812fd4	88	FREESCALE_MCR20A
JMF	0:24d3eb812fd4	89	}rf_trx_part_e;
JMF	0:24d3eb812fd4	90
JMF	0:24d3eb812fd4	91	/Atmel RF states/
JMF	0:24d3eb812fd4	92	typedef enum
JMF	0:24d3eb812fd4	93	{
JMF	0:24d3eb812fd4	94	NOP = 0x00,
JMF	0:24d3eb812fd4	95	BUSY_RX = 0x01,
JMF	0:24d3eb812fd4	96	RF_TX_START = 0x02,
JMF	0:24d3eb812fd4	97	FORCE_TRX_OFF = 0x03,
JMF	0:24d3eb812fd4	98	FORCE_PLL_ON = 0x04,
JMF	0:24d3eb812fd4	99	RX_ON = 0x06,
JMF	0:24d3eb812fd4	100	TRX_OFF = 0x08,
JMF	0:24d3eb812fd4	101	PLL_ON = 0x09,
JMF	0:24d3eb812fd4	102	BUSY_RX_AACK = 0x11,
JMF	0:24d3eb812fd4	103	SLEEP = 0x0F,
JMF	0:24d3eb812fd4	104	RX_AACK_ON = 0x16,
JMF	0:24d3eb812fd4	105	TX_ARET_ON = 0x19
JMF	0:24d3eb812fd4	106	}rf_trx_states_t;
JMF	0:24d3eb812fd4	107
JMF	0:24d3eb812fd4	108	/RF receive buffer/
JMF	0:24d3eb812fd4	109	static uint8_t rf_buffer[RF_BUFFER_SIZE];
JMF	0:24d3eb812fd4	110
JMF	0:24d3eb812fd4	111	/* TX info */
JMF	0:24d3eb812fd4	112	static uint8_t radio_tx_power = 0x17; /* 0 dBm */
JMF	0:24d3eb812fd4	113	static uint8_t mac_tx_handle = 0;
JMF	0:24d3eb812fd4	114	static uint8_t need_ack = 0;
JMF	0:24d3eb812fd4	115	static uint16_t tx_len = 0;
JMF	0:24d3eb812fd4	116
JMF	0:24d3eb812fd4	117	/* RF driver data */
JMF	0:24d3eb812fd4	118	static xcvrState_t mPhySeqState;
JMF	0:24d3eb812fd4	119	static xcvrPwrMode_t mPwrState;
JMF	0:24d3eb812fd4	120	static phy_device_driver_s device_driver;
JMF	0:24d3eb812fd4	121	static uint8_t mStatusAndControlRegs[8];
JMF	0:24d3eb812fd4	122	static uint8_t rf_rnd = 0;
JMF	0:24d3eb812fd4	123	static int8_t rf_radio_driver_id = -1;
JMF	0:24d3eb812fd4	124	static uint8_t MAC_address[8];
JMF	0:24d3eb812fd4	125
JMF	0:24d3eb812fd4	126	/* Driver instance handle and hardware */
JMF	0:24d3eb812fd4	127	static NanostackRfPhyMcr20a *rf = NULL;
JMF	0:24d3eb812fd4	128	static SPI *spi = NULL;
JMF	0:24d3eb812fd4	129	static DigitalOut *cs = NULL;
JMF	0:24d3eb812fd4	130	static DigitalOut *rst = NULL;
JMF	0:24d3eb812fd4	131	static InterruptIn *irq = NULL;
JMF	0:24d3eb812fd4	132	static DigitalIn *irq_pin = NULL;
JMF	0:24d3eb812fd4	133	static Thread *irq_thread = NULL;
JMF	0:24d3eb812fd4	134
JMF	0:24d3eb812fd4	135	/* Channel info / / 2405 2410 2415 2420 2425 2430 2435 2440 2445 2450 2455 2460 2465 2470 2475 2480 */
JMF	0:24d3eb812fd4	136	static const uint8_t pll_int[16] = {0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D};
JMF	0:24d3eb812fd4	137	static const uint16_t pll_frac[16] = {0x2800, 0x5000, 0x7800, 0xA000, 0xC800, 0xF000, 0x1800, 0x4000, 0x6800, 0x9000, 0xB800, 0xE000, 0x0800, 0x3000, 0x5800, 0x8000};
JMF	0:24d3eb812fd4	138
JMF	0:24d3eb812fd4	139	/* Channel configurations for 2.4 */
JMF	0:24d3eb812fd4	140	static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
JMF	0:24d3eb812fd4	141
JMF	0:24d3eb812fd4	142	static const phy_device_channel_page_s phy_channel_pages[] = {
JMF	0:24d3eb812fd4	143	{ CHANNEL_PAGE_0, &phy_24ghz},
JMF	0:24d3eb812fd4	144	{ CHANNEL_PAGE_0, NULL}
JMF	0:24d3eb812fd4	145	};
JMF	0:24d3eb812fd4	146
JMF	0:24d3eb812fd4	147
JMF	0:24d3eb812fd4	148	static rf_trx_part_e rf_radio_type_read(void);
JMF	0:24d3eb812fd4	149
JMF	0:24d3eb812fd4	150	MBED_UNUSED static void rf_ack_wait_timer_start(uint16_t slots);
JMF	0:24d3eb812fd4	151	MBED_UNUSED static void rf_ack_wait_timer_stop(void);
JMF	0:24d3eb812fd4	152	MBED_UNUSED static void rf_handle_cca_ed_done(void);
JMF	0:24d3eb812fd4	153	MBED_UNUSED static void rf_handle_tx_end(void);
JMF	0:24d3eb812fd4	154	MBED_UNUSED static void rf_handle_rx_end(void);
JMF	0:24d3eb812fd4	155	MBED_UNUSED static void rf_on(void);
JMF	0:24d3eb812fd4	156	MBED_UNUSED static void rf_receive(void);
JMF	0:24d3eb812fd4	157	MBED_UNUSED static void rf_poll_trx_state_change(rf_trx_states_t trx_state);
JMF	0:24d3eb812fd4	158	MBED_UNUSED static void rf_init(void);
JMF	0:24d3eb812fd4	159	MBED_UNUSED static void rf_set_mac_address(const uint8_t *ptr);
JMF	0:24d3eb812fd4	160	MBED_UNUSED static int8_t rf_device_register(void);
JMF	0:24d3eb812fd4	161	MBED_UNUSED static void rf_device_unregister(void);
JMF	0:24d3eb812fd4	162	MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
JMF	0:24d3eb812fd4	163	MBED_UNUSED static void rf_cca_abort(void);
JMF	0:24d3eb812fd4	164	MBED_UNUSED static void rf_read_mac_address(uint8_t *ptr);
JMF	0:24d3eb812fd4	165	MBED_UNUSED static int8_t rf_read_random(void);
JMF	0:24d3eb812fd4	166	MBED_UNUSED static void rf_calibration_cb(void);
JMF	0:24d3eb812fd4	167	MBED_UNUSED static void rf_init_phy_mode(void);
JMF	0:24d3eb812fd4	168	MBED_UNUSED static void rf_ack_wait_timer_interrupt(void);
JMF	0:24d3eb812fd4	169	MBED_UNUSED static void rf_calibration_timer_interrupt(void);
JMF	0:24d3eb812fd4	170	MBED_UNUSED static void rf_calibration_timer_start(uint32_t slots);
JMF	0:24d3eb812fd4	171	MBED_UNUSED static void rf_cca_timer_interrupt(void);
JMF	0:24d3eb812fd4	172	MBED_UNUSED static void rf_cca_timer_start(uint32_t slots);
JMF	0:24d3eb812fd4	173	MBED_UNUSED static uint16_t rf_get_phy_mtu_size(void);
JMF	0:24d3eb812fd4	174	MBED_UNUSED static uint8_t rf_scale_lqi(int8_t rssi);
JMF	0:24d3eb812fd4	175
JMF	0:24d3eb812fd4	176	/**
JMF	0:24d3eb812fd4	177	* RF output power write
JMF	0:24d3eb812fd4	178	*
JMF	0:24d3eb812fd4	179	* \brief TX power has to be set before network start.
JMF	0:24d3eb812fd4	180	*
JMF	0:24d3eb812fd4	181	* \param power
JMF	0:24d3eb812fd4	182	* See datasheet for TX power settings
JMF	0:24d3eb812fd4	183	*
JMF	0:24d3eb812fd4	184	* \return 0, Supported Value
JMF	0:24d3eb812fd4	185	* \return -1, Not Supported Value
JMF	0:24d3eb812fd4	186	*/
JMF	0:24d3eb812fd4	187	MBED_UNUSED static int8_t rf_tx_power_set(uint8_t power);
JMF	0:24d3eb812fd4	188	MBED_UNUSED static uint8_t rf_tx_power_get(void);
JMF	0:24d3eb812fd4	189	MBED_UNUSED static int8_t rf_enable_antenna_diversity(void);
JMF	0:24d3eb812fd4	190
JMF	0:24d3eb812fd4	191	/* Private functions */
JMF	0:24d3eb812fd4	192	MBED_UNUSED static void rf_abort(void);
JMF	0:24d3eb812fd4	193	MBED_UNUSED static void rf_promiscuous(uint8_t mode);
JMF	0:24d3eb812fd4	194	MBED_UNUSED static void rf_get_timestamp(uint32_t *pRetClk);
JMF	0:24d3eb812fd4	195	MBED_UNUSED static void rf_set_timeout(uint32_t *pEndTime);
JMF	0:24d3eb812fd4	196	MBED_UNUSED static void rf_set_power_state(xcvrPwrMode_t newState);
JMF	0:24d3eb812fd4	197	MBED_UNUSED static uint8_t rf_if_read_rnd(void);
JMF	0:24d3eb812fd4	198	MBED_UNUSED static uint8_t rf_convert_LQI(uint8_t hwLqi);
JMF	0:24d3eb812fd4	199	MBED_UNUSED static uint8_t rf_get_channel_energy(void);
JMF	0:24d3eb812fd4	200	MBED_UNUSED static uint8_t rf_convert_energy_level(uint8_t energyLevel);
JMF	0:24d3eb812fd4	201	MBED_UNUSED static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi);
JMF	0:24d3eb812fd4	202	MBED_UNUSED static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
JMF	0:24d3eb812fd4	203	MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
JMF	0:24d3eb812fd4	204	MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
JMF	0:24d3eb812fd4	205	static void PHY_InterruptThread(void);
JMF	0:24d3eb812fd4	206	static void handle_interrupt(void);
JMF	0:24d3eb812fd4	207
JMF	0:24d3eb812fd4	208
JMF	0:24d3eb812fd4	209	/*
JMF	0:24d3eb812fd4	210	* \brief Read connected radio part.
JMF	0:24d3eb812fd4	211	*
JMF	0:24d3eb812fd4	212	* This function only return valid information when rf_init() is called
JMF	0:24d3eb812fd4	213	*
JMF	0:24d3eb812fd4	214	* \return
JMF	0:24d3eb812fd4	215	*/
JMF	0:24d3eb812fd4	216	static rf_trx_part_e rf_radio_type_read(void)
JMF	0:24d3eb812fd4	217	{
JMF	0:24d3eb812fd4	218	return FREESCALE_MCR20A;
JMF	0:24d3eb812fd4	219	}
JMF	0:24d3eb812fd4	220
JMF	0:24d3eb812fd4	221	/*
JMF	0:24d3eb812fd4	222	* \brief Function initialises and registers the RF driver.
JMF	0:24d3eb812fd4	223	*
JMF	0:24d3eb812fd4	224	* \param none
JMF	0:24d3eb812fd4	225	*
JMF	0:24d3eb812fd4	226	* \return rf_radio_driver_id Driver ID given by NET library
JMF	0:24d3eb812fd4	227	*/
JMF	0:24d3eb812fd4	228	static int8_t rf_device_register(void)
JMF	0:24d3eb812fd4	229	{
JMF	0:24d3eb812fd4	230	rf_trx_part_e radio_type;
JMF	0:24d3eb812fd4	231
JMF	0:24d3eb812fd4	232	rf_init();
JMF	0:24d3eb812fd4	233
JMF	0:24d3eb812fd4	234
JMF	0:24d3eb812fd4	235
JMF	0:24d3eb812fd4	236	radio_type = rf_radio_type_read();
JMF	0:24d3eb812fd4	237	if(radio_type == FREESCALE_MCR20A)
JMF	0:24d3eb812fd4	238	{
JMF	0:24d3eb812fd4	239	/Set pointer to MAC address/
JMF	0:24d3eb812fd4	240	device_driver.PHY_MAC = MAC_address;
JMF	0:24d3eb812fd4	241	device_driver.driver_description = (char*)"FREESCALE_MAC";
JMF	0:24d3eb812fd4	242
JMF	0:24d3eb812fd4	243	//Create setup Used Radio chips
JMF	0:24d3eb812fd4	244	/Type of RF PHY is SubGHz/
JMF	0:24d3eb812fd4	245	device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
JMF	0:24d3eb812fd4	246
JMF	0:24d3eb812fd4	247	device_driver.phy_channel_pages = phy_channel_pages;
JMF	0:24d3eb812fd4	248	/Maximum size of payload is 127/
JMF	0:24d3eb812fd4	249	device_driver.phy_MTU = 127;
JMF	0:24d3eb812fd4	250	/No header in PHY/
JMF	0:24d3eb812fd4	251	device_driver.phy_header_length = 0;
JMF	0:24d3eb812fd4	252	/No tail in PHY/
JMF	0:24d3eb812fd4	253	device_driver.phy_tail_length = 0;
JMF	0:24d3eb812fd4	254	/Set address write function/
JMF	0:24d3eb812fd4	255	device_driver.address_write = &rf_address_write;
JMF	0:24d3eb812fd4	256	/Set RF extension function/
JMF	0:24d3eb812fd4	257	device_driver.extension = &rf_extension;
JMF	0:24d3eb812fd4	258	/Set RF state control function/
JMF	0:24d3eb812fd4	259	device_driver.state_control = &rf_interface_state_control;
JMF	0:24d3eb812fd4	260	/Set transmit function/
JMF	0:24d3eb812fd4	261	device_driver.tx = &rf_start_cca;
JMF	0:24d3eb812fd4	262	/Upper layer callbacks init to NULL/
JMF	0:24d3eb812fd4	263	device_driver.phy_rx_cb = NULL;
JMF	0:24d3eb812fd4	264	device_driver.phy_tx_done_cb = NULL;
JMF	0:24d3eb812fd4	265	/Virtual upper data callback init to NULL/
JMF	0:24d3eb812fd4	266	device_driver.arm_net_virtual_rx_cb = NULL;
JMF	0:24d3eb812fd4	267	device_driver.arm_net_virtual_tx_cb = NULL;
JMF	0:24d3eb812fd4	268
JMF	0:24d3eb812fd4	269	/Register device driver/
JMF	0:24d3eb812fd4	270	rf_radio_driver_id = arm_net_phy_register(&device_driver);
JMF	0:24d3eb812fd4	271	}
JMF	0:24d3eb812fd4	272
JMF	0:24d3eb812fd4	273	return rf_radio_driver_id;
JMF	0:24d3eb812fd4	274	}
JMF	0:24d3eb812fd4	275
JMF	0:24d3eb812fd4	276	/*
JMF	0:24d3eb812fd4	277	* \brief Function unregisters the RF driver.
JMF	0:24d3eb812fd4	278	*
JMF	0:24d3eb812fd4	279	* \param none
JMF	0:24d3eb812fd4	280	*
JMF	0:24d3eb812fd4	281	* \return none
JMF	0:24d3eb812fd4	282	*/
JMF	0:24d3eb812fd4	283	static void rf_device_unregister(void)
JMF	0:24d3eb812fd4	284	{
JMF	0:24d3eb812fd4	285	arm_net_phy_unregister(rf_radio_driver_id);
JMF	0:24d3eb812fd4	286	}
JMF	0:24d3eb812fd4	287
JMF	0:24d3eb812fd4	288	/*
JMF	0:24d3eb812fd4	289	* \brief Function returns the generated 8-bit random value for seeding Pseudo-random generator.
JMF	0:24d3eb812fd4	290	*
JMF	0:24d3eb812fd4	291	* \param none
JMF	0:24d3eb812fd4	292	*
JMF	0:24d3eb812fd4	293	* \return random value
JMF	0:24d3eb812fd4	294	*/
JMF	0:24d3eb812fd4	295	static int8_t rf_read_random(void)
JMF	0:24d3eb812fd4	296	{
JMF	0:24d3eb812fd4	297	return rf_rnd;
JMF	0:24d3eb812fd4	298	}
JMF	0:24d3eb812fd4	299
JMF	0:24d3eb812fd4	300	/*
JMF	0:24d3eb812fd4	301	* \brief Function is a call back for ACK wait timeout.
JMF	0:24d3eb812fd4	302	*
JMF	0:24d3eb812fd4	303	* \param none
JMF	0:24d3eb812fd4	304	*
JMF	0:24d3eb812fd4	305	* \return none
JMF	0:24d3eb812fd4	306	*/
JMF	0:24d3eb812fd4	307	static void rf_ack_wait_timer_interrupt(void)
JMF	0:24d3eb812fd4	308	{
JMF	0:24d3eb812fd4	309	/* The packet was transmitted successfully, but no ACK was received */
JMF	0:24d3eb812fd4	310	if (device_driver.phy_tx_done_cb) {
JMF	0:24d3eb812fd4	311	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
JMF	0:24d3eb812fd4	312	}
JMF	0:24d3eb812fd4	313	rf_receive();
JMF	0:24d3eb812fd4	314	}
JMF	0:24d3eb812fd4	315
JMF	0:24d3eb812fd4	316	/*
JMF	0:24d3eb812fd4	317	* \brief Function is a call back for calibration interval timer.
JMF	0:24d3eb812fd4	318	*
JMF	0:24d3eb812fd4	319	* \param none
JMF	0:24d3eb812fd4	320	*
JMF	0:24d3eb812fd4	321	* \return none
JMF	0:24d3eb812fd4	322	*/
JMF	0:24d3eb812fd4	323	static void rf_calibration_timer_interrupt(void)
JMF	0:24d3eb812fd4	324	{
JMF	0:24d3eb812fd4	325	}
JMF	0:24d3eb812fd4	326
JMF	0:24d3eb812fd4	327	/*
JMF	0:24d3eb812fd4	328	* \brief Function is a call back for cca interval timer.
JMF	0:24d3eb812fd4	329	*
JMF	0:24d3eb812fd4	330	* \param none
JMF	0:24d3eb812fd4	331	*
JMF	0:24d3eb812fd4	332	* \return none
JMF	0:24d3eb812fd4	333	*/
JMF	0:24d3eb812fd4	334	static void rf_cca_timer_interrupt(void)
JMF	0:24d3eb812fd4	335	{
JMF	0:24d3eb812fd4	336	/* CCA time-out handled by Hardware */
JMF	0:24d3eb812fd4	337	}
JMF	0:24d3eb812fd4	338
JMF	0:24d3eb812fd4	339
JMF	0:24d3eb812fd4	340	/*
JMF	0:24d3eb812fd4	341	* \brief Function starts the ACK wait time-out.
JMF	0:24d3eb812fd4	342	*
JMF	0:24d3eb812fd4	343	* \param slots The ACK wait time-out in [symbols]
JMF	0:24d3eb812fd4	344	*
JMF	0:24d3eb812fd4	345	* \return none
JMF	0:24d3eb812fd4	346	*/
JMF	0:24d3eb812fd4	347	static void rf_ack_wait_timer_start(uint16_t time)
JMF	0:24d3eb812fd4	348	{
JMF	0:24d3eb812fd4	349	uint32_t timeout;
JMF	0:24d3eb812fd4	350
JMF	0:24d3eb812fd4	351	rf_get_timestamp(&timeout);
JMF	0:24d3eb812fd4	352	timeout += time;
JMF	0:24d3eb812fd4	353	rf_set_timeout(&timeout);
JMF	0:24d3eb812fd4	354	}
JMF	0:24d3eb812fd4	355
JMF	0:24d3eb812fd4	356	/*
JMF	0:24d3eb812fd4	357	* \brief Function starts the calibration interval.
JMF	0:24d3eb812fd4	358	*
JMF	0:24d3eb812fd4	359	* \param slots Given slots, resolution 50us
JMF	0:24d3eb812fd4	360	*
JMF	0:24d3eb812fd4	361	* \return none
JMF	0:24d3eb812fd4	362	*/
JMF	0:24d3eb812fd4	363	static void rf_calibration_timer_start(uint32_t slots)
JMF	0:24d3eb812fd4	364	{
JMF	0:24d3eb812fd4	365	(void)slots;
JMF	0:24d3eb812fd4	366	}
JMF	0:24d3eb812fd4	367
JMF	0:24d3eb812fd4	368	/*
JMF	0:24d3eb812fd4	369	* \brief Function starts the CCA timout.
JMF	0:24d3eb812fd4	370	*
JMF	0:24d3eb812fd4	371	* \param slots Given slots, resolution 50us
JMF	0:24d3eb812fd4	372	*
JMF	0:24d3eb812fd4	373	* \return none
JMF	0:24d3eb812fd4	374	*/
JMF	0:24d3eb812fd4	375	static void rf_cca_timer_start(uint32_t slots)
JMF	0:24d3eb812fd4	376	{
JMF	0:24d3eb812fd4	377	(void)slots;
JMF	0:24d3eb812fd4	378	}
JMF	0:24d3eb812fd4	379
JMF	0:24d3eb812fd4	380	/*
JMF	0:24d3eb812fd4	381	* \brief Function stops the ACK wait timeout.
JMF	0:24d3eb812fd4	382	*
JMF	0:24d3eb812fd4	383	* \param none
JMF	0:24d3eb812fd4	384	*
JMF	0:24d3eb812fd4	385	* \return none
JMF	0:24d3eb812fd4	386	*/
JMF	0:24d3eb812fd4	387	static void rf_ack_wait_timer_stop(void)
JMF	0:24d3eb812fd4	388	{
JMF	0:24d3eb812fd4	389	}
JMF	0:24d3eb812fd4	390
JMF	0:24d3eb812fd4	391	/*
JMF	0:24d3eb812fd4	392	* \brief Function reads the MAC address array.
JMF	0:24d3eb812fd4	393	*
JMF	0:24d3eb812fd4	394	* \param ptr Pointer to read array
JMF	0:24d3eb812fd4	395	*
JMF	0:24d3eb812fd4	396	* \return none
JMF	0:24d3eb812fd4	397	*/
JMF	0:24d3eb812fd4	398	static void rf_read_mac_address(uint8_t *ptr)
JMF	0:24d3eb812fd4	399	{
JMF	0:24d3eb812fd4	400	memcpy(ptr, MAC_address, 8);
JMF	0:24d3eb812fd4	401	}
JMF	0:24d3eb812fd4	402
JMF	0:24d3eb812fd4	403	/*
JMF	0:24d3eb812fd4	404	* \brief Function sets the MAC address array.
JMF	0:24d3eb812fd4	405	*
JMF	0:24d3eb812fd4	406	* \param ptr Pointer to given MAC address array
JMF	0:24d3eb812fd4	407	*
JMF	0:24d3eb812fd4	408	* \return none
JMF	0:24d3eb812fd4	409	*/
JMF	0:24d3eb812fd4	410	static void rf_set_mac_address(const uint8_t *ptr)
JMF	0:24d3eb812fd4	411	{
JMF	0:24d3eb812fd4	412	memcpy(MAC_address, ptr, 8);
JMF	0:24d3eb812fd4	413	}
JMF	0:24d3eb812fd4	414
JMF	0:24d3eb812fd4	415	static uint16_t rf_get_phy_mtu_size(void)
JMF	0:24d3eb812fd4	416	{
JMF	0:24d3eb812fd4	417	return device_driver.phy_MTU;
JMF	0:24d3eb812fd4	418	}
JMF	0:24d3eb812fd4	419
JMF	0:24d3eb812fd4	420	/*
JMF	0:24d3eb812fd4	421	* \brief Function writes 16-bit address in RF address filter.
JMF	0:24d3eb812fd4	422	*
JMF	0:24d3eb812fd4	423	* \param short_address Given short address
JMF	0:24d3eb812fd4	424	*
JMF	0:24d3eb812fd4	425	* \return none
JMF	0:24d3eb812fd4	426	*/
JMF	0:24d3eb812fd4	427	static void rf_set_short_adr(uint8_t * short_address)
JMF	0:24d3eb812fd4	428	{
JMF	0:24d3eb812fd4	429	/* Write one register at a time to be accessible from hibernate mode */
JMF	0:24d3eb812fd4	430	MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_MSB, short_address[0]);
JMF	0:24d3eb812fd4	431	MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_LSB, short_address[1]);
JMF	0:24d3eb812fd4	432	}
JMF	0:24d3eb812fd4	433
JMF	0:24d3eb812fd4	434	/*
JMF	0:24d3eb812fd4	435	* \brief Function writes PAN Id in RF PAN Id filter.
JMF	0:24d3eb812fd4	436	*
JMF	0:24d3eb812fd4	437	* \param pan_id Given PAN Id
JMF	0:24d3eb812fd4	438	*
JMF	0:24d3eb812fd4	439	* \return none
JMF	0:24d3eb812fd4	440	*/
JMF	0:24d3eb812fd4	441	static void rf_set_pan_id(uint8_t *pan_id)
JMF	0:24d3eb812fd4	442	{
JMF	0:24d3eb812fd4	443	/* Write one register at a time to be accessible from hibernate mode */
JMF	0:24d3eb812fd4	444	MCR20Drv_IndirectAccessSPIWrite(MACPANID0_MSB, pan_id[0]);
JMF	0:24d3eb812fd4	445	MCR20Drv_IndirectAccessSPIWrite(MACPANID0_LSB, pan_id[1]);
JMF	0:24d3eb812fd4	446	}
JMF	0:24d3eb812fd4	447
JMF	0:24d3eb812fd4	448	/*
JMF	0:24d3eb812fd4	449	* \brief Function writes 64-bit address in RF address filter.
JMF	0:24d3eb812fd4	450	*
JMF	0:24d3eb812fd4	451	* \param address Given 64-bit address
JMF	0:24d3eb812fd4	452	*
JMF	0:24d3eb812fd4	453	* \return none
JMF	0:24d3eb812fd4	454	*/
JMF	0:24d3eb812fd4	455	static void rf_set_address(uint8_t *address)
JMF	0:24d3eb812fd4	456	{
JMF	0:24d3eb812fd4	457	/* Write one register at a time to be accessible from hibernate mode */
JMF	0:24d3eb812fd4	458	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_0, address[7]);
JMF	0:24d3eb812fd4	459	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_8, address[6]);
JMF	0:24d3eb812fd4	460	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_16, address[5]);
JMF	0:24d3eb812fd4	461	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_24, address[4]);
JMF	0:24d3eb812fd4	462	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_32, address[3]);
JMF	0:24d3eb812fd4	463	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_40, address[2]);
JMF	0:24d3eb812fd4	464	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_48, address[1]);
JMF	0:24d3eb812fd4	465	MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_56, address[0]);
JMF	0:24d3eb812fd4	466	}
JMF	0:24d3eb812fd4	467
JMF	0:24d3eb812fd4	468	/*
JMF	0:24d3eb812fd4	469	* \brief Function sets the RF channel.
JMF	0:24d3eb812fd4	470	*
JMF	0:24d3eb812fd4	471	* \param ch New channel
JMF	0:24d3eb812fd4	472	*
JMF	0:24d3eb812fd4	473	* \return none
JMF	0:24d3eb812fd4	474	*/
JMF	0:24d3eb812fd4	475	static void rf_channel_set(uint8_t channel)
JMF	0:24d3eb812fd4	476	{
JMF	0:24d3eb812fd4	477	MCR20Drv_DirectAccessSPIWrite(PLL_INT0, pll_int[channel - 11]);
JMF	0:24d3eb812fd4	478	MCR20Drv_DirectAccessSPIMultiByteWrite(PLL_FRAC0_LSB, (uint8_t *) &pll_frac[channel - 11], 2);
JMF	0:24d3eb812fd4	479	}
JMF	0:24d3eb812fd4	480
JMF	0:24d3eb812fd4	481
JMF	0:24d3eb812fd4	482	/*
JMF	0:24d3eb812fd4	483	* \brief Function initialises the radio driver and resets the radio.
JMF	0:24d3eb812fd4	484	*
JMF	0:24d3eb812fd4	485	* \param none
JMF	0:24d3eb812fd4	486	*
JMF	0:24d3eb812fd4	487	* \return none
JMF	0:24d3eb812fd4	488	*/
JMF	0:24d3eb812fd4	489	static void rf_init(void)
JMF	0:24d3eb812fd4	490	{
JMF	0:24d3eb812fd4	491	uint32_t index;
JMF	0:24d3eb812fd4	492	mPhySeqState = gIdle_c;
JMF	0:24d3eb812fd4	493	mPwrState = gXcvrPwrIdle_c;
JMF	0:24d3eb812fd4	494	/Reset RF module/
JMF	0:24d3eb812fd4	495	MCR20Drv_RESET();
JMF	0:24d3eb812fd4	496	/* Initialize the transceiver SPI driver */
JMF	0:24d3eb812fd4	497	MCR20Drv_Init();
JMF	0:24d3eb812fd4	498	/* Disable Tristate on MISO for SPI reads */
JMF	0:24d3eb812fd4	499	MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02);
JMF	0:24d3eb812fd4	500	/* Set XCVR clock output settings */
JMF	0:24d3eb812fd4	501	#if !defined(TARGET_KW24D)
JMF	0:24d3eb812fd4	502	MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
JMF	0:24d3eb812fd4	503	#endif
JMF	0:24d3eb812fd4	504	/* Set default XCVR power state */
JMF	0:24d3eb812fd4	505	rf_set_power_state(gXcvrRunState_d);
JMF	0:24d3eb812fd4	506
JMF	0:24d3eb812fd4	507	/* PHY_CTRL1 default HW settings + AUTOACK enabled */
JMF	0:24d3eb812fd4	508	mStatusAndControlRegs[PHY_CTRL1] = cPHY_CTRL1_AUTOACK;
JMF	0:24d3eb812fd4	509	/* PHY_CTRL2 : mask all PP interrupts */
JMF	0:24d3eb812fd4	510	mStatusAndControlRegs[PHY_CTRL2] = cPHY_CTRL2_CRC_MSK \| \
JMF	0:24d3eb812fd4	511	cPHY_CTRL2_PLL_UNLOCK_MSK \| \
JMF	0:24d3eb812fd4	512	/cPHY_CTRL2_FILTERFAIL_MSK \| / \
JMF	0:24d3eb812fd4	513	cPHY_CTRL2_RX_WMRK_MSK \| \
JMF	0:24d3eb812fd4	514	cPHY_CTRL2_CCAMSK \| \
JMF	0:24d3eb812fd4	515	cPHY_CTRL2_RXMSK \| \
JMF	0:24d3eb812fd4	516	cPHY_CTRL2_TXMSK \| \
JMF	0:24d3eb812fd4	517	cPHY_CTRL2_SEQMSK;
JMF	0:24d3eb812fd4	518	/* PHY_CTRL3 : enable timer 3 and disable remaining interrupts */
JMF	0:24d3eb812fd4	519	mStatusAndControlRegs[PHY_CTRL3] = cPHY_CTRL3_ASM_MSK \| \
JMF	0:24d3eb812fd4	520	cPHY_CTRL3_PB_ERR_MSK \| \
JMF	0:24d3eb812fd4	521	cPHY_CTRL3_WAKE_MSK \| \
JMF	0:24d3eb812fd4	522	cPHY_CTRL3_TMR3CMP_EN;
JMF	0:24d3eb812fd4	523	/* PHY_CTRL4 unmask global TRX interrupts, enable 16 bit mode for TC2 - TC2 prime EN */
JMF	0:24d3eb812fd4	524	mStatusAndControlRegs[PHY_CTRL4] = cPHY_CTRL4_TC2PRIME_EN \| (gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c);
JMF	0:24d3eb812fd4	525	/* Clear all PP IRQ bits to avoid unexpected interrupts immediately after initialization */
JMF	0:24d3eb812fd4	526	mStatusAndControlRegs[IRQSTS1] = cIRQSTS1_PLL_UNLOCK_IRQ \| \
JMF	0:24d3eb812fd4	527	cIRQSTS1_FILTERFAIL_IRQ \| \
JMF	0:24d3eb812fd4	528	cIRQSTS1_RXWTRMRKIRQ \| \
JMF	0:24d3eb812fd4	529	cIRQSTS1_CCAIRQ \| \
JMF	0:24d3eb812fd4	530	cIRQSTS1_RXIRQ \| \
JMF	0:24d3eb812fd4	531	cIRQSTS1_TXIRQ \| \
JMF	0:24d3eb812fd4	532	cIRQSTS1_SEQIRQ;
JMF	0:24d3eb812fd4	533
JMF	0:24d3eb812fd4	534	mStatusAndControlRegs[IRQSTS2] = cIRQSTS2_ASM_IRQ \| cIRQSTS2_PB_ERR_IRQ \| cIRQSTS2_WAKE_IRQ;
JMF	0:24d3eb812fd4	535	/* Mask and clear all TMR IRQs */
JMF	0:24d3eb812fd4	536	mStatusAndControlRegs[IRQSTS3] = cIRQSTS3_TMR4MSK \| cIRQSTS3_TMR3MSK \| cIRQSTS3_TMR2MSK \| cIRQSTS3_TMR1MSK \| \
JMF	0:24d3eb812fd4	537	cIRQSTS3_TMR4IRQ \| cIRQSTS3_TMR3IRQ \| cIRQSTS3_TMR2IRQ \| cIRQSTS3_TMR1IRQ;
JMF	0:24d3eb812fd4	538	/* Write settings to XCVR */
JMF	0:24d3eb812fd4	539	MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 5);
JMF	0:24d3eb812fd4	540	/* Clear all interrupts */
JMF	0:24d3eb812fd4	541	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, &mStatusAndControlRegs[IRQSTS1], 3);
JMF	0:24d3eb812fd4	542
JMF	0:24d3eb812fd4	543	/* RX_FRAME_FILTER. Accept FrameVersion 0 and 1 packets, reject all others */
JMF	0:24d3eb812fd4	544	MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (cRX_FRAME_FLT_FRM_VER \| \
JMF	0:24d3eb812fd4	545	cRX_FRAME_FLT_BEACON_FT \| \
JMF	0:24d3eb812fd4	546	cRX_FRAME_FLT_DATA_FT \| \
JMF	0:24d3eb812fd4	547	cRX_FRAME_FLT_CMD_FT ));
JMF	0:24d3eb812fd4	548	/* Direct register overwrites */
JMF	0:24d3eb812fd4	549	for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++)
JMF	0:24d3eb812fd4	550	MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data);
JMF	0:24d3eb812fd4	551	/* Indirect register overwrites */
JMF	0:24d3eb812fd4	552	for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++)
JMF	0:24d3eb812fd4	553	MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data);
JMF	0:24d3eb812fd4	554
JMF	0:24d3eb812fd4	555	/* Set the CCA energy threshold value */
JMF	0:24d3eb812fd4	556	MCR20Drv_IndirectAccessSPIWrite(CCA1_THRESH, RF_CCA_THRESHOLD);
JMF	0:24d3eb812fd4	557	/* Set prescaller to obtain 1 symbol (16us) timebase */
JMF	0:24d3eb812fd4	558	MCR20Drv_IndirectAccessSPIWrite(TMR_PRESCALE, 0x05);
JMF	0:24d3eb812fd4	559
JMF	0:24d3eb812fd4	560	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	561
JMF	0:24d3eb812fd4	562	/Read random variable. This will be used when seeding pseudo-random generator/
JMF	0:24d3eb812fd4	563	rf_rnd = rf_if_read_rnd();
JMF	0:24d3eb812fd4	564	/Write initial eui64/
JMF	0:24d3eb812fd4	565	rf_set_address(MAC_address);
JMF	0:24d3eb812fd4	566	/set default channel to 11/
JMF	0:24d3eb812fd4	567	rf_channel_set(11);
JMF	0:24d3eb812fd4	568	/Start receiver/
JMF	0:24d3eb812fd4	569	rf_receive();
JMF	0:24d3eb812fd4	570	}
JMF	0:24d3eb812fd4	571
JMF	0:24d3eb812fd4	572	/**
JMF	0:24d3eb812fd4	573	* \brief Function gets called when MAC is setting radio off.
JMF	0:24d3eb812fd4	574	*
JMF	0:24d3eb812fd4	575	* \param none
JMF	0:24d3eb812fd4	576	*
JMF	0:24d3eb812fd4	577	* \return none
JMF	0:24d3eb812fd4	578	*/
JMF	0:24d3eb812fd4	579	static void rf_off(void)
JMF	0:24d3eb812fd4	580	{
JMF	0:24d3eb812fd4	581	/* Abort any ongoing sequences */
JMF	0:24d3eb812fd4	582	rf_abort();
JMF	0:24d3eb812fd4	583	/* Set XCVR in a low power state */
JMF	0:24d3eb812fd4	584	rf_set_power_state(gXcvrLowPowerState_d);
JMF	0:24d3eb812fd4	585	}
JMF	0:24d3eb812fd4	586
JMF	0:24d3eb812fd4	587	/*
JMF	0:24d3eb812fd4	588	* \brief Function polls the RF state until it has changed to desired state.
JMF	0:24d3eb812fd4	589	*
JMF	0:24d3eb812fd4	590	* \param trx_state RF state
JMF	0:24d3eb812fd4	591	*
JMF	0:24d3eb812fd4	592	* \return none
JMF	0:24d3eb812fd4	593	*/
JMF	0:24d3eb812fd4	594	static void rf_poll_trx_state_change(rf_trx_states_t trx_state)
JMF	0:24d3eb812fd4	595	{
JMF	0:24d3eb812fd4	596	(void)trx_state;
JMF	0:24d3eb812fd4	597	}
JMF	0:24d3eb812fd4	598
JMF	0:24d3eb812fd4	599	/*
JMF	0:24d3eb812fd4	600	* \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
JMF	0:24d3eb812fd4	601	*
JMF	0:24d3eb812fd4	602	* \param data_ptr Pointer to TX data
JMF	0:24d3eb812fd4	603	* \param data_length Length of the TX data
JMF	0:24d3eb812fd4	604	* \param tx_handle Handle to transmission
JMF	0:24d3eb812fd4	605	* \return 0 Success
JMF	0:24d3eb812fd4	606	* \return -1 Busy
JMF	0:24d3eb812fd4	607	*/
JMF	0:24d3eb812fd4	608	static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
JMF	0:24d3eb812fd4	609	{
JMF	0:24d3eb812fd4	610	uint8_t ccaMode;
JMF	0:24d3eb812fd4	611
JMF	0:24d3eb812fd4	612	/* Parameter validation */
JMF	0:24d3eb812fd4	613	if( !data_ptr \|\| (data_length > 125) \|\| (PHY_LAYER_PAYLOAD != data_protocol) )
JMF	0:24d3eb812fd4	614	{
JMF	0:24d3eb812fd4	615	return -1;
JMF	0:24d3eb812fd4	616	}
JMF	0:24d3eb812fd4	617
JMF	0:24d3eb812fd4	618	if( mPhySeqState == gRX_c )
JMF	0:24d3eb812fd4	619	{
JMF	0:24d3eb812fd4	620	uint8_t phyReg = MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F;
JMF	0:24d3eb812fd4	621	/* Check for an Rx in progress. */
JMF	0:24d3eb812fd4	622	if((phyReg <= 0x06) \|\| (phyReg == 0x15) \|\| (phyReg == 0x16))
JMF	0:24d3eb812fd4	623	{
JMF	0:24d3eb812fd4	624	if (device_driver.phy_tx_done_cb) {
JMF	0:24d3eb812fd4	625	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
JMF	0:24d3eb812fd4	626	}
JMF	0:24d3eb812fd4	627	return -1;
JMF	0:24d3eb812fd4	628	}
JMF	0:24d3eb812fd4	629	rf_abort();
JMF	0:24d3eb812fd4	630	}
JMF	0:24d3eb812fd4	631
JMF	0:24d3eb812fd4	632	/Check if transmitter is busy/
JMF	0:24d3eb812fd4	633	if( mPhySeqState != gIdle_c )
JMF	0:24d3eb812fd4	634	{
JMF	0:24d3eb812fd4	635	/Return busy/
JMF	0:24d3eb812fd4	636	return -1;
JMF	0:24d3eb812fd4	637	}
JMF	0:24d3eb812fd4	638
JMF	0:24d3eb812fd4	639	/Store TX handle/
JMF	0:24d3eb812fd4	640	mac_tx_handle = tx_handle;
JMF	0:24d3eb812fd4	641	/Check if transmitted data needs to be acked/
JMF	0:24d3eb812fd4	642	need_ack = (*data_ptr & 0x20) == 0x20;
JMF	0:24d3eb812fd4	643
JMF	0:24d3eb812fd4	644	/* Set XCVR power state in run mode */
JMF	0:24d3eb812fd4	645	rf_set_power_state(gXcvrRunState_d);
JMF	0:24d3eb812fd4	646	/* Load data into XCVR */
JMF	0:24d3eb812fd4	647	tx_len = data_length + 2;
JMF	0:24d3eb812fd4	648	MCR20Drv_PB_SPIBurstWrite(data_ptr - 1, data_length + 1);
JMF	0:24d3eb812fd4	649	MCR20Drv_PB_SPIByteWrite(0,tx_len);
JMF	0:24d3eb812fd4	650
JMF	0:24d3eb812fd4	651	/* Set CCA mode 1 */
JMF	0:24d3eb812fd4	652	ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
JMF	0:24d3eb812fd4	653	if( ccaMode != gCcaCCA_MODE1_c )
JMF	0:24d3eb812fd4	654	{
JMF	0:24d3eb812fd4	655	mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
JMF	0:24d3eb812fd4	656	mStatusAndControlRegs[PHY_CTRL4] \|= gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c;
JMF	0:24d3eb812fd4	657	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
JMF	0:24d3eb812fd4	658	}
JMF	0:24d3eb812fd4	659
JMF	0:24d3eb812fd4	660	/* Read XCVR registers */
JMF	0:24d3eb812fd4	661	mStatusAndControlRegs[0] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[1], 4);
JMF	0:24d3eb812fd4	662	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	663	mStatusAndControlRegs[PHY_CTRL1] \|= gCCA_c;
JMF	0:24d3eb812fd4	664	mPhySeqState = gCCA_c;
JMF	0:24d3eb812fd4	665
JMF	0:24d3eb812fd4	666	/* Ensure that no spurious interrupts are raised */
JMF	0:24d3eb812fd4	667	mStatusAndControlRegs[IRQSTS3] &= 0xF0; /* do not change other IRQ status */
JMF	0:24d3eb812fd4	668	mStatusAndControlRegs[IRQSTS3] \|= (cIRQSTS3_TMR3MSK \| cIRQSTS3_TMR3IRQ);
JMF	0:24d3eb812fd4	669	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
JMF	0:24d3eb812fd4	670
JMF	0:24d3eb812fd4	671	/* Write XCVR settings */
JMF	0:24d3eb812fd4	672	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	673
JMF	0:24d3eb812fd4	674	/* Unmask SEQ interrupt */
JMF	0:24d3eb812fd4	675	mStatusAndControlRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
JMF	0:24d3eb812fd4	676	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]);
JMF	0:24d3eb812fd4	677
JMF	0:24d3eb812fd4	678	/Return success/
JMF	0:24d3eb812fd4	679	return 0;
JMF	0:24d3eb812fd4	680	}
JMF	0:24d3eb812fd4	681
JMF	0:24d3eb812fd4	682	/*
JMF	0:24d3eb812fd4	683	* \brief Function aborts CCA process.
JMF	0:24d3eb812fd4	684	*
JMF	0:24d3eb812fd4	685	* \param none
JMF	0:24d3eb812fd4	686	*
JMF	0:24d3eb812fd4	687	* \return none
JMF	0:24d3eb812fd4	688	*/
JMF	0:24d3eb812fd4	689	static void rf_cca_abort(void)
JMF	0:24d3eb812fd4	690	{
JMF	0:24d3eb812fd4	691	rf_abort();
JMF	0:24d3eb812fd4	692	}
JMF	0:24d3eb812fd4	693
JMF	0:24d3eb812fd4	694	/*
JMF	0:24d3eb812fd4	695	* \brief Function starts the transmission of the frame. Called from ISR context!
JMF	0:24d3eb812fd4	696	*
JMF	0:24d3eb812fd4	697	* \param none
JMF	0:24d3eb812fd4	698	*
JMF	0:24d3eb812fd4	699	* \return none
JMF	0:24d3eb812fd4	700	*/
JMF	0:24d3eb812fd4	701	static void rf_start_tx(void)
JMF	0:24d3eb812fd4	702	{
JMF	0:24d3eb812fd4	703	/* Perform TxRxAck sequence if required by phyTxMode */
JMF	0:24d3eb812fd4	704	if( need_ack )
JMF	0:24d3eb812fd4	705	{
JMF	0:24d3eb812fd4	706	mStatusAndControlRegs[PHY_CTRL1] \|= cPHY_CTRL1_RXACKRQD;
JMF	0:24d3eb812fd4	707	mPhySeqState = gTR_c;
JMF	0:24d3eb812fd4	708	}
JMF	0:24d3eb812fd4	709	else
JMF	0:24d3eb812fd4	710	{
JMF	0:24d3eb812fd4	711	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_RXACKRQD);
JMF	0:24d3eb812fd4	712	mPhySeqState = gTX_c;
JMF	0:24d3eb812fd4	713	}
JMF	0:24d3eb812fd4	714
JMF	0:24d3eb812fd4	715	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	716	mStatusAndControlRegs[PHY_CTRL1] \|= mPhySeqState;
JMF	0:24d3eb812fd4	717
JMF	0:24d3eb812fd4	718	/* Unmask SEQ interrupt */
JMF	0:24d3eb812fd4	719	mStatusAndControlRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
JMF	0:24d3eb812fd4	720
JMF	0:24d3eb812fd4	721	/* Start the sequence immediately */
JMF	0:24d3eb812fd4	722	MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 2);
JMF	0:24d3eb812fd4	723
JMF	0:24d3eb812fd4	724	if( need_ack )
JMF	0:24d3eb812fd4	725	{
JMF	0:24d3eb812fd4	726	rf_ack_wait_timer_start(gPhyWarmUpTime_c + gPhySHRDuration_c + tx_len * gPhySymbolsPerOctet_c + gPhyAckWaitDuration_c);
JMF	0:24d3eb812fd4	727	}
JMF	0:24d3eb812fd4	728	}
JMF	0:24d3eb812fd4	729
JMF	0:24d3eb812fd4	730	/*
JMF	0:24d3eb812fd4	731	* \brief Function sets the RF in RX state. Called from ISR context!
JMF	0:24d3eb812fd4	732	*
JMF	0:24d3eb812fd4	733	* \param none
JMF	0:24d3eb812fd4	734	*
JMF	0:24d3eb812fd4	735	* \return none
JMF	0:24d3eb812fd4	736	*/
JMF	0:24d3eb812fd4	737	static void rf_receive(void)
JMF	0:24d3eb812fd4	738	{
JMF	0:24d3eb812fd4	739	uint8_t phyRegs[5];
JMF	0:24d3eb812fd4	740
JMF	0:24d3eb812fd4	741	/* RX can start only from Idle state */
JMF	0:24d3eb812fd4	742	if( mPhySeqState != gIdle_c )
JMF	0:24d3eb812fd4	743	{
JMF	0:24d3eb812fd4	744	return;
JMF	0:24d3eb812fd4	745	}
JMF	0:24d3eb812fd4	746
JMF	0:24d3eb812fd4	747	/* Set XCVR power state in run mode */
JMF	0:24d3eb812fd4	748	rf_set_power_state(gXcvrRunState_d);
JMF	0:24d3eb812fd4	749	/* read XVCR settings */
JMF	0:24d3eb812fd4	750	phyRegs[IRQSTS1] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &phyRegs[IRQSTS2], 4);
JMF	0:24d3eb812fd4	751	/* unmask SEQ interrupt */
JMF	0:24d3eb812fd4	752	phyRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
JMF	0:24d3eb812fd4	753	/* set XcvrSeq to RX */
JMF	0:24d3eb812fd4	754	phyRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	755	phyRegs[PHY_CTRL1] \|= gRX_c;
JMF	0:24d3eb812fd4	756	mPhySeqState = gRX_c;
JMF	0:24d3eb812fd4	757	/* Ensure that no spurious interrupts are raised */
JMF	0:24d3eb812fd4	758	phyRegs[IRQSTS3] &= 0xF0; /* do not change other IRQ status */
JMF	0:24d3eb812fd4	759	phyRegs[IRQSTS3] \|= cIRQSTS3_TMR3MSK \| cIRQSTS3_TMR3IRQ;
JMF	0:24d3eb812fd4	760	/* sync settings with XCVR */
JMF	0:24d3eb812fd4	761	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, phyRegs, 5);
JMF	0:24d3eb812fd4	762	}
JMF	0:24d3eb812fd4	763
JMF	0:24d3eb812fd4	764	/*
JMF	0:24d3eb812fd4	765	* \brief Function calibrates the radio.
JMF	0:24d3eb812fd4	766	*
JMF	0:24d3eb812fd4	767	* \param none
JMF	0:24d3eb812fd4	768	*
JMF	0:24d3eb812fd4	769	* \return none
JMF	0:24d3eb812fd4	770	*/
JMF	0:24d3eb812fd4	771	static void rf_calibration_cb(void)
JMF	0:24d3eb812fd4	772	{
JMF	0:24d3eb812fd4	773	}
JMF	0:24d3eb812fd4	774
JMF	0:24d3eb812fd4	775	/*
JMF	0:24d3eb812fd4	776	* \brief Function sets RF_ON flag when radio is powered.
JMF	0:24d3eb812fd4	777	*
JMF	0:24d3eb812fd4	778	* \param none
JMF	0:24d3eb812fd4	779	*
JMF	0:24d3eb812fd4	780	* \return none
JMF	0:24d3eb812fd4	781	*/
JMF	0:24d3eb812fd4	782	static void rf_on(void)
JMF	0:24d3eb812fd4	783	{
JMF	0:24d3eb812fd4	784	}
JMF	0:24d3eb812fd4	785
JMF	0:24d3eb812fd4	786	/*
JMF	0:24d3eb812fd4	787	* \brief Function is a call back for RX end interrupt.
JMF	0:24d3eb812fd4	788	*
JMF	0:24d3eb812fd4	789	* \param none
JMF	0:24d3eb812fd4	790	*
JMF	0:24d3eb812fd4	791	* \return none
JMF	0:24d3eb812fd4	792	*/
JMF	0:24d3eb812fd4	793	static void rf_handle_rx_end(void)
JMF	0:24d3eb812fd4	794	{
JMF	0:24d3eb812fd4	795	uint8_t rf_lqi = MCR20Drv_DirectAccessSPIRead(LQI_VALUE);
JMF	0:24d3eb812fd4	796	int8_t rf_rssi = 0;
JMF	0:24d3eb812fd4	797	uint8_t len = mStatusAndControlRegs[RX_FRM_LEN] - 2;
JMF	0:24d3eb812fd4	798
JMF	0:24d3eb812fd4	799
JMF	0:24d3eb812fd4	800	/Start receiver/
JMF	0:24d3eb812fd4	801	rf_receive();
JMF	0:24d3eb812fd4	802
JMF	0:24d3eb812fd4	803	/Check the length is valid/
JMF	0:24d3eb812fd4	804	if(len > 1 && len < RF_BUFFER_SIZE)
JMF	0:24d3eb812fd4	805	{
JMF	0:24d3eb812fd4	806	rf_lqi = rf_convert_LQI(rf_lqi);
JMF	0:24d3eb812fd4	807	rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi);
JMF	0:24d3eb812fd4	808	/gcararu: Scale LQI using received RSSI, to match the LQI reported by the ATMEL radio /
JMF	0:24d3eb812fd4	809	rf_lqi = rf_scale_lqi(rf_rssi);
JMF	0:24d3eb812fd4	810
JMF	0:24d3eb812fd4	811	/Read received packet/
JMF	0:24d3eb812fd4	812	MCR20Drv_PB_SPIBurstRead(rf_buffer, len);
JMF	0:24d3eb812fd4	813	if (device_driver.phy_rx_cb) {
JMF	0:24d3eb812fd4	814	device_driver.phy_rx_cb(rf_buffer, len, rf_lqi, rf_rssi, rf_radio_driver_id);
JMF	0:24d3eb812fd4	815	}
JMF	0:24d3eb812fd4	816	}
JMF	0:24d3eb812fd4	817	}
JMF	0:24d3eb812fd4	818
JMF	0:24d3eb812fd4	819	/*
JMF	0:24d3eb812fd4	820	* \brief Function is called when MAC is shutting down the radio.
JMF	0:24d3eb812fd4	821	*
JMF	0:24d3eb812fd4	822	* \param none
JMF	0:24d3eb812fd4	823	*
JMF	0:24d3eb812fd4	824	* \return none
JMF	0:24d3eb812fd4	825	*/
JMF	0:24d3eb812fd4	826	static void rf_shutdown(void)
JMF	0:24d3eb812fd4	827	{
JMF	0:24d3eb812fd4	828	/Call RF OFF/
JMF	0:24d3eb812fd4	829	rf_off();
JMF	0:24d3eb812fd4	830	}
JMF	0:24d3eb812fd4	831
JMF	0:24d3eb812fd4	832	/*
JMF	0:24d3eb812fd4	833	* \brief Function is a call back for TX end interrupt.
JMF	0:24d3eb812fd4	834	*
JMF	0:24d3eb812fd4	835	* \param none
JMF	0:24d3eb812fd4	836	*
JMF	0:24d3eb812fd4	837	* \return none
JMF	0:24d3eb812fd4	838	*/
JMF	0:24d3eb812fd4	839	static void rf_handle_tx_end(void)
JMF	0:24d3eb812fd4	840	{
JMF	0:24d3eb812fd4	841	uint8_t rx_frame_pending = mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_RX_FRM_PEND;
JMF	0:24d3eb812fd4	842
JMF	0:24d3eb812fd4	843	/Start receiver/
JMF	0:24d3eb812fd4	844	rf_receive();
JMF	0:24d3eb812fd4	845
JMF	0:24d3eb812fd4	846	if (!device_driver.phy_tx_done_cb) {
JMF	0:24d3eb812fd4	847	return;
JMF	0:24d3eb812fd4	848	}
JMF	0:24d3eb812fd4	849
JMF	0:24d3eb812fd4	850	/Call PHY TX Done API/
JMF	0:24d3eb812fd4	851	if( need_ack )
JMF	0:24d3eb812fd4	852	{
JMF	0:24d3eb812fd4	853	if( rx_frame_pending )
JMF	0:24d3eb812fd4	854	{
JMF	0:24d3eb812fd4	855	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE_PENDING, 1, 1);
JMF	0:24d3eb812fd4	856	}
JMF	0:24d3eb812fd4	857	else
JMF	0:24d3eb812fd4	858	{
JMF	0:24d3eb812fd4	859	// arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
JMF	0:24d3eb812fd4	860	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE, 1, 1);
JMF	0:24d3eb812fd4	861	}
JMF	0:24d3eb812fd4	862	}
JMF	0:24d3eb812fd4	863	else
JMF	0:24d3eb812fd4	864	{
JMF	0:24d3eb812fd4	865	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
JMF	0:24d3eb812fd4	866	}
JMF	0:24d3eb812fd4	867	}
JMF	0:24d3eb812fd4	868
JMF	0:24d3eb812fd4	869	/*
JMF	0:24d3eb812fd4	870	* \brief Function is a call back for CCA ED done interrupt.
JMF	0:24d3eb812fd4	871	*
JMF	0:24d3eb812fd4	872	* \param none
JMF	0:24d3eb812fd4	873	*
JMF	0:24d3eb812fd4	874	* \return none
JMF	0:24d3eb812fd4	875	*/
JMF	0:24d3eb812fd4	876	static void rf_handle_cca_ed_done(void)
JMF	0:24d3eb812fd4	877	{
JMF	0:24d3eb812fd4	878	/Check the result of CCA process/
JMF	0:24d3eb812fd4	879	if( !(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA) )
JMF	0:24d3eb812fd4	880	{
JMF	0:24d3eb812fd4	881	rf_start_tx();
JMF	0:24d3eb812fd4	882	}
JMF	0:24d3eb812fd4	883	else if (device_driver.phy_tx_done_cb)
JMF	0:24d3eb812fd4	884	{
JMF	0:24d3eb812fd4	885	/Send CCA fail notification/
JMF	0:24d3eb812fd4	886	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
JMF	0:24d3eb812fd4	887	}
JMF	0:24d3eb812fd4	888	}
JMF	0:24d3eb812fd4	889
JMF	0:24d3eb812fd4	890	/*
JMF	0:24d3eb812fd4	891	* \brief Function sets the TX power variable.
JMF	0:24d3eb812fd4	892	*
JMF	0:24d3eb812fd4	893	* \param power TX power setting
JMF	0:24d3eb812fd4	894	*
JMF	0:24d3eb812fd4	895	* \return 0 Success
JMF	0:24d3eb812fd4	896	* \return -1 Fail
JMF	0:24d3eb812fd4	897	*/
JMF	0:24d3eb812fd4	898	static int8_t rf_tx_power_set(uint8_t power)
JMF	0:24d3eb812fd4	899	{
JMF	0:24d3eb812fd4	900	/* gcapraru: Map MCR20A Tx power levels over ATMEL values */
JMF	0:24d3eb812fd4	901	static uint8_t pwrLevelMapping[16] = {25,25,25,24,24,24,23,23,22,22,21,20,19,18,17,14};
JMF	0:24d3eb812fd4	902
JMF	0:24d3eb812fd4	903	if( power > 15 )
JMF	0:24d3eb812fd4	904	{
JMF	0:24d3eb812fd4	905	return -1;
JMF	0:24d3eb812fd4	906	}
JMF	0:24d3eb812fd4	907
JMF	0:24d3eb812fd4	908	radio_tx_power = power;
JMF	0:24d3eb812fd4	909	MCR20Drv_DirectAccessSPIWrite(PA_PWR, pwrLevelMapping[power]);
JMF	0:24d3eb812fd4	910	return 0;
JMF	0:24d3eb812fd4	911	}
JMF	0:24d3eb812fd4	912
JMF	0:24d3eb812fd4	913	/*
JMF	0:24d3eb812fd4	914	* \brief Function returns the TX power variable.
JMF	0:24d3eb812fd4	915	*
JMF	0:24d3eb812fd4	916	* \param none
JMF	0:24d3eb812fd4	917	*
JMF	0:24d3eb812fd4	918	* \return radio_tx_power TX power variable
JMF	0:24d3eb812fd4	919	*/
JMF	0:24d3eb812fd4	920	static uint8_t rf_tx_power_get(void)
JMF	0:24d3eb812fd4	921	{
JMF	0:24d3eb812fd4	922	return radio_tx_power;
JMF	0:24d3eb812fd4	923	}
JMF	0:24d3eb812fd4	924
JMF	0:24d3eb812fd4	925	/*
JMF	0:24d3eb812fd4	926	* \brief Function enables the usage of Antenna diversity.
JMF	0:24d3eb812fd4	927	*
JMF	0:24d3eb812fd4	928	* \param none
JMF	0:24d3eb812fd4	929	*
JMF	0:24d3eb812fd4	930	* \return 0 Success
JMF	0:24d3eb812fd4	931	*/
JMF	0:24d3eb812fd4	932	static int8_t rf_enable_antenna_diversity(void)
JMF	0:24d3eb812fd4	933	{
JMF	0:24d3eb812fd4	934	uint8_t phyReg;
JMF	0:24d3eb812fd4	935
JMF	0:24d3eb812fd4	936	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
JMF	0:24d3eb812fd4	937	phyReg \|= cANT_AGC_CTRL_FAD_EN_Mask_c;
JMF	0:24d3eb812fd4	938	MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
JMF	0:24d3eb812fd4	939
JMF	0:24d3eb812fd4	940	phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
JMF	0:24d3eb812fd4	941	phyReg \|= 0x02;
JMF	0:24d3eb812fd4	942	MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
JMF	0:24d3eb812fd4	943
JMF	0:24d3eb812fd4	944	return 0;
JMF	0:24d3eb812fd4	945	}
JMF	0:24d3eb812fd4	946
JMF	0:24d3eb812fd4	947	/*
JMF	0:24d3eb812fd4	948	* \brief Function gives the control of RF states to MAC.
JMF	0:24d3eb812fd4	949	*
JMF	0:24d3eb812fd4	950	* \param new_state RF state
JMF	0:24d3eb812fd4	951	* \param rf_channel RF channel
JMF	0:24d3eb812fd4	952	*
JMF	0:24d3eb812fd4	953	* \return 0 Success
JMF	0:24d3eb812fd4	954	*/
JMF	0:24d3eb812fd4	955	static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
JMF	0:24d3eb812fd4	956	{
JMF	0:24d3eb812fd4	957	int8_t ret_val = 0;
JMF	0:24d3eb812fd4	958	switch (new_state)
JMF	0:24d3eb812fd4	959	{
JMF	0:24d3eb812fd4	960	/Reset PHY driver and set to idle/
JMF	0:24d3eb812fd4	961	case PHY_INTERFACE_RESET:
JMF	0:24d3eb812fd4	962	break;
JMF	0:24d3eb812fd4	963	/Disable PHY Interface driver/
JMF	0:24d3eb812fd4	964	case PHY_INTERFACE_DOWN:
JMF	0:24d3eb812fd4	965	rf_shutdown();
JMF	0:24d3eb812fd4	966	break;
JMF	0:24d3eb812fd4	967	/Enable PHY Interface driver/
JMF	0:24d3eb812fd4	968	case PHY_INTERFACE_UP:
JMF	0:24d3eb812fd4	969	rf_channel_set(rf_channel);
JMF	0:24d3eb812fd4	970	rf_receive();
JMF	0:24d3eb812fd4	971	break;
JMF	0:24d3eb812fd4	972	/Enable wireless interface ED scan mode/
JMF	0:24d3eb812fd4	973	case PHY_INTERFACE_RX_ENERGY_STATE:
JMF	0:24d3eb812fd4	974	rf_abort();
JMF	0:24d3eb812fd4	975	rf_channel_set(rf_channel);
JMF	0:24d3eb812fd4	976	break;
JMF	0:24d3eb812fd4	977	case PHY_INTERFACE_SNIFFER_STATE: /*< Enable Sniffer state /
JMF	0:24d3eb812fd4	978	rf_promiscuous(1);
JMF	0:24d3eb812fd4	979	rf_channel_set(rf_channel);
JMF	0:24d3eb812fd4	980	rf_receive();
JMF	0:24d3eb812fd4	981	break;
JMF	0:24d3eb812fd4	982	}
JMF	0:24d3eb812fd4	983	return ret_val;
JMF	0:24d3eb812fd4	984	}
JMF	0:24d3eb812fd4	985
JMF	0:24d3eb812fd4	986	/*
JMF	0:24d3eb812fd4	987	* \brief Function controls the ACK pending, channel setting and energy detection.
JMF	0:24d3eb812fd4	988	*
JMF	0:24d3eb812fd4	989	* \param extension_type Type of control
JMF	0:24d3eb812fd4	990	* \param data_ptr Data from NET library
JMF	0:24d3eb812fd4	991	*
JMF	0:24d3eb812fd4	992	* \return 0 Success
JMF	0:24d3eb812fd4	993	*/
JMF	0:24d3eb812fd4	994	static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
JMF	0:24d3eb812fd4	995	{
JMF	0:24d3eb812fd4	996	switch (extension_type)
JMF	0:24d3eb812fd4	997	{
JMF	0:24d3eb812fd4	998	/Control MAC pending bit for Indirect data transmission/
JMF	0:24d3eb812fd4	999	case PHY_EXTENSION_CTRL_PENDING_BIT:
JMF	0:24d3eb812fd4	1000	{
JMF	0:24d3eb812fd4	1001	uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
JMF	0:24d3eb812fd4	1002
JMF	0:24d3eb812fd4	1003	if(*data_ptr)
JMF	0:24d3eb812fd4	1004	{
JMF	0:24d3eb812fd4	1005	reg \|= cSRC_CTRL_ACK_FRM_PND;
JMF	0:24d3eb812fd4	1006	}
JMF	0:24d3eb812fd4	1007	else
JMF	0:24d3eb812fd4	1008	{
JMF	0:24d3eb812fd4	1009	reg &= ~cSRC_CTRL_ACK_FRM_PND;
JMF	0:24d3eb812fd4	1010	}
JMF	0:24d3eb812fd4	1011
JMF	0:24d3eb812fd4	1012	MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, reg);
JMF	0:24d3eb812fd4	1013	break;
JMF	0:24d3eb812fd4	1014
JMF	0:24d3eb812fd4	1015	}
JMF	0:24d3eb812fd4	1016	/Return frame Auto Ack frame pending status/
JMF	0:24d3eb812fd4	1017	case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS: {
JMF	0:24d3eb812fd4	1018	uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
JMF	0:24d3eb812fd4	1019	if (reg & cSRC_CTRL_ACK_FRM_PND) {
JMF	0:24d3eb812fd4	1020	*data_ptr = 1;
JMF	0:24d3eb812fd4	1021	} else {
JMF	0:24d3eb812fd4	1022	*data_ptr = 0;
JMF	0:24d3eb812fd4	1023	}
JMF	0:24d3eb812fd4	1024	break;
JMF	0:24d3eb812fd4	1025	}
JMF	0:24d3eb812fd4	1026	/Set channel/
JMF	0:24d3eb812fd4	1027	case PHY_EXTENSION_SET_CHANNEL:
JMF	0:24d3eb812fd4	1028	break;
JMF	0:24d3eb812fd4	1029	/Read energy on the channel/
JMF	0:24d3eb812fd4	1030	case PHY_EXTENSION_READ_CHANNEL_ENERGY:
JMF	0:24d3eb812fd4	1031	*data_ptr = rf_get_channel_energy();
JMF	0:24d3eb812fd4	1032	break;
JMF	0:24d3eb812fd4	1033	/Read status of the link/
JMF	0:24d3eb812fd4	1034	case PHY_EXTENSION_READ_LINK_STATUS:
JMF	0:24d3eb812fd4	1035	break;
JMF	0:24d3eb812fd4	1036	case PHY_EXTENSION_CONVERT_SIGNAL_INFO:
JMF	0:24d3eb812fd4	1037	break;
JMF	0:24d3eb812fd4	1038	case PHY_EXTENSION_ACCEPT_ANY_BEACON:
JMF	0:24d3eb812fd4	1039	break;
JMF	0:24d3eb812fd4	1040	}
JMF	0:24d3eb812fd4	1041	return 0;
JMF	0:24d3eb812fd4	1042	}
JMF	0:24d3eb812fd4	1043
JMF	0:24d3eb812fd4	1044	/*
JMF	0:24d3eb812fd4	1045	* \brief Function sets the addresses to RF address filters.
JMF	0:24d3eb812fd4	1046	*
JMF	0:24d3eb812fd4	1047	* \param address_type Type of address
JMF	0:24d3eb812fd4	1048	* \param address_ptr Pointer to given address
JMF	0:24d3eb812fd4	1049	*
JMF	0:24d3eb812fd4	1050	* \return 0 Success
JMF	0:24d3eb812fd4	1051	*/
JMF	0:24d3eb812fd4	1052	static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
JMF	0:24d3eb812fd4	1053	{
JMF	0:24d3eb812fd4	1054	int8_t ret_val = 0;
JMF	0:24d3eb812fd4	1055	switch (address_type)
JMF	0:24d3eb812fd4	1056	{
JMF	0:24d3eb812fd4	1057	/Set 48-bit address/
JMF	0:24d3eb812fd4	1058	case PHY_MAC_48BIT:
JMF	0:24d3eb812fd4	1059	break;
JMF	0:24d3eb812fd4	1060	/Set 64-bit address/
JMF	0:24d3eb812fd4	1061	case PHY_MAC_64BIT:
JMF	0:24d3eb812fd4	1062	rf_set_address(address_ptr);
JMF	0:24d3eb812fd4	1063	break;
JMF	0:24d3eb812fd4	1064	/Set 16-bit address/
JMF	0:24d3eb812fd4	1065	case PHY_MAC_16BIT:
JMF	0:24d3eb812fd4	1066	rf_set_short_adr(address_ptr);
JMF	0:24d3eb812fd4	1067	break;
JMF	0:24d3eb812fd4	1068	/Set PAN Id/
JMF	0:24d3eb812fd4	1069	case PHY_MAC_PANID:
JMF	0:24d3eb812fd4	1070	rf_set_pan_id(address_ptr);
JMF	0:24d3eb812fd4	1071	break;
JMF	0:24d3eb812fd4	1072	}
JMF	0:24d3eb812fd4	1073	return ret_val;
JMF	0:24d3eb812fd4	1074	}
JMF	0:24d3eb812fd4	1075
JMF	0:24d3eb812fd4	1076	/*
JMF	0:24d3eb812fd4	1077	* \brief Function initialises the ACK wait time and returns the used PHY mode.
JMF	0:24d3eb812fd4	1078	*
JMF	0:24d3eb812fd4	1079	* \param none
JMF	0:24d3eb812fd4	1080	*
JMF	0:24d3eb812fd4	1081	* \return tmp Used PHY mode
JMF	0:24d3eb812fd4	1082	*/
JMF	0:24d3eb812fd4	1083	static void rf_init_phy_mode(void)
JMF	0:24d3eb812fd4	1084	{
JMF	0:24d3eb812fd4	1085	}
JMF	0:24d3eb812fd4	1086
JMF	0:24d3eb812fd4	1087	/*
JMF	0:24d3eb812fd4	1088	* \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
JMF	0:24d3eb812fd4	1089	*
JMF	0:24d3eb812fd4	1090	* \param none
JMF	0:24d3eb812fd4	1091	*
JMF	0:24d3eb812fd4	1092	* \return none
JMF	0:24d3eb812fd4	1093	*/
JMF	0:24d3eb812fd4	1094	static void PHY_InterruptHandler(void)
JMF	0:24d3eb812fd4	1095	{
JMF	0:24d3eb812fd4	1096	/* Disable and clear transceiver(IRQ_B) interrupt */
JMF	0:24d3eb812fd4	1097	MCR20Drv_IRQ_Disable();
JMF	0:24d3eb812fd4	1098	irq_thread->signal_set(1);
JMF	0:24d3eb812fd4	1099	}
JMF	0:24d3eb812fd4	1100
JMF	0:24d3eb812fd4	1101	static void PHY_InterruptThread(void)
JMF	0:24d3eb812fd4	1102	{
JMF	0:24d3eb812fd4	1103	for (;;) {
JMF	0:24d3eb812fd4	1104	osEvent event = irq_thread->signal_wait(0);
JMF	0:24d3eb812fd4	1105	if (event.status != osEventSignal) {
JMF	0:24d3eb812fd4	1106	continue;
JMF	0:24d3eb812fd4	1107	}
JMF	0:24d3eb812fd4	1108	handle_interrupt();
JMF	0:24d3eb812fd4	1109	}
JMF	0:24d3eb812fd4	1110	}
JMF	0:24d3eb812fd4	1111
JMF	0:24d3eb812fd4	1112	static void handle_interrupt(void)
JMF	0:24d3eb812fd4	1113	{
JMF	0:24d3eb812fd4	1114	uint8_t xcvseqCopy;
JMF	0:24d3eb812fd4	1115
JMF	0:24d3eb812fd4	1116	//MCR20Drv_IRQ_Clear();
JMF	0:24d3eb812fd4	1117
JMF	0:24d3eb812fd4	1118	/* Read transceiver interrupt status and control registers */
JMF	0:24d3eb812fd4	1119	mStatusAndControlRegs[IRQSTS1] =
JMF	0:24d3eb812fd4	1120	MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[IRQSTS2], 7);
JMF	0:24d3eb812fd4	1121
JMF	0:24d3eb812fd4	1122	xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ;
JMF	0:24d3eb812fd4	1123
JMF	0:24d3eb812fd4	1124	/* Flter Fail IRQ */
JMF	0:24d3eb812fd4	1125	if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) &&
JMF	0:24d3eb812fd4	1126	!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK) )
JMF	0:24d3eb812fd4	1127	{
JMF	0:24d3eb812fd4	1128	if( xcvseqCopy == gRX_c )
JMF	0:24d3eb812fd4	1129	{
JMF	0:24d3eb812fd4	1130	/* Abort current SEQ */
JMF	0:24d3eb812fd4	1131	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	1132	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	1133	/* Wait for Sequence Idle */
JMF	0:24d3eb812fd4	1134	while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
JMF	0:24d3eb812fd4	1135	/* Clear IRQ flags: */
JMF	0:24d3eb812fd4	1136	MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ);
JMF	0:24d3eb812fd4	1137	/* Restart Rx asap */
JMF	0:24d3eb812fd4	1138	mStatusAndControlRegs[PHY_CTRL1] \|= gRX_c;
JMF	0:24d3eb812fd4	1139	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	1140	}
JMF	0:24d3eb812fd4	1141	}
JMF	0:24d3eb812fd4	1142
JMF	0:24d3eb812fd4	1143	/* TMR3 IRQ: ACK wait time-out */
JMF	0:24d3eb812fd4	1144	if( (mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) &&
JMF	0:24d3eb812fd4	1145	!(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK) )
JMF	0:24d3eb812fd4	1146	{
JMF	0:24d3eb812fd4	1147	/* Disable TMR3 IRQ */
JMF	0:24d3eb812fd4	1148	mStatusAndControlRegs[IRQSTS3] \|= cIRQSTS3_TMR3MSK;
JMF	0:24d3eb812fd4	1149
JMF	0:24d3eb812fd4	1150	if( xcvseqCopy == gTR_c )
JMF	0:24d3eb812fd4	1151	{
JMF	0:24d3eb812fd4	1152	/* Set XCVR to Idle */
JMF	0:24d3eb812fd4	1153	mPhySeqState = gIdle_c;
JMF	0:24d3eb812fd4	1154	mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
JMF	0:24d3eb812fd4	1155	/* Mask interrupts */
JMF	0:24d3eb812fd4	1156	mStatusAndControlRegs[PHY_CTRL2] \|= cPHY_CTRL2_CCAMSK \| cPHY_CTRL2_RXMSK \| cPHY_CTRL2_TXMSK \| cPHY_CTRL2_SEQMSK;
JMF	0:24d3eb812fd4	1157	/* Sync settings with XCVR */
JMF	0:24d3eb812fd4	1158	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
JMF	0:24d3eb812fd4	1159
JMF	0:24d3eb812fd4	1160	rf_ack_wait_timer_interrupt();
JMF	0:24d3eb812fd4	1161	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1162	return;
JMF	0:24d3eb812fd4	1163	}
JMF	0:24d3eb812fd4	1164	}
JMF	0:24d3eb812fd4	1165
JMF	0:24d3eb812fd4	1166	/* Sequencer interrupt, the autosequence has completed */
JMF	0:24d3eb812fd4	1167	if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) &&
JMF	0:24d3eb812fd4	1168	!(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK) )
JMF	0:24d3eb812fd4	1169	{
JMF	0:24d3eb812fd4	1170	/* Set XCVR to Idle */
JMF	0:24d3eb812fd4	1171	mPhySeqState = gIdle_c;
JMF	0:24d3eb812fd4	1172	mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
JMF	0:24d3eb812fd4	1173	/* Mask interrupts */
JMF	0:24d3eb812fd4	1174	mStatusAndControlRegs[PHY_CTRL2] \|= cPHY_CTRL2_CCAMSK \| cPHY_CTRL2_RXMSK \| cPHY_CTRL2_TXMSK \| cPHY_CTRL2_SEQMSK;
JMF	0:24d3eb812fd4	1175	/* Sync settings with XCVR */
JMF	0:24d3eb812fd4	1176	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
JMF	0:24d3eb812fd4	1177
JMF	0:24d3eb812fd4	1178	/* PLL unlock, the autosequence has been aborted due to PLL unlock */
JMF	0:24d3eb812fd4	1179	if( mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ )
JMF	0:24d3eb812fd4	1180	{
JMF	0:24d3eb812fd4	1181	if(xcvseqCopy == gRX_c)
JMF	0:24d3eb812fd4	1182	{
JMF	0:24d3eb812fd4	1183	rf_receive();
JMF	0:24d3eb812fd4	1184	}
JMF	0:24d3eb812fd4	1185	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1186	return;
JMF	0:24d3eb812fd4	1187	}
JMF	0:24d3eb812fd4	1188
JMF	0:24d3eb812fd4	1189	switch(xcvseqCopy)
JMF	0:24d3eb812fd4	1190	{
JMF	0:24d3eb812fd4	1191	case gTX_c:
JMF	0:24d3eb812fd4	1192	case gTR_c:
JMF	0:24d3eb812fd4	1193	rf_handle_tx_end();
JMF	0:24d3eb812fd4	1194	break;
JMF	0:24d3eb812fd4	1195
JMF	0:24d3eb812fd4	1196	case gRX_c:
JMF	0:24d3eb812fd4	1197	rf_handle_rx_end();
JMF	0:24d3eb812fd4	1198	break;
JMF	0:24d3eb812fd4	1199
JMF	0:24d3eb812fd4	1200	case gCCA_c:
JMF	0:24d3eb812fd4	1201	rf_handle_cca_ed_done();
JMF	0:24d3eb812fd4	1202	break;
JMF	0:24d3eb812fd4	1203
JMF	0:24d3eb812fd4	1204	default:
JMF	0:24d3eb812fd4	1205	break;
JMF	0:24d3eb812fd4	1206	}
JMF	0:24d3eb812fd4	1207
JMF	0:24d3eb812fd4	1208	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1209	return;
JMF	0:24d3eb812fd4	1210	}
JMF	0:24d3eb812fd4	1211	/* Other IRQ. Clear XCVR interrupt flags */
JMF	0:24d3eb812fd4	1212	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
JMF	0:24d3eb812fd4	1213	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1214	}
JMF	0:24d3eb812fd4	1215
JMF	0:24d3eb812fd4	1216	/*
JMF	0:24d3eb812fd4	1217	* \brief Function forces the XCVR to Idle state.
JMF	0:24d3eb812fd4	1218	*
JMF	0:24d3eb812fd4	1219	* \param none
JMF	0:24d3eb812fd4	1220	*
JMF	0:24d3eb812fd4	1221	* \return none
JMF	0:24d3eb812fd4	1222	*/
JMF	0:24d3eb812fd4	1223	static void rf_abort(void)
JMF	0:24d3eb812fd4	1224	{
JMF	0:24d3eb812fd4	1225	/* Mask XCVR irq */
JMF	0:24d3eb812fd4	1226	MCR20Drv_IRQ_Disable();
JMF	0:24d3eb812fd4	1227
JMF	0:24d3eb812fd4	1228	mPhySeqState = gIdle_c;
JMF	0:24d3eb812fd4	1229
JMF	0:24d3eb812fd4	1230	mStatusAndControlRegs[IRQSTS1] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[IRQSTS2], 5);
JMF	0:24d3eb812fd4	1231
JMF	0:24d3eb812fd4	1232	/* Mask SEQ interrupt */
JMF	0:24d3eb812fd4	1233	mStatusAndControlRegs[PHY_CTRL2] \|= cPHY_CTRL2_SEQMSK;
JMF	0:24d3eb812fd4	1234	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]);
JMF	0:24d3eb812fd4	1235
JMF	0:24d3eb812fd4	1236	if( (mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c )
JMF	0:24d3eb812fd4	1237	{
JMF	0:24d3eb812fd4	1238	/* Abort current SEQ */
JMF	0:24d3eb812fd4	1239	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	1240	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	1241
JMF	0:24d3eb812fd4	1242	/* Wait for Sequence Idle (if not already) */
JMF	0:24d3eb812fd4	1243	while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
JMF	0:24d3eb812fd4	1244	//while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
JMF	0:24d3eb812fd4	1245	mStatusAndControlRegs[IRQSTS1] \|= cIRQSTS1_SEQIRQ;
JMF	0:24d3eb812fd4	1246	}
JMF	0:24d3eb812fd4	1247
JMF	0:24d3eb812fd4	1248	/* Clear all PP IRQ bits to avoid unexpected interrupts and mask TMR3 interrupt.
JMF	0:24d3eb812fd4	1249	Do not change TMR IRQ status. */
JMF	0:24d3eb812fd4	1250	mStatusAndControlRegs[IRQSTS3] &= 0xF0;
JMF	0:24d3eb812fd4	1251	mStatusAndControlRegs[IRQSTS3] \|= (cIRQSTS3_TMR3MSK \| cIRQSTS3_TMR3IRQ);
JMF	0:24d3eb812fd4	1252	MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
JMF	0:24d3eb812fd4	1253
JMF	0:24d3eb812fd4	1254	/* Unmask XCVR irq */
JMF	0:24d3eb812fd4	1255	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1256	}
JMF	0:24d3eb812fd4	1257
JMF	0:24d3eb812fd4	1258	/*
JMF	0:24d3eb812fd4	1259	* \brief Function reads a time-stamp value from XCVR [symbols]
JMF	0:24d3eb812fd4	1260	*
JMF	0:24d3eb812fd4	1261	* \param pEndTime pointer to location where time-stamp will be stored
JMF	0:24d3eb812fd4	1262	*
JMF	0:24d3eb812fd4	1263	* \return none
JMF	0:24d3eb812fd4	1264	*/
JMF	0:24d3eb812fd4	1265	static void rf_get_timestamp(uint32_t *pRetClk)
JMF	0:24d3eb812fd4	1266	{
JMF	0:24d3eb812fd4	1267	if(NULL == pRetClk)
JMF	0:24d3eb812fd4	1268	{
JMF	0:24d3eb812fd4	1269	return;
JMF	0:24d3eb812fd4	1270	}
JMF	0:24d3eb812fd4	1271
JMF	0:24d3eb812fd4	1272	platform_enter_critical();
JMF	0:24d3eb812fd4	1273
JMF	0:24d3eb812fd4	1274	*pRetClk = 0;
JMF	0:24d3eb812fd4	1275	MCR20Drv_DirectAccessSPIMultiByteRead(EVENT_TMR_LSB, (uint8_t *) pRetClk, 3);
JMF	0:24d3eb812fd4	1276
JMF	0:24d3eb812fd4	1277	platform_exit_critical();
JMF	0:24d3eb812fd4	1278	}
JMF	0:24d3eb812fd4	1279
JMF	0:24d3eb812fd4	1280	/*
JMF	0:24d3eb812fd4	1281	* \brief Function set a time-out to an XCVR sequence.
JMF	0:24d3eb812fd4	1282	*
JMF	0:24d3eb812fd4	1283	* \param pEndTime pointer to the sequence time-out value [symbols]
JMF	0:24d3eb812fd4	1284	*
JMF	0:24d3eb812fd4	1285	* \return none
JMF	0:24d3eb812fd4	1286	*/
JMF	0:24d3eb812fd4	1287	static void rf_set_timeout(uint32_t *pEndTime)
JMF	0:24d3eb812fd4	1288	{
JMF	0:24d3eb812fd4	1289	uint8_t phyReg;
JMF	0:24d3eb812fd4	1290
JMF	0:24d3eb812fd4	1291	if(NULL == pEndTime)
JMF	0:24d3eb812fd4	1292	{
JMF	0:24d3eb812fd4	1293	return;
JMF	0:24d3eb812fd4	1294	}
JMF	0:24d3eb812fd4	1295
JMF	0:24d3eb812fd4	1296	platform_enter_critical();
JMF	0:24d3eb812fd4	1297
JMF	0:24d3eb812fd4	1298	phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
JMF	0:24d3eb812fd4	1299	phyReg &= 0xF0; /* do not change IRQ status */
JMF	0:24d3eb812fd4	1300	phyReg \|= (cIRQSTS3_TMR3MSK); /* mask TMR3 interrupt */
JMF	0:24d3eb812fd4	1301	MCR20Drv_DirectAccessSPIWrite(IRQSTS3, phyReg);
JMF	0:24d3eb812fd4	1302
JMF	0:24d3eb812fd4	1303	MCR20Drv_DirectAccessSPIMultiByteWrite(T3CMP_LSB, (uint8_t *) pEndTime, 3);
JMF	0:24d3eb812fd4	1304
JMF	0:24d3eb812fd4	1305	phyReg &= ~(cIRQSTS3_TMR3MSK); /* unmask TMR3 interrupt */
JMF	0:24d3eb812fd4	1306	phyReg \|= (cIRQSTS3_TMR3IRQ); /* aknowledge TMR3 IRQ */
JMF	0:24d3eb812fd4	1307	MCR20Drv_DirectAccessSPIWrite(IRQSTS3, phyReg);
JMF	0:24d3eb812fd4	1308
JMF	0:24d3eb812fd4	1309	platform_exit_critical();
JMF	0:24d3eb812fd4	1310	}
JMF	0:24d3eb812fd4	1311
JMF	0:24d3eb812fd4	1312	/*
JMF	0:24d3eb812fd4	1313	* \brief Function reads a random number from RF.
JMF	0:24d3eb812fd4	1314	*
JMF	0:24d3eb812fd4	1315	* \param none
JMF	0:24d3eb812fd4	1316	*
JMF	0:24d3eb812fd4	1317	* \return 8-bit random number
JMF	0:24d3eb812fd4	1318	*/
JMF	0:24d3eb812fd4	1319	static uint8_t rf_if_read_rnd(void)
JMF	0:24d3eb812fd4	1320	{
JMF	0:24d3eb812fd4	1321	uint8_t phyReg;
JMF	0:24d3eb812fd4	1322
JMF	0:24d3eb812fd4	1323	MCR20Drv_IRQ_Disable();
JMF	0:24d3eb812fd4	1324	/* Check if XCVR is idle */
JMF	0:24d3eb812fd4	1325	phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
JMF	0:24d3eb812fd4	1326
JMF	0:24d3eb812fd4	1327	if( (phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c )
JMF	0:24d3eb812fd4	1328	{
JMF	0:24d3eb812fd4	1329	/* Program a new sequence */
JMF	0:24d3eb812fd4	1330	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyReg \| gCCA_c);
JMF	0:24d3eb812fd4	1331	/* Wait for sequence to finish */
JMF	0:24d3eb812fd4	1332	while( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ) );
JMF	0:24d3eb812fd4	1333	/* Clear interrupt flag */
JMF	0:24d3eb812fd4	1334	MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ);
JMF	0:24d3eb812fd4	1335	}
JMF	0:24d3eb812fd4	1336
JMF	0:24d3eb812fd4	1337	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1338
JMF	0:24d3eb812fd4	1339	return MCR20Drv_IndirectAccessSPIRead(_RNG);
JMF	0:24d3eb812fd4	1340	}
JMF	0:24d3eb812fd4	1341
JMF	0:24d3eb812fd4	1342	/*
JMF	0:24d3eb812fd4	1343	* \brief Function converts LQI into RSSI.
JMF	0:24d3eb812fd4	1344	*
JMF	0:24d3eb812fd4	1345	* \param LQI
JMF	0:24d3eb812fd4	1346	*
JMF	0:24d3eb812fd4	1347	* \return RSSI
JMF	0:24d3eb812fd4	1348	*/
JMF	0:24d3eb812fd4	1349	static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi)
JMF	0:24d3eb812fd4	1350	{
JMF	0:24d3eb812fd4	1351	int32_t rssi = (50*lqi - 16820) / 163;
JMF	0:24d3eb812fd4	1352	return (int8_t)rssi;
JMF	0:24d3eb812fd4	1353	}
JMF	0:24d3eb812fd4	1354
JMF	0:24d3eb812fd4	1355	/*
JMF	0:24d3eb812fd4	1356	* \brief Function scale the LQI value reported by RF into a 0-255 value.
JMF	0:24d3eb812fd4	1357	*
JMF	0:24d3eb812fd4	1358	* \param hwLqi - the LQI value reported by RF
JMF	0:24d3eb812fd4	1359	*
JMF	0:24d3eb812fd4	1360	* \return scaled LQI
JMF	0:24d3eb812fd4	1361	*/
JMF	0:24d3eb812fd4	1362	static uint8_t rf_convert_LQI(uint8_t hwLqi)
JMF	0:24d3eb812fd4	1363	{
JMF	0:24d3eb812fd4	1364	uint32_t tmpLQI;
JMF	0:24d3eb812fd4	1365
JMF	0:24d3eb812fd4	1366	/* LQI Saturation Level */
JMF	0:24d3eb812fd4	1367	if (hwLqi >= 230)
JMF	0:24d3eb812fd4	1368	{
JMF	0:24d3eb812fd4	1369	return 0xFF;
JMF	0:24d3eb812fd4	1370	}
JMF	0:24d3eb812fd4	1371	else if (hwLqi <= 9)
JMF	0:24d3eb812fd4	1372	{
JMF	0:24d3eb812fd4	1373	return 0;
JMF	0:24d3eb812fd4	1374	}
JMF	0:24d3eb812fd4	1375	else
JMF	0:24d3eb812fd4	1376	{
JMF	0:24d3eb812fd4	1377	/* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */
JMF	0:24d3eb812fd4	1378	/* The LQI value mst be multiplied by ~1.1087 */
JMF	0:24d3eb812fd4	1379	/* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/
JMF	0:24d3eb812fd4	1380	tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 );
JMF	0:24d3eb812fd4	1381	/* tmpLQI = (tmpLQI / 2^16) + hwLqi */
JMF	0:24d3eb812fd4	1382	tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi;
JMF	0:24d3eb812fd4	1383
JMF	0:24d3eb812fd4	1384	return (uint8_t)tmpLQI;
JMF	0:24d3eb812fd4	1385	}
JMF	0:24d3eb812fd4	1386	}
JMF	0:24d3eb812fd4	1387
JMF	0:24d3eb812fd4	1388	/*
JMF	0:24d3eb812fd4	1389	* \brief Function enables/disables Rx promiscuous mode.
JMF	0:24d3eb812fd4	1390	*
JMF	0:24d3eb812fd4	1391	* \param state of XCVR promiscuous mode
JMF	0:24d3eb812fd4	1392	*
JMF	0:24d3eb812fd4	1393	* \return none
JMF	0:24d3eb812fd4	1394	*/
JMF	0:24d3eb812fd4	1395	static void rf_promiscuous(uint8_t state)
JMF	0:24d3eb812fd4	1396	{
JMF	0:24d3eb812fd4	1397	uint8_t rxFrameFltReg, phyCtrl4Reg;
JMF	0:24d3eb812fd4	1398
JMF	0:24d3eb812fd4	1399	rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
JMF	0:24d3eb812fd4	1400	phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
JMF	0:24d3eb812fd4	1401
JMF	0:24d3eb812fd4	1402	if( state )
JMF	0:24d3eb812fd4	1403	{
JMF	0:24d3eb812fd4	1404	/* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */
JMF	0:24d3eb812fd4	1405	/* All frame types accepted*/
JMF	0:24d3eb812fd4	1406	phyCtrl4Reg \|= cPHY_CTRL4_PROMISCUOUS;
JMF	0:24d3eb812fd4	1407	rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
JMF	0:24d3eb812fd4	1408	rxFrameFltReg \|= (cRX_FRAME_FLT_ACK_FT \| cRX_FRAME_FLT_NS_FT);
JMF	0:24d3eb812fd4	1409	}
JMF	0:24d3eb812fd4	1410	else
JMF	0:24d3eb812fd4	1411	{
JMF	0:24d3eb812fd4	1412	phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS;
JMF	0:24d3eb812fd4	1413	/* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */
JMF	0:24d3eb812fd4	1414	/* Beacon, Data and MAC command frame types accepted */
JMF	0:24d3eb812fd4	1415	rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
JMF	0:24d3eb812fd4	1416	rxFrameFltReg \|= (0x03 << cRX_FRAME_FLT_FRM_VER_Shift_c);
JMF	0:24d3eb812fd4	1417	rxFrameFltReg &= ~(cRX_FRAME_FLT_ACK_FT \| cRX_FRAME_FLT_NS_FT);
JMF	0:24d3eb812fd4	1418	}
JMF	0:24d3eb812fd4	1419
JMF	0:24d3eb812fd4	1420	MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, rxFrameFltReg);
JMF	0:24d3eb812fd4	1421	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, phyCtrl4Reg);
JMF	0:24d3eb812fd4	1422	}
JMF	0:24d3eb812fd4	1423
JMF	0:24d3eb812fd4	1424	/*
JMF	0:24d3eb812fd4	1425	* \brief Function used to switch XCVR power state.
JMF	0:24d3eb812fd4	1426	*
JMF	0:24d3eb812fd4	1427	* \param state The XCVR power mode
JMF	0:24d3eb812fd4	1428	*
JMF	0:24d3eb812fd4	1429	* \return none
JMF	0:24d3eb812fd4	1430	*/
JMF	0:24d3eb812fd4	1431	static void rf_set_power_state(xcvrPwrMode_t newState)
JMF	0:24d3eb812fd4	1432	{
JMF	0:24d3eb812fd4	1433	uint8_t pwrMode;
JMF	0:24d3eb812fd4	1434	uint8_t xtalState;
JMF	0:24d3eb812fd4	1435
JMF	0:24d3eb812fd4	1436	if( mPwrState == newState )
JMF	0:24d3eb812fd4	1437	{
JMF	0:24d3eb812fd4	1438	return;
JMF	0:24d3eb812fd4	1439	}
JMF	0:24d3eb812fd4	1440
JMF	0:24d3eb812fd4	1441	/* Read power settings from RF */
JMF	0:24d3eb812fd4	1442	pwrMode = MCR20Drv_DirectAccessSPIRead(PWR_MODES);
JMF	0:24d3eb812fd4	1443	xtalState = pwrMode & cPWR_MODES_XTALEN;
JMF	0:24d3eb812fd4	1444
JMF	0:24d3eb812fd4	1445	switch( newState )
JMF	0:24d3eb812fd4	1446	{
JMF	0:24d3eb812fd4	1447	case gXcvrPwrIdle_c:
JMF	0:24d3eb812fd4	1448	pwrMode &= ~(cPWR_MODES_AUTODOZE);
JMF	0:24d3eb812fd4	1449	pwrMode \|= (cPWR_MODES_XTALEN \| cPWR_MODES_PMC_MODE);
JMF	0:24d3eb812fd4	1450	break;
JMF	0:24d3eb812fd4	1451	case gXcvrPwrAutodoze_c:
JMF	0:24d3eb812fd4	1452	pwrMode \|= (cPWR_MODES_XTALEN \| cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
JMF	0:24d3eb812fd4	1453	break;
JMF	0:24d3eb812fd4	1454	case gXcvrPwrDoze_c:
JMF	0:24d3eb812fd4	1455	pwrMode &= ~(cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
JMF	0:24d3eb812fd4	1456	pwrMode \|= cPWR_MODES_XTALEN;
JMF	0:24d3eb812fd4	1457	break;
JMF	0:24d3eb812fd4	1458	case gXcvrPwrHibernate_c:
JMF	0:24d3eb812fd4	1459	pwrMode &= ~(cPWR_MODES_XTALEN \| cPWR_MODES_AUTODOZE \| cPWR_MODES_PMC_MODE);
JMF	0:24d3eb812fd4	1460	break;
JMF	0:24d3eb812fd4	1461	default:
JMF	0:24d3eb812fd4	1462	return;
JMF	0:24d3eb812fd4	1463	}
JMF	0:24d3eb812fd4	1464
JMF	0:24d3eb812fd4	1465	mPwrState = newState;
JMF	0:24d3eb812fd4	1466	MCR20Drv_DirectAccessSPIWrite(PWR_MODES, pwrMode);
JMF	0:24d3eb812fd4	1467
JMF	0:24d3eb812fd4	1468	if( !xtalState && (pwrMode & cPWR_MODES_XTALEN))
JMF	0:24d3eb812fd4	1469	{
JMF	0:24d3eb812fd4	1470	/* wait for crystal oscillator to complet its warmup */
JMF	0:24d3eb812fd4	1471	while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY);
JMF	0:24d3eb812fd4	1472	/* wait for radio wakeup from hibernate interrupt */
JMF	0:24d3eb812fd4	1473	while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ \| cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ \| cIRQSTS2_TMRSTATUS) );
JMF	0:24d3eb812fd4	1474
JMF	0:24d3eb812fd4	1475	MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ);
JMF	0:24d3eb812fd4	1476	}
JMF	0:24d3eb812fd4	1477	}
JMF	0:24d3eb812fd4	1478
JMF	0:24d3eb812fd4	1479	/*
JMF	0:24d3eb812fd4	1480	* \brief Function reads the energy level on the preselected channel.
JMF	0:24d3eb812fd4	1481	*
JMF	0:24d3eb812fd4	1482	* \return energy level
JMF	0:24d3eb812fd4	1483	*/
JMF	0:24d3eb812fd4	1484	static uint8_t rf_get_channel_energy(void)
JMF	0:24d3eb812fd4	1485	{
JMF	0:24d3eb812fd4	1486	uint8_t ccaMode;
JMF	0:24d3eb812fd4	1487
JMF	0:24d3eb812fd4	1488	MCR20Drv_IRQ_Disable();
JMF	0:24d3eb812fd4	1489	/* RX can start only from Idle state */
JMF	0:24d3eb812fd4	1490	if( mPhySeqState != gIdle_c )
JMF	0:24d3eb812fd4	1491	{
JMF	0:24d3eb812fd4	1492	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1493	return 0;
JMF	0:24d3eb812fd4	1494	}
JMF	0:24d3eb812fd4	1495
JMF	0:24d3eb812fd4	1496	/* Set XCVR power state in run mode */
JMF	0:24d3eb812fd4	1497	rf_set_power_state(gXcvrRunState_d);
JMF	0:24d3eb812fd4	1498
JMF	0:24d3eb812fd4	1499	/* Switch to ED mode */
JMF	0:24d3eb812fd4	1500	ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
JMF	0:24d3eb812fd4	1501	if( ccaMode != gCcaED_c )
JMF	0:24d3eb812fd4	1502	{
JMF	0:24d3eb812fd4	1503	mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
JMF	0:24d3eb812fd4	1504	mStatusAndControlRegs[PHY_CTRL4] \|= gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c;
JMF	0:24d3eb812fd4	1505	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
JMF	0:24d3eb812fd4	1506	}
JMF	0:24d3eb812fd4	1507
JMF	0:24d3eb812fd4	1508	/* Start ED sequence */
JMF	0:24d3eb812fd4	1509	mStatusAndControlRegs[PHY_CTRL1] \|= gCCA_c;
JMF	0:24d3eb812fd4	1510	MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ \| cIRQSTS1_SEQIRQ);
JMF	0:24d3eb812fd4	1511	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	1512	/* Wait for sequence to finish */
JMF	0:24d3eb812fd4	1513	while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
JMF	0:24d3eb812fd4	1514	/* Set XCVR to Idle */
JMF	0:24d3eb812fd4	1515	mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
JMF	0:24d3eb812fd4	1516	MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
JMF	0:24d3eb812fd4	1517	MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ \| cIRQSTS1_SEQIRQ);
JMF	0:24d3eb812fd4	1518
JMF	0:24d3eb812fd4	1519	MCR20Drv_IRQ_Enable();
JMF	0:24d3eb812fd4	1520
JMF	0:24d3eb812fd4	1521	return rf_convert_energy_level(MCR20Drv_DirectAccessSPIRead(CCA1_ED_FNL));
JMF	0:24d3eb812fd4	1522	}
JMF	0:24d3eb812fd4	1523
JMF	0:24d3eb812fd4	1524	/*
JMF	0:24d3eb812fd4	1525	* \brief Function converts the energy level from dBm to a 0-255 value.
JMF	0:24d3eb812fd4	1526	*
JMF	0:24d3eb812fd4	1527	* \param energyLevel in dBm
JMF	0:24d3eb812fd4	1528	*
JMF	0:24d3eb812fd4	1529	* \return energy level (0-255)
JMF	0:24d3eb812fd4	1530	*/
JMF	0:24d3eb812fd4	1531	static uint8_t rf_convert_energy_level(uint8_t energyLevel)
JMF	0:24d3eb812fd4	1532	{
JMF	0:24d3eb812fd4	1533	if(energyLevel >= 90)
JMF	0:24d3eb812fd4	1534	{
JMF	0:24d3eb812fd4	1535	/* ED value is below minimum. Return 0x00. */
JMF	0:24d3eb812fd4	1536	energyLevel = 0x00;
JMF	0:24d3eb812fd4	1537	}
JMF	0:24d3eb812fd4	1538	else if(energyLevel <= 26)
JMF	0:24d3eb812fd4	1539	{
JMF	0:24d3eb812fd4	1540	/* ED value is above maximum. Return 0xFF. */
JMF	0:24d3eb812fd4	1541	energyLevel = 0xFF;
JMF	0:24d3eb812fd4	1542	}
JMF	0:24d3eb812fd4	1543	else
JMF	0:24d3eb812fd4	1544	{
JMF	0:24d3eb812fd4	1545	/* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */
JMF	0:24d3eb812fd4	1546	energyLevel = (90 - energyLevel);
JMF	0:24d3eb812fd4	1547	/* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */
JMF	0:24d3eb812fd4	1548	/* energyLevel * 3.9844 ~= 4 */
JMF	0:24d3eb812fd4	1549	/* Multiply with 4=2^2 by shifting left.
JMF	0:24d3eb812fd4	1550	The multiplication will not overflow beacause energyLevel has values between 0 and 63 */
JMF	0:24d3eb812fd4	1551	energyLevel <<= 2;
JMF	0:24d3eb812fd4	1552	}
JMF	0:24d3eb812fd4	1553
JMF	0:24d3eb812fd4	1554	return energyLevel;
JMF	0:24d3eb812fd4	1555	}
JMF	0:24d3eb812fd4	1556
JMF	0:24d3eb812fd4	1557	static uint8_t rf_scale_lqi(int8_t rssi)
JMF	0:24d3eb812fd4	1558	{
JMF	0:24d3eb812fd4	1559	uint8_t scaled_lqi;
JMF	0:24d3eb812fd4	1560	/Worst case sensitivity/
JMF	0:24d3eb812fd4	1561	const int8_t rf_sensitivity = -98;
JMF	0:24d3eb812fd4	1562
JMF	0:24d3eb812fd4	1563	/rssi < RF sensitivity/
JMF	0:24d3eb812fd4	1564	if(rssi < rf_sensitivity)
JMF	0:24d3eb812fd4	1565	scaled_lqi=0;
JMF	0:24d3eb812fd4	1566	/-91 dBm < rssi < -81 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1567	/-90 dBm < rssi < -80 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1568	else if(rssi < (rf_sensitivity + 10))
JMF	0:24d3eb812fd4	1569	scaled_lqi=31;
JMF	0:24d3eb812fd4	1570	/-81 dBm < rssi < -71 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1571	/-80 dBm < rssi < -70 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1572	else if(rssi < (rf_sensitivity + 20))
JMF	0:24d3eb812fd4	1573	scaled_lqi=207;
JMF	0:24d3eb812fd4	1574	/-71 dBm < rssi < -61 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1575	/-70 dBm < rssi < -60 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1576	else if(rssi < (rf_sensitivity + 30))
JMF	0:24d3eb812fd4	1577	scaled_lqi=255;
JMF	0:24d3eb812fd4	1578	/-61 dBm < rssi < -51 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1579	/-60 dBm < rssi < -50 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1580	else if(rssi < (rf_sensitivity + 40))
JMF	0:24d3eb812fd4	1581	scaled_lqi=255;
JMF	0:24d3eb812fd4	1582	/-51 dBm < rssi < -41 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1583	/-50 dBm < rssi < -40 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1584	else if(rssi < (rf_sensitivity + 50))
JMF	0:24d3eb812fd4	1585	scaled_lqi=255;
JMF	0:24d3eb812fd4	1586	/-41 dBm < rssi < -31 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1587	/-40 dBm < rssi < -30 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1588	else if(rssi < (rf_sensitivity + 60))
JMF	0:24d3eb812fd4	1589	scaled_lqi=255;
JMF	0:24d3eb812fd4	1590	/-31 dBm < rssi < -21 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1591	/-30 dBm < rssi < -20 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1592	else if(rssi < (rf_sensitivity + 70))
JMF	0:24d3eb812fd4	1593	scaled_lqi=255;
JMF	0:24d3eb812fd4	1594	/rssi > RF saturation/
JMF	0:24d3eb812fd4	1595	else if(rssi > (rf_sensitivity + 80))
JMF	0:24d3eb812fd4	1596	scaled_lqi=111;
JMF	0:24d3eb812fd4	1597	/-21 dBm < rssi < -11 dBm (AT86RF233 XPro)/
JMF	0:24d3eb812fd4	1598	/-20 dBm < rssi < -10 dBm (AT86RF212B XPro)/
JMF	0:24d3eb812fd4	1599	else
JMF	0:24d3eb812fd4	1600	scaled_lqi=255;
JMF	0:24d3eb812fd4	1601
JMF	0:24d3eb812fd4	1602	return scaled_lqi;
JMF	0:24d3eb812fd4	1603	}
JMF	0:24d3eb812fd4	1604
JMF	0:24d3eb812fd4	1605
JMF	0:24d3eb812fd4	1606	/*****************************************************************************/
JMF	0:24d3eb812fd4	1607	/* Layer porting to the Freescale driver */
JMF	0:24d3eb812fd4	1608	/*****************************************************************************/
JMF	0:24d3eb812fd4	1609	extern "C" void xcvr_spi_init(uint32_t instance)
JMF	0:24d3eb812fd4	1610	{
JMF	0:24d3eb812fd4	1611	(void)instance;
JMF	0:24d3eb812fd4	1612	}
JMF	0:24d3eb812fd4	1613
JMF	0:24d3eb812fd4	1614	extern "C" void RF_IRQ_Init(void) {
JMF	0:24d3eb812fd4	1615	MBED_ASSERT(irq != NULL);
JMF	0:24d3eb812fd4	1616	irq->mode(PullUp);
JMF	0:24d3eb812fd4	1617	irq->fall(&PHY_InterruptHandler);
JMF	0:24d3eb812fd4	1618	}
JMF	0:24d3eb812fd4	1619
JMF	0:24d3eb812fd4	1620	extern "C" void RF_IRQ_Enable(void) {
JMF	0:24d3eb812fd4	1621	MBED_ASSERT(irq != NULL);
JMF	0:24d3eb812fd4	1622	irq->enable_irq();
JMF	0:24d3eb812fd4	1623	}
JMF	0:24d3eb812fd4	1624
JMF	0:24d3eb812fd4	1625	extern "C" void RF_IRQ_Disable(void) {
JMF	0:24d3eb812fd4	1626	MBED_ASSERT(irq != NULL);
JMF	0:24d3eb812fd4	1627	irq->disable_irq();
JMF	0:24d3eb812fd4	1628	}
JMF	0:24d3eb812fd4	1629
JMF	0:24d3eb812fd4	1630	extern "C" uint8_t RF_isIRQ_Pending(void) {
JMF	0:24d3eb812fd4	1631	MBED_ASSERT(rf != NULL);
JMF	0:24d3eb812fd4	1632	return !irq_pin->read();
JMF	0:24d3eb812fd4	1633	}
JMF	0:24d3eb812fd4	1634
JMF	0:24d3eb812fd4	1635	extern "C" void RF_RST_Set(int state) {
JMF	0:24d3eb812fd4	1636	MBED_ASSERT(rst != NULL);
JMF	0:24d3eb812fd4	1637	*rst = state;
JMF	0:24d3eb812fd4	1638	}
JMF	0:24d3eb812fd4	1639
JMF	0:24d3eb812fd4	1640	extern "C" void gXcvrAssertCS_d(void)
JMF	0:24d3eb812fd4	1641	{
JMF	0:24d3eb812fd4	1642	MBED_ASSERT(cs != NULL);
JMF	0:24d3eb812fd4	1643	*cs = 0;
JMF	0:24d3eb812fd4	1644	}
JMF	0:24d3eb812fd4	1645
JMF	0:24d3eb812fd4	1646	extern "C" void gXcvrDeassertCS_d(void)
JMF	0:24d3eb812fd4	1647	{
JMF	0:24d3eb812fd4	1648	MBED_ASSERT(cs != NULL);
JMF	0:24d3eb812fd4	1649	*cs = 1;
JMF	0:24d3eb812fd4	1650	}
JMF	0:24d3eb812fd4	1651
JMF	0:24d3eb812fd4	1652	extern "C" void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq)
JMF	0:24d3eb812fd4	1653	{
JMF	0:24d3eb812fd4	1654	MBED_ASSERT(spi != NULL);
JMF	0:24d3eb812fd4	1655	(void)instance;
JMF	0:24d3eb812fd4	1656	spi->frequency(freq);
JMF	0:24d3eb812fd4	1657	}
JMF	0:24d3eb812fd4	1658
JMF	0:24d3eb812fd4	1659	extern "C" void xcvr_spi_transfer(uint32_t instance,
JMF	0:24d3eb812fd4	1660	uint8_t * sendBuffer,
JMF	0:24d3eb812fd4	1661	uint8_t * receiveBuffer,
JMF	0:24d3eb812fd4	1662	size_t transferByteCount)
JMF	0:24d3eb812fd4	1663	{
JMF	0:24d3eb812fd4	1664	MBED_ASSERT(spi != NULL);
JMF	0:24d3eb812fd4	1665	(void)instance;
JMF	0:24d3eb812fd4	1666	volatile uint8_t dummy;
JMF	0:24d3eb812fd4	1667
JMF	0:24d3eb812fd4	1668	if( !transferByteCount )
JMF	0:24d3eb812fd4	1669	return;
JMF	0:24d3eb812fd4	1670
JMF	0:24d3eb812fd4	1671	if( !sendBuffer && !receiveBuffer )
JMF	0:24d3eb812fd4	1672	return;
JMF	0:24d3eb812fd4	1673
JMF	0:24d3eb812fd4	1674	while( transferByteCount-- )
JMF	0:24d3eb812fd4	1675	{
JMF	0:24d3eb812fd4	1676	if( sendBuffer )
JMF	0:24d3eb812fd4	1677	{
JMF	0:24d3eb812fd4	1678	dummy = *sendBuffer;
JMF	0:24d3eb812fd4	1679	sendBuffer++;
JMF	0:24d3eb812fd4	1680	}
JMF	0:24d3eb812fd4	1681	else
JMF	0:24d3eb812fd4	1682	{
JMF	0:24d3eb812fd4	1683	dummy = 0xFF;
JMF	0:24d3eb812fd4	1684	}
JMF	0:24d3eb812fd4	1685
JMF	0:24d3eb812fd4	1686	dummy = spi->write(dummy);
JMF	0:24d3eb812fd4	1687
JMF	0:24d3eb812fd4	1688	if( receiveBuffer )
JMF	0:24d3eb812fd4	1689	{
JMF	0:24d3eb812fd4	1690	*receiveBuffer = dummy;
JMF	0:24d3eb812fd4	1691	receiveBuffer++;
JMF	0:24d3eb812fd4	1692	}
JMF	0:24d3eb812fd4	1693	}
JMF	0:24d3eb812fd4	1694	}
JMF	0:24d3eb812fd4	1695
JMF	0:24d3eb812fd4	1696	/*****************************************************************************/
JMF	0:24d3eb812fd4	1697	/*****************************************************************************/
JMF	0:24d3eb812fd4	1698
JMF	0:24d3eb812fd4	1699	static void rf_if_lock(void)
JMF	0:24d3eb812fd4	1700	{
JMF	0:24d3eb812fd4	1701	platform_enter_critical();
JMF	0:24d3eb812fd4	1702	}
JMF	0:24d3eb812fd4	1703
JMF	0:24d3eb812fd4	1704	static void rf_if_unlock(void)
JMF	0:24d3eb812fd4	1705	{
JMF	0:24d3eb812fd4	1706	platform_exit_critical();
JMF	0:24d3eb812fd4	1707	}
JMF	0:24d3eb812fd4	1708
JMF	0:24d3eb812fd4	1709	NanostackRfPhyMcr20a::NanostackRfPhyMcr20a(PinName spi_mosi, PinName spi_miso,
JMF	0:24d3eb812fd4	1710	PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_irq)
JMF	0:24d3eb812fd4	1711	: _spi(spi_mosi, spi_miso, spi_sclk), _rf_cs(spi_cs), _rf_rst(spi_rst, 1),
JMF	0:24d3eb812fd4	1712	_rf_irq(spi_irq), _rf_irq_pin(spi_irq),
JMF	0:24d3eb812fd4	1713	_irq_thread(osPriorityRealtime, 1024)
JMF	0:24d3eb812fd4	1714	{
JMF	0:24d3eb812fd4	1715	char mac48[6];
JMF	0:24d3eb812fd4	1716	mbed_mac_address(mac48);
JMF	0:24d3eb812fd4	1717
JMF	0:24d3eb812fd4	1718	MAC_address[0] = mac48[0];
JMF	0:24d3eb812fd4	1719	MAC_address[1] = mac48[1];
JMF	0:24d3eb812fd4	1720	MAC_address[2] = mac48[2];
JMF	0:24d3eb812fd4	1721	MAC_address[3] = 0xFF;
JMF	0:24d3eb812fd4	1722	MAC_address[4] = 0xFF;
JMF	0:24d3eb812fd4	1723	MAC_address[5] = mac48[3];
JMF	0:24d3eb812fd4	1724	MAC_address[6] = mac48[4];
JMF	0:24d3eb812fd4	1725	MAC_address[7] = mac48[5];
JMF	0:24d3eb812fd4	1726	}
JMF	0:24d3eb812fd4	1727
JMF	0:24d3eb812fd4	1728	NanostackRfPhyMcr20a::~NanostackRfPhyMcr20a()
JMF	0:24d3eb812fd4	1729	{
JMF	0:24d3eb812fd4	1730	// Do nothing
JMF	0:24d3eb812fd4	1731	}
JMF	0:24d3eb812fd4	1732
JMF	0:24d3eb812fd4	1733	int8_t NanostackRfPhyMcr20a::rf_register()
JMF	0:24d3eb812fd4	1734	{
JMF	0:24d3eb812fd4	1735
JMF	0:24d3eb812fd4	1736	rf_if_lock();
JMF	0:24d3eb812fd4	1737
JMF	0:24d3eb812fd4	1738	if (rf != NULL) {
JMF	0:24d3eb812fd4	1739	rf_if_unlock();
JMF	0:24d3eb812fd4	1740	error("Multiple registrations of NanostackRfPhyMcr20a not supported");
JMF	0:24d3eb812fd4	1741	return -1;
JMF	0:24d3eb812fd4	1742	}
JMF	0:24d3eb812fd4	1743
JMF	0:24d3eb812fd4	1744	_irq_thread.start(mbed::callback(PHY_InterruptThread));
JMF	0:24d3eb812fd4	1745
JMF	0:24d3eb812fd4	1746	_pins_set();
JMF	0:24d3eb812fd4	1747	int8_t radio_id = rf_device_register();
JMF	0:24d3eb812fd4	1748	if (radio_id < 0) {
JMF	0:24d3eb812fd4	1749	_pins_clear();
JMF	0:24d3eb812fd4	1750	rf = NULL;
JMF	0:24d3eb812fd4	1751	}
JMF	0:24d3eb812fd4	1752
JMF	0:24d3eb812fd4	1753	rf_if_unlock();
JMF	0:24d3eb812fd4	1754	return radio_id;
JMF	0:24d3eb812fd4	1755	}
JMF	0:24d3eb812fd4	1756
JMF	0:24d3eb812fd4	1757	void NanostackRfPhyMcr20a::rf_unregister()
JMF	0:24d3eb812fd4	1758	{
JMF	0:24d3eb812fd4	1759	rf_if_lock();
JMF	0:24d3eb812fd4	1760
JMF	0:24d3eb812fd4	1761	if (rf != this) {
JMF	0:24d3eb812fd4	1762	rf_if_unlock();
JMF	0:24d3eb812fd4	1763	return;
JMF	0:24d3eb812fd4	1764	}
JMF	0:24d3eb812fd4	1765
JMF	0:24d3eb812fd4	1766	rf_device_unregister();
JMF	0:24d3eb812fd4	1767	rf = NULL;
JMF	0:24d3eb812fd4	1768	_pins_clear();
JMF	0:24d3eb812fd4	1769
JMF	0:24d3eb812fd4	1770	rf_if_unlock();
JMF	0:24d3eb812fd4	1771	}
JMF	0:24d3eb812fd4	1772
JMF	0:24d3eb812fd4	1773	void NanostackRfPhyMcr20a::get_mac_address(uint8_t *mac)
JMF	0:24d3eb812fd4	1774	{
JMF	0:24d3eb812fd4	1775	rf_if_lock();
JMF	0:24d3eb812fd4	1776
JMF	0:24d3eb812fd4	1777	memcpy((void)mac, (void)MAC_address, sizeof(MAC_address));
JMF	0:24d3eb812fd4	1778
JMF	0:24d3eb812fd4	1779	rf_if_unlock();
JMF	0:24d3eb812fd4	1780	}
JMF	0:24d3eb812fd4	1781
JMF	0:24d3eb812fd4	1782	void NanostackRfPhyMcr20a::set_mac_address(uint8_t *mac)
JMF	0:24d3eb812fd4	1783	{
JMF	0:24d3eb812fd4	1784	rf_if_lock();
JMF	0:24d3eb812fd4	1785
JMF	0:24d3eb812fd4	1786	if (NULL != rf) {
JMF	0:24d3eb812fd4	1787	error("NanostackRfPhyAtmel cannot change mac address when running");
JMF	0:24d3eb812fd4	1788	rf_if_unlock();
JMF	0:24d3eb812fd4	1789	return;
JMF	0:24d3eb812fd4	1790	}
JMF	0:24d3eb812fd4	1791	memcpy((void)MAC_address, (void)mac, sizeof(MAC_address));
JMF	0:24d3eb812fd4	1792
JMF	0:24d3eb812fd4	1793	rf_if_unlock();
JMF	0:24d3eb812fd4	1794	}
JMF	0:24d3eb812fd4	1795
JMF	0:24d3eb812fd4	1796	void NanostackRfPhyMcr20a::_pins_set()
JMF	0:24d3eb812fd4	1797	{
JMF	0:24d3eb812fd4	1798	spi = &_spi;
JMF	0:24d3eb812fd4	1799	cs = &_rf_cs;
JMF	0:24d3eb812fd4	1800	rst = &_rf_rst;
JMF	0:24d3eb812fd4	1801	irq = &_rf_irq;
JMF	0:24d3eb812fd4	1802	irq_pin = &_rf_irq_pin;
JMF	0:24d3eb812fd4	1803	irq_thread = &_irq_thread;
JMF	0:24d3eb812fd4	1804	}
JMF	0:24d3eb812fd4	1805
JMF	0:24d3eb812fd4	1806	void NanostackRfPhyMcr20a::_pins_clear()
JMF	0:24d3eb812fd4	1807	{
JMF	0:24d3eb812fd4	1808	spi = NULL;
JMF	0:24d3eb812fd4	1809	cs = NULL;
JMF	0:24d3eb812fd4	1810	rst = NULL;
JMF	0:24d3eb812fd4	1811	irq = NULL;
JMF	0:24d3eb812fd4	1812	irq_pin = NULL;
JMF	0:24d3eb812fd4	1813	irq_thread = NULL;
JMF	0:24d3eb812fd4	1814	}
JMF	0:24d3eb812fd4	1815
JMF	0:24d3eb812fd4	1816	#if MBED_CONF_MCR20A_PROVIDE_DEFAULT \|\| DEVICE_MCR20A
JMF	0:24d3eb812fd4	1817
JMF	0:24d3eb812fd4	1818	NanostackRfPhy &NanostackRfPhy::get_default_instance()
JMF	0:24d3eb812fd4	1819	{
JMF	0:24d3eb812fd4	1820	static NanostackRfPhyMcr20a rf_phy(MCR20A_SPI_MOSI, MCR20A_SPI_MISO, MCR20A_SPI_SCLK, MCR20A_SPI_CS, MCR20A_SPI_RST, MCR20A_SPI_IRQ);
JMF	0:24d3eb812fd4	1821	return rf_phy;
JMF	0:24d3eb812fd4	1822	}
JMF	0:24d3eb812fd4	1823
JMF	0:24d3eb812fd4	1824	#endif // MBED_CONF_MCR20A_PROVIDE_DEFAULT
JMF	0:24d3eb812fd4	1825
JMF	0:24d3eb812fd4	1826	#endif // MBED_CONF_NANOSTACK_CONFIGURATION

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Type:	Program
Mbed OS support:	Mbed OS
Created:	05 Sep 2018
Imports:	5
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	2
Followers:	1

easy-connect/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp@0:24d3eb812fd4, 2018-09-05 (annotated)

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