Jim Flynn / Mbed OS wifi_Example

wifi test

Dependencies:   X_NUCLEO_IKS01A2 mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Reg.h@0:24d3eb812fd4, 2018-09-05 (annotated)

Committer:
JMF
Date:
Wed Sep 05 14:28:24 2018 +0000
Revision:
0:24d3eb812fd4
Initial commit

Who changed what in which revision?

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JMF 0:24d3eb812fd4 1 /*!
JMF 0:24d3eb812fd4 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
JMF 0:24d3eb812fd4 3 * All rights reserved.
JMF 0:24d3eb812fd4 4 *
JMF 0:24d3eb812fd4 5 * \file MCR20reg.h
JMF 0:24d3eb812fd4 6 * MCR20 Registers
JMF 0:24d3eb812fd4 7 *
JMF 0:24d3eb812fd4 8 * Redistribution and use in source and binary forms, with or without modification,
JMF 0:24d3eb812fd4 9 * are permitted provided that the following conditions are met:
JMF 0:24d3eb812fd4 10 *
JMF 0:24d3eb812fd4 11 * o Redistributions of source code must retain the above copyright notice, this list
JMF 0:24d3eb812fd4 12 * of conditions and the following disclaimer.
JMF 0:24d3eb812fd4 13 *
JMF 0:24d3eb812fd4 14 * o Redistributions in binary form must reproduce the above copyright notice, this
JMF 0:24d3eb812fd4 15 * list of conditions and the following disclaimer in the documentation and/or
JMF 0:24d3eb812fd4 16 * other materials provided with the distribution.
JMF 0:24d3eb812fd4 17 *
JMF 0:24d3eb812fd4 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
JMF 0:24d3eb812fd4 19 * contributors may be used to endorse or promote products derived from this
JMF 0:24d3eb812fd4 20 * software without specific prior written permission.
JMF 0:24d3eb812fd4 21 *
JMF 0:24d3eb812fd4 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
JMF 0:24d3eb812fd4 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
JMF 0:24d3eb812fd4 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
JMF 0:24d3eb812fd4 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
JMF 0:24d3eb812fd4 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
JMF 0:24d3eb812fd4 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
JMF 0:24d3eb812fd4 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
JMF 0:24d3eb812fd4 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
JMF 0:24d3eb812fd4 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
JMF 0:24d3eb812fd4 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
JMF 0:24d3eb812fd4 32 */
JMF 0:24d3eb812fd4 33
JMF 0:24d3eb812fd4 34 #ifndef __MCR20_REG_H__
JMF 0:24d3eb812fd4 35 #define __MCR20_REG_H__
JMF 0:24d3eb812fd4 36 /*****************************************************************************
JMF 0:24d3eb812fd4 37 * INCLUDED HEADERS *
JMF 0:24d3eb812fd4 38 *---------------------------------------------------------------------------*
JMF 0:24d3eb812fd4 39 * Add to this section all the headers that this module needs to include. *
JMF 0:24d3eb812fd4 40 * Note that it is not a good practice to include header files into header *
JMF 0:24d3eb812fd4 41 * files, so use this section only if there is no other better solution. *
JMF 0:24d3eb812fd4 42 *---------------------------------------------------------------------------*
JMF 0:24d3eb812fd4 43 *****************************************************************************/
JMF 0:24d3eb812fd4 44
JMF 0:24d3eb812fd4 45 /****************************************************************************/
JMF 0:24d3eb812fd4 46 /* Transceiver SPI Registers */
JMF 0:24d3eb812fd4 47 /****************************************************************************/
JMF 0:24d3eb812fd4 48
JMF 0:24d3eb812fd4 49 #define TransceiverSPI_IARIndexReg (0x3E)
JMF 0:24d3eb812fd4 50
JMF 0:24d3eb812fd4 51 #define TransceiverSPI_ReadSelect (1<<7)
JMF 0:24d3eb812fd4 52 #define TransceiverSPI_WriteSelect (0<<7)
JMF 0:24d3eb812fd4 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
JMF 0:24d3eb812fd4 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
JMF 0:24d3eb812fd4 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
JMF 0:24d3eb812fd4 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
JMF 0:24d3eb812fd4 57
JMF 0:24d3eb812fd4 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
JMF 0:24d3eb812fd4 59
JMF 0:24d3eb812fd4 60 #define IRQSTS1 0x00
JMF 0:24d3eb812fd4 61 #define IRQSTS2 0x01
JMF 0:24d3eb812fd4 62 #define IRQSTS3 0x02
JMF 0:24d3eb812fd4 63 #define PHY_CTRL1 0x03
JMF 0:24d3eb812fd4 64 #define PHY_CTRL2 0x04
JMF 0:24d3eb812fd4 65 #define PHY_CTRL3 0x05
JMF 0:24d3eb812fd4 66 #define RX_FRM_LEN 0x06
JMF 0:24d3eb812fd4 67 #define PHY_CTRL4 0x07
JMF 0:24d3eb812fd4 68 #define SRC_CTRL 0x08
JMF 0:24d3eb812fd4 69 #define SRC_ADDRS_SUM_LSB 0x09
JMF 0:24d3eb812fd4 70 #define SRC_ADDRS_SUM_MSB 0x0A
JMF 0:24d3eb812fd4 71 #define CCA1_ED_FNL 0x0B
JMF 0:24d3eb812fd4 72 #define EVENT_TMR_LSB 0x0C
JMF 0:24d3eb812fd4 73 #define EVENT_TMR_MSB 0x0D
JMF 0:24d3eb812fd4 74 #define EVENT_TMR_USB 0x0E
JMF 0:24d3eb812fd4 75 #define TIMESTAMP_LSB 0x0F
JMF 0:24d3eb812fd4 76 #define TIMESTAMP_MSB 0x10
JMF 0:24d3eb812fd4 77 #define TIMESTAMP_USB 0x11
JMF 0:24d3eb812fd4 78 #define T3CMP_LSB 0x12
JMF 0:24d3eb812fd4 79 #define T3CMP_MSB 0x13
JMF 0:24d3eb812fd4 80 #define T3CMP_USB 0x14
JMF 0:24d3eb812fd4 81 #define T2PRIMECMP_LSB 0x15
JMF 0:24d3eb812fd4 82 #define T2PRIMECMP_MSB 0x16
JMF 0:24d3eb812fd4 83 #define T1CMP_LSB 0x17
JMF 0:24d3eb812fd4 84 #define T1CMP_MSB 0x18
JMF 0:24d3eb812fd4 85 #define T1CMP_USB 0x19
JMF 0:24d3eb812fd4 86 #define T2CMP_LSB 0x1A
JMF 0:24d3eb812fd4 87 #define T2CMP_MSB 0x1B
JMF 0:24d3eb812fd4 88 #define T2CMP_USB 0x1C
JMF 0:24d3eb812fd4 89 #define T4CMP_LSB 0x1D
JMF 0:24d3eb812fd4 90 #define T4CMP_MSB 0x1E
JMF 0:24d3eb812fd4 91 #define T4CMP_USB 0x1F
JMF 0:24d3eb812fd4 92 #define PLL_INT0 0x20
JMF 0:24d3eb812fd4 93 #define PLL_FRAC0_LSB 0x21
JMF 0:24d3eb812fd4 94 #define PLL_FRAC0_MSB 0x22
JMF 0:24d3eb812fd4 95 #define PA_PWR 0x23
JMF 0:24d3eb812fd4 96 #define SEQ_STATE 0x24
JMF 0:24d3eb812fd4 97 #define LQI_VALUE 0x25
JMF 0:24d3eb812fd4 98 #define RSSI_CCA_CONT 0x26
JMF 0:24d3eb812fd4 99 //-------------- 0x27
JMF 0:24d3eb812fd4 100 #define ASM_CTRL1 0x28
JMF 0:24d3eb812fd4 101 #define ASM_CTRL2 0x29
JMF 0:24d3eb812fd4 102 #define ASM_DATA_0 0x2A
JMF 0:24d3eb812fd4 103 #define ASM_DATA_1 0x2B
JMF 0:24d3eb812fd4 104 #define ASM_DATA_2 0x2C
JMF 0:24d3eb812fd4 105 #define ASM_DATA_3 0x2D
JMF 0:24d3eb812fd4 106 #define ASM_DATA_4 0x2E
JMF 0:24d3eb812fd4 107 #define ASM_DATA_5 0x2F
JMF 0:24d3eb812fd4 108 #define ASM_DATA_6 0x30
JMF 0:24d3eb812fd4 109 #define ASM_DATA_7 0x31
JMF 0:24d3eb812fd4 110 #define ASM_DATA_8 0x32
JMF 0:24d3eb812fd4 111 #define ASM_DATA_9 0x33
JMF 0:24d3eb812fd4 112 #define ASM_DATA_A 0x34
JMF 0:24d3eb812fd4 113 #define ASM_DATA_B 0x35
JMF 0:24d3eb812fd4 114 #define ASM_DATA_C 0x36
JMF 0:24d3eb812fd4 115 #define ASM_DATA_D 0x37
JMF 0:24d3eb812fd4 116 #define ASM_DATA_E 0x38
JMF 0:24d3eb812fd4 117 #define ASM_DATA_F 0x39
JMF 0:24d3eb812fd4 118 //------------------- 0x3A
JMF 0:24d3eb812fd4 119 #define OVERWRITE_VER 0x3B
JMF 0:24d3eb812fd4 120 #define CLK_OUT_CTRL 0x3C
JMF 0:24d3eb812fd4 121 #define PWR_MODES 0x3D
JMF 0:24d3eb812fd4 122 #define IAR_INDEX 0x3E
JMF 0:24d3eb812fd4 123 #define IAR_DATA 0x3F
JMF 0:24d3eb812fd4 124
JMF 0:24d3eb812fd4 125
JMF 0:24d3eb812fd4 126 #define PART_ID 0x00
JMF 0:24d3eb812fd4 127 #define XTAL_TRIM 0x01
JMF 0:24d3eb812fd4 128 #define PMC_LP_TRIM 0x02
JMF 0:24d3eb812fd4 129 #define MACPANID0_LSB 0x03
JMF 0:24d3eb812fd4 130 #define MACPANID0_MSB 0x04
JMF 0:24d3eb812fd4 131 #define MACSHORTADDRS0_LSB 0x05
JMF 0:24d3eb812fd4 132 #define MACSHORTADDRS0_MSB 0x06
JMF 0:24d3eb812fd4 133 #define MACLONGADDRS0_0 0x07
JMF 0:24d3eb812fd4 134 #define MACLONGADDRS0_8 0x08
JMF 0:24d3eb812fd4 135 #define MACLONGADDRS0_16 0x09
JMF 0:24d3eb812fd4 136 #define MACLONGADDRS0_24 0x0A
JMF 0:24d3eb812fd4 137 #define MACLONGADDRS0_32 0x0B
JMF 0:24d3eb812fd4 138 #define MACLONGADDRS0_40 0x0C
JMF 0:24d3eb812fd4 139 #define MACLONGADDRS0_48 0x0D
JMF 0:24d3eb812fd4 140 #define MACLONGADDRS0_56 0x0E
JMF 0:24d3eb812fd4 141 #define RX_FRAME_FILTER 0x0F
JMF 0:24d3eb812fd4 142 #define PLL_INT1 0x10
JMF 0:24d3eb812fd4 143 #define PLL_FRAC1_LSB 0x11
JMF 0:24d3eb812fd4 144 #define PLL_FRAC1_MSB 0x12
JMF 0:24d3eb812fd4 145 #define MACPANID1_LSB 0x13
JMF 0:24d3eb812fd4 146 #define MACPANID1_MSB 0x14
JMF 0:24d3eb812fd4 147 #define MACSHORTADDRS1_LSB 0x15
JMF 0:24d3eb812fd4 148 #define MACSHORTADDRS1_MSB 0x16
JMF 0:24d3eb812fd4 149 #define MACLONGADDRS1_0 0x17
JMF 0:24d3eb812fd4 150 #define MACLONGADDRS1_8 0x18
JMF 0:24d3eb812fd4 151 #define MACLONGADDRS1_16 0x19
JMF 0:24d3eb812fd4 152 #define MACLONGADDRS1_24 0x1A
JMF 0:24d3eb812fd4 153 #define MACLONGADDRS1_32 0x1B
JMF 0:24d3eb812fd4 154 #define MACLONGADDRS1_40 0x1C
JMF 0:24d3eb812fd4 155 #define MACLONGADDRS1_48 0x1D
JMF 0:24d3eb812fd4 156 #define MACLONGADDRS1_56 0x1E
JMF 0:24d3eb812fd4 157 #define DUAL_PAN_CTRL 0x1F
JMF 0:24d3eb812fd4 158 #define DUAL_PAN_DWELL 0x20
JMF 0:24d3eb812fd4 159 #define DUAL_PAN_STS 0x21
JMF 0:24d3eb812fd4 160 #define CCA1_THRESH 0x22
JMF 0:24d3eb812fd4 161 #define CCA1_ED_OFFSET_COMP 0x23
JMF 0:24d3eb812fd4 162 #define LQI_OFFSET_COMP 0x24
JMF 0:24d3eb812fd4 163 #define CCA_CTRL 0x25
JMF 0:24d3eb812fd4 164 #define CCA2_CORR_PEAKS 0x26
JMF 0:24d3eb812fd4 165 #define CCA2_CORR_THRESH 0x27
JMF 0:24d3eb812fd4 166 #define TMR_PRESCALE 0x28
JMF 0:24d3eb812fd4 167 //---------------- 0x29
JMF 0:24d3eb812fd4 168 #define GPIO_DATA 0x2A
JMF 0:24d3eb812fd4 169 #define GPIO_DIR 0x2B
JMF 0:24d3eb812fd4 170 #define GPIO_PUL_EN 0x2C
JMF 0:24d3eb812fd4 171 #define GPIO_PUL_SEL 0x2D
JMF 0:24d3eb812fd4 172 #define GPIO_DS 0x2E
JMF 0:24d3eb812fd4 173 //-------------- 0x2F
JMF 0:24d3eb812fd4 174 #define ANT_PAD_CTRL 0x30
JMF 0:24d3eb812fd4 175 #define MISC_PAD_CTRL 0x31
JMF 0:24d3eb812fd4 176 #define BSM_CTRL 0x32
JMF 0:24d3eb812fd4 177 //--------------- 0x33
JMF 0:24d3eb812fd4 178 #define _RNG 0x34
JMF 0:24d3eb812fd4 179 #define RX_BYTE_COUNT 0x35
JMF 0:24d3eb812fd4 180 #define RX_WTR_MARK 0x36
JMF 0:24d3eb812fd4 181 #define SOFT_RESET 0x37
JMF 0:24d3eb812fd4 182 #define TXDELAY 0x38
JMF 0:24d3eb812fd4 183 #define ACKDELAY 0x39
JMF 0:24d3eb812fd4 184 #define SEQ_MGR_CTRL 0x3A
JMF 0:24d3eb812fd4 185 #define SEQ_MGR_STS 0x3B
JMF 0:24d3eb812fd4 186 #define SEQ_T_STS 0x3C
JMF 0:24d3eb812fd4 187 #define ABORT_STS 0x3D
JMF 0:24d3eb812fd4 188 #define CCCA_BUSY_CNT 0x3E
JMF 0:24d3eb812fd4 189 #define SRC_ADDR_CHECKSUM1 0x3F
JMF 0:24d3eb812fd4 190 #define SRC_ADDR_CHECKSUM2 0x40
JMF 0:24d3eb812fd4 191 #define SRC_TBL_VALID1 0x41
JMF 0:24d3eb812fd4 192 #define SRC_TBL_VALID2 0x42
JMF 0:24d3eb812fd4 193 #define FILTERFAIL_CODE1 0x43
JMF 0:24d3eb812fd4 194 #define FILTERFAIL_CODE2 0x44
JMF 0:24d3eb812fd4 195 #define SLOT_PRELOAD 0x45
JMF 0:24d3eb812fd4 196 //---------------- 0x46
JMF 0:24d3eb812fd4 197 #define CORR_VT 0x47
JMF 0:24d3eb812fd4 198 #define SYNC_CTRL 0x48
JMF 0:24d3eb812fd4 199 #define PN_LSB_0 0x49
JMF 0:24d3eb812fd4 200 #define PN_LSB_1 0x4A
JMF 0:24d3eb812fd4 201 #define PN_MSB_0 0x4B
JMF 0:24d3eb812fd4 202 #define PN_MSB_1 0x4C
JMF 0:24d3eb812fd4 203 #define CORR_NVAL 0x4D
JMF 0:24d3eb812fd4 204 #define TX_MODE_CTRL 0x4E
JMF 0:24d3eb812fd4 205 #define SNF_THR 0x4F
JMF 0:24d3eb812fd4 206 #define FAD_THR 0x50
JMF 0:24d3eb812fd4 207 #define ANT_AGC_CTRL 0x51
JMF 0:24d3eb812fd4 208 #define AGC_THR1 0x52
JMF 0:24d3eb812fd4 209 #define AGC_THR2 0x53
JMF 0:24d3eb812fd4 210 #define AGC_HYS 0x54
JMF 0:24d3eb812fd4 211 #define AFC 0x55
JMF 0:24d3eb812fd4 212 //--------------- 0x56
JMF 0:24d3eb812fd4 213 //--------------- 0x57
JMF 0:24d3eb812fd4 214 #define PHY_STS 0x58
JMF 0:24d3eb812fd4 215 #define RX_MAX_CORR 0x59
JMF 0:24d3eb812fd4 216 #define RX_MAX_PREAMBLE 0x5A
JMF 0:24d3eb812fd4 217 #define RSSI 0x5B
JMF 0:24d3eb812fd4 218 //--------------- 0x5C
JMF 0:24d3eb812fd4 219 //--------------- 0x5D
JMF 0:24d3eb812fd4 220 #define PLL_DIG_CTRL 0x5E
JMF 0:24d3eb812fd4 221 #define VCO_CAL 0x5F
JMF 0:24d3eb812fd4 222 #define VCO_BEST_DIFF 0x60
JMF 0:24d3eb812fd4 223 #define VCO_BIAS 0x61
JMF 0:24d3eb812fd4 224 #define KMOD_CTRL 0x62
JMF 0:24d3eb812fd4 225 #define KMOD_CAL 0x63
JMF 0:24d3eb812fd4 226 #define PA_CAL 0x64
JMF 0:24d3eb812fd4 227 #define PA_PWRCAL 0x65
JMF 0:24d3eb812fd4 228 #define ATT_RSSI1 0x66
JMF 0:24d3eb812fd4 229 #define ATT_RSSI2 0x67
JMF 0:24d3eb812fd4 230 #define RSSI_OFFSET 0x68
JMF 0:24d3eb812fd4 231 #define RSSI_SLOPE 0x69
JMF 0:24d3eb812fd4 232 #define RSSI_CAL1 0x6A
JMF 0:24d3eb812fd4 233 #define RSSI_CAL2 0x6B
JMF 0:24d3eb812fd4 234 //--------------- 0x6C
JMF 0:24d3eb812fd4 235 //--------------- 0x6D
JMF 0:24d3eb812fd4 236 #define XTAL_CTRL 0x6E
JMF 0:24d3eb812fd4 237 #define XTAL_COMP_MIN 0x6F
JMF 0:24d3eb812fd4 238 #define XTAL_COMP_MAX 0x70
JMF 0:24d3eb812fd4 239 #define XTAL_GM 0x71
JMF 0:24d3eb812fd4 240 //--------------- 0x72
JMF 0:24d3eb812fd4 241 //--------------- 0x73
JMF 0:24d3eb812fd4 242 #define LNA_TUNE 0x74
JMF 0:24d3eb812fd4 243 #define LNA_AGCGAIN 0x75
JMF 0:24d3eb812fd4 244 //--------------- 0x76
JMF 0:24d3eb812fd4 245 //--------------- 0x77
JMF 0:24d3eb812fd4 246 #define CHF_PMA_GAIN 0x78
JMF 0:24d3eb812fd4 247 #define CHF_IBUF 0x79
JMF 0:24d3eb812fd4 248 #define CHF_QBUF 0x7A
JMF 0:24d3eb812fd4 249 #define CHF_IRIN 0x7B
JMF 0:24d3eb812fd4 250 #define CHF_QRIN 0x7C
JMF 0:24d3eb812fd4 251 #define CHF_IL 0x7D
JMF 0:24d3eb812fd4 252 #define CHF_QL 0x7E
JMF 0:24d3eb812fd4 253 #define CHF_CC1 0x7F
JMF 0:24d3eb812fd4 254 #define CHF_CCL 0x80
JMF 0:24d3eb812fd4 255 #define CHF_CC2 0x81
JMF 0:24d3eb812fd4 256 #define CHF_IROUT 0x82
JMF 0:24d3eb812fd4 257 #define CHF_QROUT 0x83
JMF 0:24d3eb812fd4 258 //--------------- 0x84
JMF 0:24d3eb812fd4 259 //--------------- 0x85
JMF 0:24d3eb812fd4 260 #define RSSI_CTRL 0x86
JMF 0:24d3eb812fd4 261 //--------------- 0x87
JMF 0:24d3eb812fd4 262 //--------------- 0x88
JMF 0:24d3eb812fd4 263 #define PA_BIAS 0x89
JMF 0:24d3eb812fd4 264 #define PA_TUNING 0x8A
JMF 0:24d3eb812fd4 265 //--------------- 0x8B
JMF 0:24d3eb812fd4 266 //--------------- 0x8C
JMF 0:24d3eb812fd4 267 #define PMC_HP_TRIM 0x8D
JMF 0:24d3eb812fd4 268 #define VREGA_TRIM 0x8E
JMF 0:24d3eb812fd4 269 //--------------- 0x8F
JMF 0:24d3eb812fd4 270 //--------------- 0x90
JMF 0:24d3eb812fd4 271 #define VCO_CTRL1 0x91
JMF 0:24d3eb812fd4 272 #define VCO_CTRL2 0x92
JMF 0:24d3eb812fd4 273 //--------------- 0x93
JMF 0:24d3eb812fd4 274 //--------------- 0x94
JMF 0:24d3eb812fd4 275 #define ANA_SPARE_OUT1 0x95
JMF 0:24d3eb812fd4 276 #define ANA_SPARE_OUT2 0x96
JMF 0:24d3eb812fd4 277 #define ANA_SPARE_IN 0x97
JMF 0:24d3eb812fd4 278 #define MISCELLANEOUS 0x98
JMF 0:24d3eb812fd4 279 //--------------- 0x99
JMF 0:24d3eb812fd4 280 #define SEQ_MGR_OVRD0 0x9A
JMF 0:24d3eb812fd4 281 #define SEQ_MGR_OVRD1 0x9B
JMF 0:24d3eb812fd4 282 #define SEQ_MGR_OVRD2 0x9C
JMF 0:24d3eb812fd4 283 #define SEQ_MGR_OVRD3 0x9D
JMF 0:24d3eb812fd4 284 #define SEQ_MGR_OVRD4 0x9E
JMF 0:24d3eb812fd4 285 #define SEQ_MGR_OVRD5 0x9F
JMF 0:24d3eb812fd4 286 #define SEQ_MGR_OVRD6 0xA0
JMF 0:24d3eb812fd4 287 #define SEQ_MGR_OVRD7 0xA1
JMF 0:24d3eb812fd4 288 //--------------- 0xA2
JMF 0:24d3eb812fd4 289 #define TESTMODE_CTRL 0xA3
JMF 0:24d3eb812fd4 290 #define DTM_CTRL1 0xA4
JMF 0:24d3eb812fd4 291 #define DTM_CTRL2 0xA5
JMF 0:24d3eb812fd4 292 #define ATM_CTRL1 0xA6
JMF 0:24d3eb812fd4 293 #define ATM_CTRL2 0xA7
JMF 0:24d3eb812fd4 294 #define ATM_CTRL3 0xA8
JMF 0:24d3eb812fd4 295 //--------------- 0xA9
JMF 0:24d3eb812fd4 296 #define LIM_FE_TEST_CTRL 0xAA
JMF 0:24d3eb812fd4 297 #define CHF_TEST_CTRL 0xAB
JMF 0:24d3eb812fd4 298 #define VCO_TEST_CTRL 0xAC
JMF 0:24d3eb812fd4 299 #define PLL_TEST_CTRL 0xAD
JMF 0:24d3eb812fd4 300 #define PA_TEST_CTRL 0xAE
JMF 0:24d3eb812fd4 301 #define PMC_TEST_CTRL 0xAF
JMF 0:24d3eb812fd4 302 #define SCAN_DTM_PROTECT_1 0xFE
JMF 0:24d3eb812fd4 303 #define SCAN_DTM_PROTECT_0 0xFF
JMF 0:24d3eb812fd4 304
JMF 0:24d3eb812fd4 305 // IRQSTS1 bits
JMF 0:24d3eb812fd4 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
JMF 0:24d3eb812fd4 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
JMF 0:24d3eb812fd4 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
JMF 0:24d3eb812fd4 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
JMF 0:24d3eb812fd4 310 #define cIRQSTS1_CCAIRQ (1<<3)
JMF 0:24d3eb812fd4 311 #define cIRQSTS1_RXIRQ (1<<2)
JMF 0:24d3eb812fd4 312 #define cIRQSTS1_TXIRQ (1<<1)
JMF 0:24d3eb812fd4 313 #define cIRQSTS1_SEQIRQ (1<<0)
JMF 0:24d3eb812fd4 314
JMF 0:24d3eb812fd4 315 typedef union regIRQSTS1_tag{
JMF 0:24d3eb812fd4 316 uint8_t byte;
JMF 0:24d3eb812fd4 317 struct{
JMF 0:24d3eb812fd4 318 uint8_t SEQIRQ:1;
JMF 0:24d3eb812fd4 319 uint8_t TXIRQ:1;
JMF 0:24d3eb812fd4 320 uint8_t RXIRQ:1;
JMF 0:24d3eb812fd4 321 uint8_t CCAIRQ:1;
JMF 0:24d3eb812fd4 322 uint8_t RXWTRMRKIRQ:1;
JMF 0:24d3eb812fd4 323 uint8_t FILTERFAIL_IRQ:1;
JMF 0:24d3eb812fd4 324 uint8_t PLL_UNLOCK_IRQ:1;
JMF 0:24d3eb812fd4 325 uint8_t RX_FRM_PEND:1;
JMF 0:24d3eb812fd4 326 }bit;
JMF 0:24d3eb812fd4 327 } regIRQSTS1_t;
JMF 0:24d3eb812fd4 328
JMF 0:24d3eb812fd4 329 // IRQSTS2 bits
JMF 0:24d3eb812fd4 330 #define cIRQSTS2_CRCVALID (1<<7)
JMF 0:24d3eb812fd4 331 #define cIRQSTS2_CCA (1<<6)
JMF 0:24d3eb812fd4 332 #define cIRQSTS2_SRCADDR (1<<5)
JMF 0:24d3eb812fd4 333 #define cIRQSTS2_PI (1<<4)
JMF 0:24d3eb812fd4 334 #define cIRQSTS2_TMRSTATUS (1<<3)
JMF 0:24d3eb812fd4 335 #define cIRQSTS2_ASM_IRQ (1<<2)
JMF 0:24d3eb812fd4 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
JMF 0:24d3eb812fd4 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
JMF 0:24d3eb812fd4 338
JMF 0:24d3eb812fd4 339 typedef union regIRQSTS2_tag{
JMF 0:24d3eb812fd4 340 uint8_t byte;
JMF 0:24d3eb812fd4 341 struct{
JMF 0:24d3eb812fd4 342 uint8_t WAKE_IRQ:1;
JMF 0:24d3eb812fd4 343 uint8_t PB_ERR_IRQ:1;
JMF 0:24d3eb812fd4 344 uint8_t ASM_IRQ:1;
JMF 0:24d3eb812fd4 345 uint8_t TMRSTATUS:1;
JMF 0:24d3eb812fd4 346 uint8_t PI_:1;
JMF 0:24d3eb812fd4 347 uint8_t SRCADDR:1;
JMF 0:24d3eb812fd4 348 uint8_t CCA:1;
JMF 0:24d3eb812fd4 349 uint8_t CRCVALID:1;
JMF 0:24d3eb812fd4 350 }bit;
JMF 0:24d3eb812fd4 351 } regIRQSTS2_t;
JMF 0:24d3eb812fd4 352
JMF 0:24d3eb812fd4 353 // IRQSTS3 bits
JMF 0:24d3eb812fd4 354 #define cIRQSTS3_TMR4MSK (1<<7)
JMF 0:24d3eb812fd4 355 #define cIRQSTS3_TMR3MSK (1<<6)
JMF 0:24d3eb812fd4 356 #define cIRQSTS3_TMR2MSK (1<<5)
JMF 0:24d3eb812fd4 357 #define cIRQSTS3_TMR1MSK (1<<4)
JMF 0:24d3eb812fd4 358 #define cIRQSTS3_TMR4IRQ (1<<3)
JMF 0:24d3eb812fd4 359 #define cIRQSTS3_TMR3IRQ (1<<2)
JMF 0:24d3eb812fd4 360 #define cIRQSTS3_TMR2IRQ (1<<1)
JMF 0:24d3eb812fd4 361 #define cIRQSTS3_TMR1IRQ (1<<0)
JMF 0:24d3eb812fd4 362
JMF 0:24d3eb812fd4 363 typedef union regIRQSTS3_tag{
JMF 0:24d3eb812fd4 364 uint8_t byte;
JMF 0:24d3eb812fd4 365 struct{
JMF 0:24d3eb812fd4 366 uint8_t TMR1IRQ:1;
JMF 0:24d3eb812fd4 367 uint8_t TMR2IRQ:1;
JMF 0:24d3eb812fd4 368 uint8_t TMR3IRQ:1;
JMF 0:24d3eb812fd4 369 uint8_t TMR4IRQ:1;
JMF 0:24d3eb812fd4 370 uint8_t TMR1MSK:1;
JMF 0:24d3eb812fd4 371 uint8_t TMR2MSK:1;
JMF 0:24d3eb812fd4 372 uint8_t TMR3MSK:1;
JMF 0:24d3eb812fd4 373 uint8_t TMR4MSK:1;
JMF 0:24d3eb812fd4 374 }bit;
JMF 0:24d3eb812fd4 375 } regIRQSTS3_t;
JMF 0:24d3eb812fd4 376
JMF 0:24d3eb812fd4 377 // PHY_CTRL1 bits
JMF 0:24d3eb812fd4 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
JMF 0:24d3eb812fd4 379 #define cPHY_CTRL1_SLOTTED (1<<6)
JMF 0:24d3eb812fd4 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
JMF 0:24d3eb812fd4 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
JMF 0:24d3eb812fd4 382 #define cPHY_CTRL1_AUTOACK (1<<3)
JMF 0:24d3eb812fd4 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
JMF 0:24d3eb812fd4 384
JMF 0:24d3eb812fd4 385 typedef union regPHY_CTRL1_tag{
JMF 0:24d3eb812fd4 386 uint8_t byte;
JMF 0:24d3eb812fd4 387 struct{
JMF 0:24d3eb812fd4 388 uint8_t XCVSEQ:3;
JMF 0:24d3eb812fd4 389 uint8_t AUTOACK:1;
JMF 0:24d3eb812fd4 390 uint8_t RXACKRQD:1;
JMF 0:24d3eb812fd4 391 uint8_t CCABFRTX:1;
JMF 0:24d3eb812fd4 392 uint8_t SLOTTED:1;
JMF 0:24d3eb812fd4 393 uint8_t TMRTRIGEN:1;
JMF 0:24d3eb812fd4 394 }bit;
JMF 0:24d3eb812fd4 395 } regPHY_CTRL1_t;
JMF 0:24d3eb812fd4 396
JMF 0:24d3eb812fd4 397 // PHY_CTRL2 bits
JMF 0:24d3eb812fd4 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
JMF 0:24d3eb812fd4 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
JMF 0:24d3eb812fd4 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
JMF 0:24d3eb812fd4 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
JMF 0:24d3eb812fd4 402 #define cPHY_CTRL2_CCAMSK (1<<3)
JMF 0:24d3eb812fd4 403 #define cPHY_CTRL2_RXMSK (1<<2)
JMF 0:24d3eb812fd4 404 #define cPHY_CTRL2_TXMSK (1<<1)
JMF 0:24d3eb812fd4 405 #define cPHY_CTRL2_SEQMSK (1<<0)
JMF 0:24d3eb812fd4 406
JMF 0:24d3eb812fd4 407 typedef union regPHY_CTRL2_tag{
JMF 0:24d3eb812fd4 408 uint8_t byte;
JMF 0:24d3eb812fd4 409 struct{
JMF 0:24d3eb812fd4 410 uint8_t SEQMSK:1;
JMF 0:24d3eb812fd4 411 uint8_t TXMSK:1;
JMF 0:24d3eb812fd4 412 uint8_t RXMSK:1;
JMF 0:24d3eb812fd4 413 uint8_t CCAMSK:1;
JMF 0:24d3eb812fd4 414 uint8_t RX_WMRK_MSK:1;
JMF 0:24d3eb812fd4 415 uint8_t FILTERFAIL_MSK:1;
JMF 0:24d3eb812fd4 416 uint8_t PLL_UNLOCK_MSK:1;
JMF 0:24d3eb812fd4 417 uint8_t CRC_MSK:1;
JMF 0:24d3eb812fd4 418 }bit;
JMF 0:24d3eb812fd4 419 } regPHY_CTRL2_t;
JMF 0:24d3eb812fd4 420
JMF 0:24d3eb812fd4 421 // PHY_CTRL3 bits
JMF 0:24d3eb812fd4 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
JMF 0:24d3eb812fd4 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
JMF 0:24d3eb812fd4 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
JMF 0:24d3eb812fd4 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
JMF 0:24d3eb812fd4 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
JMF 0:24d3eb812fd4 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
JMF 0:24d3eb812fd4 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
JMF 0:24d3eb812fd4 429
JMF 0:24d3eb812fd4 430 typedef union regPHY_CTRL3_tag{
JMF 0:24d3eb812fd4 431 uint8_t byte;
JMF 0:24d3eb812fd4 432 struct{
JMF 0:24d3eb812fd4 433 uint8_t WAKE_MSK:1;
JMF 0:24d3eb812fd4 434 uint8_t PB_ERR_MSK:1;
JMF 0:24d3eb812fd4 435 uint8_t ASM_MSK:1;
JMF 0:24d3eb812fd4 436 uint8_t RESERVED:1;
JMF 0:24d3eb812fd4 437 uint8_t TMR1CMP_EN:1;
JMF 0:24d3eb812fd4 438 uint8_t TMR2CMP_EN:1;
JMF 0:24d3eb812fd4 439 uint8_t TMR3CMP_EN:1;
JMF 0:24d3eb812fd4 440 uint8_t TMR4CMP_EN:1;
JMF 0:24d3eb812fd4 441 }bit;
JMF 0:24d3eb812fd4 442 } regPHY_CTRL3_t;
JMF 0:24d3eb812fd4 443
JMF 0:24d3eb812fd4 444 // RX_FRM_LEN bits
JMF 0:24d3eb812fd4 445 #define cRX_FRAME_LENGTH (0x7F)
JMF 0:24d3eb812fd4 446
JMF 0:24d3eb812fd4 447 // PHY_CTRL4 bits
JMF 0:24d3eb812fd4 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
JMF 0:24d3eb812fd4 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
JMF 0:24d3eb812fd4 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
JMF 0:24d3eb812fd4 451 #define cPHY_CTRL4_CCATYPE (3<<0)
JMF 0:24d3eb812fd4 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
JMF 0:24d3eb812fd4 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
JMF 0:24d3eb812fd4 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
JMF 0:24d3eb812fd4 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
JMF 0:24d3eb812fd4 456
JMF 0:24d3eb812fd4 457 typedef union regPHY_CTRL4_tag{
JMF 0:24d3eb812fd4 458 uint8_t byte;
JMF 0:24d3eb812fd4 459 struct{
JMF 0:24d3eb812fd4 460 uint8_t TC2PRIME_EN:1;
JMF 0:24d3eb812fd4 461 uint8_t PROMISCUOUS:1;
JMF 0:24d3eb812fd4 462 uint8_t TMRLOAD:1;
JMF 0:24d3eb812fd4 463 uint8_t CCATYPE:2;
JMF 0:24d3eb812fd4 464 uint8_t PANCORDNTR0:1;
JMF 0:24d3eb812fd4 465 uint8_t TC3TMOUT:1;
JMF 0:24d3eb812fd4 466 uint8_t TRCV_MSK:1;
JMF 0:24d3eb812fd4 467 }bit;
JMF 0:24d3eb812fd4 468 } regPHY_CTRL4_t;
JMF 0:24d3eb812fd4 469
JMF 0:24d3eb812fd4 470 // SRC_CTRL bits
JMF 0:24d3eb812fd4 471 #define cSRC_CTRL_INDEX (0x0F)
JMF 0:24d3eb812fd4 472 #define cSRC_CTRL_INDEX_Shift_c (4)
JMF 0:24d3eb812fd4 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
JMF 0:24d3eb812fd4 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
JMF 0:24d3eb812fd4 475 #define cSRC_CTRL_INDEX_EN (1<<1)
JMF 0:24d3eb812fd4 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
JMF 0:24d3eb812fd4 477
JMF 0:24d3eb812fd4 478 typedef union regSRC_CTRL_tag{
JMF 0:24d3eb812fd4 479 uint8_t byte;
JMF 0:24d3eb812fd4 480 struct{
JMF 0:24d3eb812fd4 481 uint8_t INDEX_DISABLE:1;
JMF 0:24d3eb812fd4 482 uint8_t INDEX_EN:1;
JMF 0:24d3eb812fd4 483 uint8_t SRCADDR_EN:1;
JMF 0:24d3eb812fd4 484 uint8_t ACK_FRM_PND:1;
JMF 0:24d3eb812fd4 485 uint8_t INDEX:4;
JMF 0:24d3eb812fd4 486 }bit;
JMF 0:24d3eb812fd4 487 } regSRC_CTRL_t;
JMF 0:24d3eb812fd4 488
JMF 0:24d3eb812fd4 489 // ASM_CTRL1 bits
JMF 0:24d3eb812fd4 490 #define cASM_CTRL1_CLEAR (1<<7)
JMF 0:24d3eb812fd4 491 #define cASM_CTRL1_START (1<<6)
JMF 0:24d3eb812fd4 492 #define cASM_CTRL1_SELFTST (1<<5)
JMF 0:24d3eb812fd4 493 #define cASM_CTRL1_CTR (1<<4)
JMF 0:24d3eb812fd4 494 #define cASM_CTRL1_CBC (1<<3)
JMF 0:24d3eb812fd4 495 #define cASM_CTRL1_AES (1<<2)
JMF 0:24d3eb812fd4 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
JMF 0:24d3eb812fd4 497
JMF 0:24d3eb812fd4 498 // ASM_CTRL2 bits
JMF 0:24d3eb812fd4 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
JMF 0:24d3eb812fd4 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
JMF 0:24d3eb812fd4 501 #define cASM_CTRL2_TSTPAS (1<<1)
JMF 0:24d3eb812fd4 502
JMF 0:24d3eb812fd4 503 // CLK_OUT_CTRL bits
JMF 0:24d3eb812fd4 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
JMF 0:24d3eb812fd4 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
JMF 0:24d3eb812fd4 506 #define cCLK_OUT_CTRL_SR (1<<5)
JMF 0:24d3eb812fd4 507 #define cCLK_OUT_CTRL_DS (1<<4)
JMF 0:24d3eb812fd4 508 #define cCLK_OUT_CTRL_EN (1<<3)
JMF 0:24d3eb812fd4 509 #define cCLK_OUT_CTRL_DIV (7)
JMF 0:24d3eb812fd4 510
JMF 0:24d3eb812fd4 511 // PWR_MODES bits
JMF 0:24d3eb812fd4 512 #define cPWR_MODES_XTAL_READY (1<<5)
JMF 0:24d3eb812fd4 513 #define cPWR_MODES_XTALEN (1<<4)
JMF 0:24d3eb812fd4 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
JMF 0:24d3eb812fd4 515 #define cPWR_MODES_AUTODOZE (1<<1)
JMF 0:24d3eb812fd4 516 #define cPWR_MODES_PMC_MODE (1<<0)
JMF 0:24d3eb812fd4 517
JMF 0:24d3eb812fd4 518 // RX_FRAME_FILTER bits
JMF 0:24d3eb812fd4 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
JMF 0:24d3eb812fd4 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
JMF 0:24d3eb812fd4 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
JMF 0:24d3eb812fd4 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
JMF 0:24d3eb812fd4 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
JMF 0:24d3eb812fd4 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
JMF 0:24d3eb812fd4 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
JMF 0:24d3eb812fd4 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
JMF 0:24d3eb812fd4 527
JMF 0:24d3eb812fd4 528 typedef union regRX_FRAME_FILTER_tag{
JMF 0:24d3eb812fd4 529 uint8_t byte;
JMF 0:24d3eb812fd4 530 struct{
JMF 0:24d3eb812fd4 531 uint8_t FRAME_FLT_BEACON_FT:1;
JMF 0:24d3eb812fd4 532 uint8_t FRAME_FLT_DATA_FT:1;
JMF 0:24d3eb812fd4 533 uint8_t FRAME_FLT_ACK_FT:1;
JMF 0:24d3eb812fd4 534 uint8_t FRAME_FLT_CMD_FT:1;
JMF 0:24d3eb812fd4 535 uint8_t FRAME_FLT_NS_FT:1;
JMF 0:24d3eb812fd4 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
JMF 0:24d3eb812fd4 537 uint8_t FRAME_FLT_FRM_VER:2;
JMF 0:24d3eb812fd4 538 }bit;
JMF 0:24d3eb812fd4 539 } regRX_FRAME_FILTER_t;
JMF 0:24d3eb812fd4 540
JMF 0:24d3eb812fd4 541 // DUAL_PAN_CTRL bits
JMF 0:24d3eb812fd4 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
JMF 0:24d3eb812fd4 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
JMF 0:24d3eb812fd4 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
JMF 0:24d3eb812fd4 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
JMF 0:24d3eb812fd4 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
JMF 0:24d3eb812fd4 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
JMF 0:24d3eb812fd4 548
JMF 0:24d3eb812fd4 549 // DUAL_PAN_STS bits
JMF 0:24d3eb812fd4 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
JMF 0:24d3eb812fd4 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
JMF 0:24d3eb812fd4 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
JMF 0:24d3eb812fd4 553
JMF 0:24d3eb812fd4 554 // CCA_CTRL bits
JMF 0:24d3eb812fd4 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
JMF 0:24d3eb812fd4 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
JMF 0:24d3eb812fd4 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
JMF 0:24d3eb812fd4 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
JMF 0:24d3eb812fd4 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
JMF 0:24d3eb812fd4 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
JMF 0:24d3eb812fd4 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
JMF 0:24d3eb812fd4 562
JMF 0:24d3eb812fd4 563 // GPIO_DATA bits
JMF 0:24d3eb812fd4 564 #define cGPIO_DATA_7 (1<<7)
JMF 0:24d3eb812fd4 565 #define cGPIO_DATA_6 (1<<6)
JMF 0:24d3eb812fd4 566 #define cGPIO_DATA_5 (1<<5)
JMF 0:24d3eb812fd4 567 #define cGPIO_DATA_4 (1<<4)
JMF 0:24d3eb812fd4 568 #define cGPIO_DATA_3 (1<<3)
JMF 0:24d3eb812fd4 569 #define cGPIO_DATA_2 (1<<2)
JMF 0:24d3eb812fd4 570 #define cGPIO_DATA_1 (1<<1)
JMF 0:24d3eb812fd4 571 #define cGPIO_DATA_0 (1<<0)
JMF 0:24d3eb812fd4 572
JMF 0:24d3eb812fd4 573 // GPIO_DIR bits
JMF 0:24d3eb812fd4 574 #define cGPIO_DIR_7 (1<<7)
JMF 0:24d3eb812fd4 575 #define cGPIO_DIR_6 (1<<6)
JMF 0:24d3eb812fd4 576 #define cGPIO_DIR_5 (1<<5)
JMF 0:24d3eb812fd4 577 #define cGPIO_DIR_4 (1<<4)
JMF 0:24d3eb812fd4 578 #define cGPIO_DIR_3 (1<<3)
JMF 0:24d3eb812fd4 579 #define cGPIO_DIR_2 (1<<2)
JMF 0:24d3eb812fd4 580 #define cGPIO_DIR_1 (1<<1)
JMF 0:24d3eb812fd4 581 #define cGPIO_DIR_0 (1<<0)
JMF 0:24d3eb812fd4 582
JMF 0:24d3eb812fd4 583 // GPIO_PUL_EN bits
JMF 0:24d3eb812fd4 584 #define cGPIO_PUL_EN_7 (1<<7)
JMF 0:24d3eb812fd4 585 #define cGPIO_PUL_EN_6 (1<<6)
JMF 0:24d3eb812fd4 586 #define cGPIO_PUL_EN_5 (1<<5)
JMF 0:24d3eb812fd4 587 #define cGPIO_PUL_EN_4 (1<<4)
JMF 0:24d3eb812fd4 588 #define cGPIO_PUL_EN_3 (1<<3)
JMF 0:24d3eb812fd4 589 #define cGPIO_PUL_EN_2 (1<<2)
JMF 0:24d3eb812fd4 590 #define cGPIO_PUL_EN_1 (1<<1)
JMF 0:24d3eb812fd4 591 #define cGPIO_PUL_EN_0 (1<<0)
JMF 0:24d3eb812fd4 592
JMF 0:24d3eb812fd4 593 // GPIO_PUL_SEL bits
JMF 0:24d3eb812fd4 594 #define cGPIO_PUL_SEL_7 (1<<7)
JMF 0:24d3eb812fd4 595 #define cGPIO_PUL_SEL_6 (1<<6)
JMF 0:24d3eb812fd4 596 #define cGPIO_PUL_SEL_5 (1<<5)
JMF 0:24d3eb812fd4 597 #define cGPIO_PUL_SEL_4 (1<<4)
JMF 0:24d3eb812fd4 598 #define cGPIO_PUL_SEL_3 (1<<3)
JMF 0:24d3eb812fd4 599 #define cGPIO_PUL_SEL_2 (1<<2)
JMF 0:24d3eb812fd4 600 #define cGPIO_PUL_SEL_1 (1<<1)
JMF 0:24d3eb812fd4 601 #define cGPIO_PUL_SEL_0 (1<<0)
JMF 0:24d3eb812fd4 602
JMF 0:24d3eb812fd4 603 // GPIO_DS bits
JMF 0:24d3eb812fd4 604 #define cGPIO_DS_7 (1<<7)
JMF 0:24d3eb812fd4 605 #define cGPIO_DS_6 (1<<6)
JMF 0:24d3eb812fd4 606 #define cGPIO_DS_5 (1<<5)
JMF 0:24d3eb812fd4 607 #define cGPIO_DS_4 (1<<4)
JMF 0:24d3eb812fd4 608 #define cGPIO_DS_3 (1<<3)
JMF 0:24d3eb812fd4 609 #define cGPIO_DS_2 (1<<2)
JMF 0:24d3eb812fd4 610 #define cGPIO_DS_1 (1<<1)
JMF 0:24d3eb812fd4 611 #define cGPIO_DS_0 (1<<0)
JMF 0:24d3eb812fd4 612
JMF 0:24d3eb812fd4 613 // SPI_CTRL bits
JMF 0:24d3eb812fd4 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
JMF 0:24d3eb812fd4 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
JMF 0:24d3eb812fd4 616
JMF 0:24d3eb812fd4 617 // ANT_PAD_CTRL bits
JMF 0:24d3eb812fd4 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
JMF 0:24d3eb812fd4 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
JMF 0:24d3eb812fd4 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
JMF 0:24d3eb812fd4 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
JMF 0:24d3eb812fd4 622 #define cANT_PAD_CTRL_ANTX_EN (3)
JMF 0:24d3eb812fd4 623
JMF 0:24d3eb812fd4 624 // MISC_PAD_CTRL bits
JMF 0:24d3eb812fd4 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
JMF 0:24d3eb812fd4 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
JMF 0:24d3eb812fd4 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
JMF 0:24d3eb812fd4 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
JMF 0:24d3eb812fd4 629
JMF 0:24d3eb812fd4 630 // ANT_AGC_CTRL bits
JMF 0:24d3eb812fd4 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
JMF 0:24d3eb812fd4 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
JMF 0:24d3eb812fd4 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
JMF 0:24d3eb812fd4 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
JMF 0:24d3eb812fd4 635
JMF 0:24d3eb812fd4 636 // BSM_CTRL bits
JMF 0:24d3eb812fd4 637 #define cBSM_CTRL_BSM_EN (1<<0)
JMF 0:24d3eb812fd4 638
JMF 0:24d3eb812fd4 639 // SOFT_RESET bits
JMF 0:24d3eb812fd4 640 #define cSOFT_RESET_SOG_RST (1<<7)
JMF 0:24d3eb812fd4 641 #define cSOFT_RESET_REGS_RST (1<<4)
JMF 0:24d3eb812fd4 642 #define cSOFT_RESET_PLL_RST (1<<3)
JMF 0:24d3eb812fd4 643 #define cSOFT_RESET_TX_RST (1<<2)
JMF 0:24d3eb812fd4 644 #define cSOFT_RESET_RX_RST (1<<1)
JMF 0:24d3eb812fd4 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
JMF 0:24d3eb812fd4 646
JMF 0:24d3eb812fd4 647 // SEQ_MGR_CTRL bits
JMF 0:24d3eb812fd4 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
JMF 0:24d3eb812fd4 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
JMF 0:24d3eb812fd4 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
JMF 0:24d3eb812fd4 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
JMF 0:24d3eb812fd4 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
JMF 0:24d3eb812fd4 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
JMF 0:24d3eb812fd4 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
JMF 0:24d3eb812fd4 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
JMF 0:24d3eb812fd4 656
JMF 0:24d3eb812fd4 657 // SEQ_MGR_STS bits
JMF 0:24d3eb812fd4 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
JMF 0:24d3eb812fd4 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
JMF 0:24d3eb812fd4 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
JMF 0:24d3eb812fd4 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
JMF 0:24d3eb812fd4 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
JMF 0:24d3eb812fd4 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
JMF 0:24d3eb812fd4 664
JMF 0:24d3eb812fd4 665 // ABORT_STS bits
JMF 0:24d3eb812fd4 666 #define cABORT_STS_PLL_ABORTED (1<<2)
JMF 0:24d3eb812fd4 667 #define cABORT_STS_TC3_ABORTED (1<<1)
JMF 0:24d3eb812fd4 668 #define cABORT_STS_SW_ABORTED (1<<0)
JMF 0:24d3eb812fd4 669
JMF 0:24d3eb812fd4 670 // FILTERFAIL_CODE2 bits
JMF 0:24d3eb812fd4 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
JMF 0:24d3eb812fd4 672 #define cFILTERFAIL_CODE2_9_8 (3)
JMF 0:24d3eb812fd4 673
JMF 0:24d3eb812fd4 674 // PHY_STS bits
JMF 0:24d3eb812fd4 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
JMF 0:24d3eb812fd4 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
JMF 0:24d3eb812fd4 677 #define cPHY_STS_PLL_LOCK (1<<5)
JMF 0:24d3eb812fd4 678 #define cPHY_STS_CRCVALID (1<<3)
JMF 0:24d3eb812fd4 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
JMF 0:24d3eb812fd4 680 #define cPHY_STS_SFD_DET (1<<1)
JMF 0:24d3eb812fd4 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
JMF 0:24d3eb812fd4 682
JMF 0:24d3eb812fd4 683 // TESTMODE_CTRL bits
JMF 0:24d3eb812fd4 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
JMF 0:24d3eb812fd4 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
JMF 0:24d3eb812fd4 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
JMF 0:24d3eb812fd4 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
JMF 0:24d3eb812fd4 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
JMF 0:24d3eb812fd4 689
JMF 0:24d3eb812fd4 690 // DTM_CTRL1 bits
JMF 0:24d3eb812fd4 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
JMF 0:24d3eb812fd4 692 #define cDTM_CTRL1_DTM_EN (1<<6)
JMF 0:24d3eb812fd4 693 #define cDTM_CTRL1_PAGE5 (1<<5)
JMF 0:24d3eb812fd4 694 #define cDTM_CTRL1_PAGE4 (1<<4)
JMF 0:24d3eb812fd4 695 #define cDTM_CTRL1_PAGE3 (1<<3)
JMF 0:24d3eb812fd4 696 #define cDTM_CTRL1_PAGE2 (1<<2)
JMF 0:24d3eb812fd4 697 #define cDTM_CTRL1_PAGE1 (1<<1)
JMF 0:24d3eb812fd4 698 #define cDTM_CTRL1_PAGE0 (1<<0)
JMF 0:24d3eb812fd4 699
JMF 0:24d3eb812fd4 700 // TX_MODE_CTRL
JMF 0:24d3eb812fd4 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
JMF 0:24d3eb812fd4 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
JMF 0:24d3eb812fd4 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
JMF 0:24d3eb812fd4 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
JMF 0:24d3eb812fd4 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
JMF 0:24d3eb812fd4 706
JMF 0:24d3eb812fd4 707 #define cTX_MODE_CTRL_DTS_MASK (7)
JMF 0:24d3eb812fd4 708
JMF 0:24d3eb812fd4 709 // CLK_OUT_CTRL bits
JMF 0:24d3eb812fd4 710 #define cCLK_OUT_EXTEND (1<<7)
JMF 0:24d3eb812fd4 711 #define cCLK_OUT_HIZ (1<<6)
JMF 0:24d3eb812fd4 712 #define cCLK_OUT_SR (1<<5)
JMF 0:24d3eb812fd4 713 #define cCLK_OUT_DS (1<<4)
JMF 0:24d3eb812fd4 714 #define cCLK_OUT_EN (1<<3)
JMF 0:24d3eb812fd4 715 #define cCLK_OUT_DIV_Mask (7<<0)
JMF 0:24d3eb812fd4 716
JMF 0:24d3eb812fd4 717 #define gCLK_OUT_FREQ_32_MHz (0)
JMF 0:24d3eb812fd4 718 #define gCLK_OUT_FREQ_16_MHz (1)
JMF 0:24d3eb812fd4 719 #define gCLK_OUT_FREQ_8_MHz (2)
JMF 0:24d3eb812fd4 720 #define gCLK_OUT_FREQ_4_MHz (3)
JMF 0:24d3eb812fd4 721 #define gCLK_OUT_FREQ_1_MHz (4)
JMF 0:24d3eb812fd4 722 #define gCLK_OUT_FREQ_250_KHz (5)
JMF 0:24d3eb812fd4 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
JMF 0:24d3eb812fd4 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
JMF 0:24d3eb812fd4 725 #define gCLK_OUT_FREQ_DISABLE (8)
JMF 0:24d3eb812fd4 726
JMF 0:24d3eb812fd4 727
JMF 0:24d3eb812fd4 728
JMF 0:24d3eb812fd4 729
JMF 0:24d3eb812fd4 730 #endif /* __MCR20_REG_H__ */