Jim Flynn / Mbed OS wifi_Example

wifi test

Dependencies:   X_NUCLEO_IKS01A2 mbed-http

easy-connect/atmel-rf-driver/source/AT86RFReg.h@0:24d3eb812fd4, 2018-09-05 (annotated)

Committer:
JMF
Date:
Wed Sep 05 14:28:24 2018 +0000
Revision:
0:24d3eb812fd4
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
JMF 0:24d3eb812fd4 1 /*
JMF 0:24d3eb812fd4 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
JMF 0:24d3eb812fd4 3 * SPDX-License-Identifier: Apache-2.0
JMF 0:24d3eb812fd4 4 * Licensed under the Apache License, Version 2.0 (the License); you may
JMF 0:24d3eb812fd4 5 * not use this file except in compliance with the License.
JMF 0:24d3eb812fd4 6 * You may obtain a copy of the License at
JMF 0:24d3eb812fd4 7 *
JMF 0:24d3eb812fd4 8 * http://www.apache.org/licenses/LICENSE-2.0
JMF 0:24d3eb812fd4 9 *
JMF 0:24d3eb812fd4 10 * Unless required by applicable law or agreed to in writing, software
JMF 0:24d3eb812fd4 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
JMF 0:24d3eb812fd4 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
JMF 0:24d3eb812fd4 13 * See the License for the specific language governing permissions and
JMF 0:24d3eb812fd4 14 * limitations under the License.
JMF 0:24d3eb812fd4 15 */
JMF 0:24d3eb812fd4 16
JMF 0:24d3eb812fd4 17 #ifndef AT86RFREG_H_
JMF 0:24d3eb812fd4 18 #define AT86RFREG_H_
JMF 0:24d3eb812fd4 19 #ifdef __cplusplus
JMF 0:24d3eb812fd4 20 extern "C" {
JMF 0:24d3eb812fd4 21 #endif
JMF 0:24d3eb812fd4 22
JMF 0:24d3eb812fd4 23 /*AT86RF212 PHY Modes*/
JMF 0:24d3eb812fd4 24 #define BPSK_20 0x00
JMF 0:24d3eb812fd4 25 #define BPSK_40 0x04
JMF 0:24d3eb812fd4 26 #define BPSK_40_ALT 0x14
JMF 0:24d3eb812fd4 27 #define OQPSK_SIN_RC_100 0x08
JMF 0:24d3eb812fd4 28 #define OQPSK_SIN_RC_200 0x09
JMF 0:24d3eb812fd4 29 #define OQPSK_RC_100 0x18
JMF 0:24d3eb812fd4 30 #define OQPSK_RC_200 0x19
JMF 0:24d3eb812fd4 31 #define OQPSK_SIN_250 0x0c
JMF 0:24d3eb812fd4 32 #define OQPSK_SIN_500 0x0d
JMF 0:24d3eb812fd4 33 #define OQPSK_SIN_500_ALT 0x0f
JMF 0:24d3eb812fd4 34 #define OQPSK_RC_250 0x1c
JMF 0:24d3eb812fd4 35 #define OQPSK_RC_500 0x1d
JMF 0:24d3eb812fd4 36 #define OQPSK_RC_500_ALT 0x1f
JMF 0:24d3eb812fd4 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
JMF 0:24d3eb812fd4 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
JMF 0:24d3eb812fd4 39 #define OQPSK_RC_400_SCR_ON 0x3A
JMF 0:24d3eb812fd4 40 #define OQPSK_RC_400_SCR_OFF 0x1A
JMF 0:24d3eb812fd4 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
JMF 0:24d3eb812fd4 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
JMF 0:24d3eb812fd4 43 #define OQPSK_RC_1000_SCR_ON 0x3E
JMF 0:24d3eb812fd4 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
JMF 0:24d3eb812fd4 45
JMF 0:24d3eb812fd4 46 /*Supported transceivers*/
JMF 0:24d3eb812fd4 47 #define PART_AT86RF231 0x03
JMF 0:24d3eb812fd4 48 #define PART_AT86RF212 0x07
JMF 0:24d3eb812fd4 49 #define PART_AT86RF233 0x0B
JMF 0:24d3eb812fd4 50 #define VERSION_AT86RF212 0x01
JMF 0:24d3eb812fd4 51 #define VERSION_AT86RF212B 0x03
JMF 0:24d3eb812fd4 52
JMF 0:24d3eb812fd4 53 /*RF Configuration Registers*/
JMF 0:24d3eb812fd4 54 #define TRX_STATUS 0x01
JMF 0:24d3eb812fd4 55 #define TRX_STATE 0x02
JMF 0:24d3eb812fd4 56 #define TRX_CTRL_0 0x03
JMF 0:24d3eb812fd4 57 #define TRX_CTRL_1 0x04
JMF 0:24d3eb812fd4 58 #define PHY_TX_PWR 0x05
JMF 0:24d3eb812fd4 59 #define PHY_RSSI 0x06
JMF 0:24d3eb812fd4 60 #define PHY_ED_LEVEL 0x07
JMF 0:24d3eb812fd4 61 #define PHY_CC_CCA 0x08
JMF 0:24d3eb812fd4 62 #define RX_CTRL 0x0A
JMF 0:24d3eb812fd4 63 #define SFD_VALUE 0x0B
JMF 0:24d3eb812fd4 64 #define TRX_CTRL_2 0x0C
JMF 0:24d3eb812fd4 65 #define ANT_DIV 0x0D
JMF 0:24d3eb812fd4 66 #define IRQ_MASK 0x0E
JMF 0:24d3eb812fd4 67 #define IRQ_STATUS 0x0F
JMF 0:24d3eb812fd4 68 #define VREG_CTRL 0x10
JMF 0:24d3eb812fd4 69 #define BATMON 0x11
JMF 0:24d3eb812fd4 70 #define XOSC_CTRL 0x12
JMF 0:24d3eb812fd4 71 #define CC_CTRL_0 0x13
JMF 0:24d3eb812fd4 72 #define CC_CTRL_1 0x14
JMF 0:24d3eb812fd4 73 #define RX_SYN 0x15
JMF 0:24d3eb812fd4 74 #define TRX_RPC 0x16
JMF 0:24d3eb812fd4 75 #define RF_CTRL_0 0x16
JMF 0:24d3eb812fd4 76 #define XAH_CTRL_1 0x17
JMF 0:24d3eb812fd4 77 #define FTN_CTRL 0x18
JMF 0:24d3eb812fd4 78 #define PLL_CF 0x1A
JMF 0:24d3eb812fd4 79 #define PLL_DCU 0x1B
JMF 0:24d3eb812fd4 80 #define PART_NUM 0x1C
JMF 0:24d3eb812fd4 81 #define VERSION_NUM 0x1D
JMF 0:24d3eb812fd4 82 #define MAN_ID_0 0x1E
JMF 0:24d3eb812fd4 83 #define MAN_ID_1 0x1F
JMF 0:24d3eb812fd4 84 #define SHORT_ADDR_0 0x20
JMF 0:24d3eb812fd4 85 #define SHORT_ADDR_1 0x21
JMF 0:24d3eb812fd4 86 #define PAN_ID_0 0x22
JMF 0:24d3eb812fd4 87 #define PAN_ID_1 0x23
JMF 0:24d3eb812fd4 88 #define IEEE_ADDR_0 0x24
JMF 0:24d3eb812fd4 89 #define IEEE_ADDR_1 0x25
JMF 0:24d3eb812fd4 90 #define IEEE_ADDR_2 0x26
JMF 0:24d3eb812fd4 91 #define IEEE_ADDR_3 0x27
JMF 0:24d3eb812fd4 92 #define IEEE_ADDR_4 0x28
JMF 0:24d3eb812fd4 93 #define IEEE_ADDR_5 0x29
JMF 0:24d3eb812fd4 94 #define IEEE_ADDR_6 0x2A
JMF 0:24d3eb812fd4 95 #define IEEE_ADDR_7 0x2B
JMF 0:24d3eb812fd4 96 #define XAH_CTRL_0 0x2C
JMF 0:24d3eb812fd4 97 #define CSMA_SEED_0 0x2D
JMF 0:24d3eb812fd4 98 #define CSMA_SEED_1 0x2E
JMF 0:24d3eb812fd4 99 #define CSMA_BE 0x2F
JMF 0:24d3eb812fd4 100
JMF 0:24d3eb812fd4 101 /* CSMA_SEED_1*/
JMF 0:24d3eb812fd4 102 #define AACK_FVN_MODE1 7
JMF 0:24d3eb812fd4 103 #define AACK_FVN_MODE0 6
JMF 0:24d3eb812fd4 104 #define AACK_SET_PD 5
JMF 0:24d3eb812fd4 105 #define AACK_DIS_ACK 4
JMF 0:24d3eb812fd4 106 #define AACK_I_AM_COORD 3
JMF 0:24d3eb812fd4 107 #define CSMA_SEED_12 2
JMF 0:24d3eb812fd4 108 #define CSMA_SEED_11 1
JMF 0:24d3eb812fd4 109 #define CSMA_SEED_10 0
JMF 0:24d3eb812fd4 110
JMF 0:24d3eb812fd4 111 /*TRX_STATUS bits*/
JMF 0:24d3eb812fd4 112 #define CCA_STATUS 0x40
JMF 0:24d3eb812fd4 113 #define CCA_DONE 0x80
JMF 0:24d3eb812fd4 114
JMF 0:24d3eb812fd4 115 /*PHY_CC_CCA bits*/
JMF 0:24d3eb812fd4 116 #define CCA_REQUEST 0x80
JMF 0:24d3eb812fd4 117 #define CCA_MODE_3A 0x00
JMF 0:24d3eb812fd4 118 #define CCA_MODE_1 0x20
JMF 0:24d3eb812fd4 119 #define CCA_MODE_2 0x40
JMF 0:24d3eb812fd4 120 #define CCA_MODE_3B 0x60
JMF 0:24d3eb812fd4 121 #define CCA_MODE_MASK 0x60
JMF 0:24d3eb812fd4 122 #define CCA_CHANNEL_MASK 0x1F
JMF 0:24d3eb812fd4 123
JMF 0:24d3eb812fd4 124 /*IRQ_MASK bits*/
JMF 0:24d3eb812fd4 125 #define RX_START 0x04
JMF 0:24d3eb812fd4 126 #define TRX_END 0x08
JMF 0:24d3eb812fd4 127 #define CCA_ED_DONE 0x10
JMF 0:24d3eb812fd4 128 #define AMI 0x20
JMF 0:24d3eb812fd4 129 #define TRX_UR 0x40
JMF 0:24d3eb812fd4 130
JMF 0:24d3eb812fd4 131 /*ANT_DIV bits*/
JMF 0:24d3eb812fd4 132 #define ANT_DIV_EN 0x08
JMF 0:24d3eb812fd4 133 #define ANT_EXT_SW_EN 0x04
JMF 0:24d3eb812fd4 134 #define ANT_CTRL_DEFAULT 0x03
JMF 0:24d3eb812fd4 135
JMF 0:24d3eb812fd4 136 /*TRX_CTRL_1 bits*/
JMF 0:24d3eb812fd4 137 #define PA_EXT_EN 0x80
JMF 0:24d3eb812fd4 138 #define TX_AUTO_CRC_ON 0x20
JMF 0:24d3eb812fd4 139 #define SPI_CMD_MODE_TRX_STATUS 0x04
JMF 0:24d3eb812fd4 140 #define SPI_CMD_MODE_PHY_RSSI 0x08
JMF 0:24d3eb812fd4 141 #define SPI_CMD_MODE_IRQ_STATUS 0x0C
JMF 0:24d3eb812fd4 142
JMF 0:24d3eb812fd4 143 /*TRX_CTRL_2 bits*/
JMF 0:24d3eb812fd4 144 #define RX_SAFE_MODE 0x80
JMF 0:24d3eb812fd4 145
JMF 0:24d3eb812fd4 146 /*FTN_CTRL bits*/
JMF 0:24d3eb812fd4 147 #define FTN_START 0x80
JMF 0:24d3eb812fd4 148
JMF 0:24d3eb812fd4 149 /*PHY_RSSI bits*/
JMF 0:24d3eb812fd4 150 #define CRC_VALID 0x80
JMF 0:24d3eb812fd4 151
JMF 0:24d3eb812fd4 152 /*RX_SYN bits*/
JMF 0:24d3eb812fd4 153 #define RX_PDT_DIS 0x80
JMF 0:24d3eb812fd4 154
JMF 0:24d3eb812fd4 155 /*TRX_RPC bits */
JMF 0:24d3eb812fd4 156 #define RX_RPC_CTRL 0xC0
JMF 0:24d3eb812fd4 157 #define RX_RPC_EN 0x20
JMF 0:24d3eb812fd4 158 #define PDT_RPC_EN 0x10
JMF 0:24d3eb812fd4 159 #define PLL_RPC_EN 0x08
JMF 0:24d3eb812fd4 160 #define XAH_TX_RPC_EN 0x04
JMF 0:24d3eb812fd4 161 #define IPAN_RPC_EN 0x02
JMF 0:24d3eb812fd4 162 #define TRX_RPC_RSVD_1 0x01
JMF 0:24d3eb812fd4 163
JMF 0:24d3eb812fd4 164 /*XAH_CTRL_1 bits*/
JMF 0:24d3eb812fd4 165 #define AACK_PROM_MODE 0x02
JMF 0:24d3eb812fd4 166
JMF 0:24d3eb812fd4 167
JMF 0:24d3eb812fd4 168 #ifdef __cplusplus
JMF 0:24d3eb812fd4 169 }
JMF 0:24d3eb812fd4 170 #endif
JMF 0:24d3eb812fd4 171
JMF 0:24d3eb812fd4 172 #endif /* AT86RFREG_H_ */