mille feuille / MCUGearALPC1114

This Automatic mode is the most simple lib for MCU Gear with LPC1114FN28. You don't need to think about Bank.

Dependents:   MCUGearALPC1114FN28

Fork of MCUGearA by mille feuille

MCUGearBaseALPC1114.cpp@2:aa2e471e8317, 2014-05-03 (annotated)

Committer:
Info
Date:
Sat May 03 17:09:14 2014 +0000
Revision:
2:aa2e471e8317
Parent:
MCUGearBaseA.cpp@1:95255bae41c8 
changed name

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Info 0:12d93184b350 1 /* MCU Gear Library, only for testing MCUGear without any circuit you connected.
Info 0:12d93184b350 2 * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
Info 0:12d93184b350 3 *
Info 0:12d93184b350 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
Info 0:12d93184b350 5 * of this software and associated documentation files (the "Software"), to deal
Info 0:12d93184b350 6 * in the Software without restriction, including without limitation the rights
Info 0:12d93184b350 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
Info 0:12d93184b350 8 * copies of the Software, and to permit persons to whom the Software is
Info 0:12d93184b350 9 * furnished to do so, subject to the following conditions:
Info 0:12d93184b350 10 *
Info 0:12d93184b350 11 * The above copyright notice and this permission notice shall be included in
Info 0:12d93184b350 12 * all copies or substantial portions of the Software.
Info 0:12d93184b350 13 *
Info 0:12d93184b350 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Info 0:12d93184b350 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Info 0:12d93184b350 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Info 0:12d93184b350 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Info 0:12d93184b350 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Info 0:12d93184b350 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Info 0:12d93184b350 20 * THE SOFTWARE.
Info 0:12d93184b350 21 */
Info 0:12d93184b350 22
Info 0:12d93184b350 23 #include "mbed.h"
Info 2:aa2e471e8317 24 #include "MCUGearBaseALPC1114.h"
Info 0:12d93184b350 25
Info 1:95255bae41c8 26 I2C fpga_i2c(dp5, dp27);
Info 0:12d93184b350 27
Info 0:12d93184b350 28 void fpga_write(int dev_adr,unsigned char adr, unsigned char data) {
Info 0:12d93184b350 29 char cmd[2];
Info 0:12d93184b350 30 cmd[0] = adr;
Info 0:12d93184b350 31 cmd[1] = data;
Info 1:95255bae41c8 32 //fpga_i2c.frequency (FPGA_I2C_CLOCK);
Info 0:12d93184b350 33 fpga_i2c.write(dev_adr, cmd, 2);
Info 0:12d93184b350 34
Info 0:12d93184b350 35 }
Info 0:12d93184b350 36
Info 0:12d93184b350 37 unsigned char fpga_read(int dev_adr,unsigned char adr) {
Info 0:12d93184b350 38 char cmd[2];
Info 0:12d93184b350 39 cmd[0] = adr;
Info 0:12d93184b350 40 fpga_i2c.write(dev_adr, cmd, 1);
Info 0:12d93184b350 41 fpga_i2c.read(dev_adr, cmd, 1);
Info 0:12d93184b350 42 return cmd[0];
Info 0:12d93184b350 43 }
Info 0:12d93184b350 44
Info 0:12d93184b350 45 void initBase(void){
Info 0:12d93184b350 46
Info 0:12d93184b350 47 // FPGA reg clear
Info 0:12d93184b350 48 for (int i=0;i<20;i++)
Info 0:12d93184b350 49 fpga_write(FPGA_I2C_ADR,0x80+i,0);
Info 0:12d93184b350 50
Info 0:12d93184b350 51 // read FPGA registers
Info 0:12d93184b350 52 fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0);
Info 0:12d93184b350 53 fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+1);
Info 0:12d93184b350 54 fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+2);
Info 0:12d93184b350 55 fpga_read(FPGA_I2C_ADR,FPGA_SYSINFO_0+3);
Info 0:12d93184b350 56 // FPGA enable
Info 0:12d93184b350 57 fpga_write(FPGA_I2C_ADR,FPGA_ENABLE,1);
Info 0:12d93184b350 58 }
Info 0:12d93184b350 59
Info 0:12d93184b350 60 void I2Cwrite(char addr, char data){
Info 0:12d93184b350 61
Info 0:12d93184b350 62 char cmd[1];
Info 0:12d93184b350 63 cmd[0] = data;
Info 0:12d93184b350 64 fpga_i2c.write(addr, cmd, 1);
Info 0:12d93184b350 65 //wait(0.01);
Info 0:12d93184b350 66
Info 0:12d93184b350 67 }
Info 0:12d93184b350 68
Info 0:12d93184b350 69 void changeBank(uint8_t bank){
Info 0:12d93184b350 70 fpga_write(FPGA_I2C_ADR,0x10,bank);
Info 0:12d93184b350 71 }
Info 0:12d93184b350 72
Info 0:12d93184b350 73 void deleteBank(uint8_t bank){
Info 0:12d93184b350 74 fpga_write(FPGA_I2C_ADR,0x0c,(bank|0x80));
Info 0:12d93184b350 75 fpga_write(FPGA_I2C_ADR,0x10, bank);
Info 0:12d93184b350 76 }
Info 0:12d93184b350 77 /*
Info 0:12d93184b350 78 void startReg(uint8_t bank){
Info 0:12d93184b350 79 fpga_write(FPGA_I2C_ADR,0x0c,bank);
Info 0:12d93184b350 80 }
Info 0:12d93184b350 81
Info 0:12d93184b350 82 void endReg(uint8_t bank){
Info 0:12d93184b350 83 fpga_write(FPGA_I2C_ADR,0x10, (bank|0x04));
Info 0:12d93184b350 84 }
Info 0:12d93184b350 85 */
Info 0:12d93184b350 86
Info 0:12d93184b350 87