Aukie Hooglugt
-
Diff: DMA.cpp
- Revision:
- 3:0f10f536456e
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/DMA.cpp Sun Nov 21 13:58:53 2010 +0000
@@ -0,0 +1,185 @@
+/*
+ Copyright (c) 2010 Andy Kirkham
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#include "MODSERIAL.h"
+#include "MACROS.h"
+
+#define DMA_CHANNEL_ENABLE 1
+
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART0_TX (8UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART0_RX (9UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART1_TX (10UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART1_RX (11UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART2_TX (12UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART2_RX (13UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART3_TX (14UL << 1)
+#define DMA_CHANNEL_SRC_PERIPHERAL_UART3_RX (15UL << 1)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART0_TX (8UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART0_RX (9UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART1_TX (10UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART1_RX (11UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART2_TX (12UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART2_RX (13UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART3_TX (14UL << 6)
+#define DMA_CHANNEL_DST_PERIPHERAL_UART3_RX (15UL << 6)
+
+#define DMA_CHANNEL_SRC_INC (1UL << 26)
+#define DMA_CHANNEL_DST_INC (1UL << 27)
+#define DMA_CHANNEL_TCIE (1UL << 31)
+#define DMA_TRANSFER_TYPE_M2M (0UL << 11)
+#define DMA_TRANSFER_TYPE_M2P (1UL << 11)
+#define DMA_TRANSFER_TYPE_P2M (2UL << 11)
+#define DMA_TRANSFER_TYPE_P2P (3UL << 11)
+#define DMA_MASK_IE (1UL << 14)
+#define DMA_MASK_ITC (1UL << 15)
+#define DMA_LOCK (1UL << 16)
+#define DMA_ACTIVE (1UL << 17)
+#define DMA_HALT (1UL << 18)
+
+namespace AjK {
+
+extern "C" void isr_dma_core(void);
+
+class MODSERIAL *modserial_this[4] = {
+ (class MODSERIAL *)NULL,
+ (class MODSERIAL *)NULL,
+ (class MODSERIAL *)NULL,
+ (class MODSERIAL *)NULL };
+
+uint32_t old_dma_vector = 0;
+typedef void (*MODSERIALFN)(void);
+
+
+
+int
+MODSERIAL::dmaSend(char *buffer, int length, dmaChannel q)
+{
+ LPC_GPDMACH_TypeDef *dma_base = dmaSetup(q);
+
+ switch( _uidx ) {
+ case 0: LPC_UART0->DMAREQSEL &= ~(1UL << 0) & 0xFF; break;
+ case 1: LPC_UART0->DMAREQSEL &= ~(1UL << 2) & 0xFF; break;
+ case 2: LPC_UART0->DMAREQSEL &= ~(1UL << 4) & 0xFF; break;
+ case 3: LPC_UART0->DMAREQSEL &= ~(1UL << 6) & 0xFF; break;
+ default: error("No _uidx to request select for DMA UART peripheral destination.");
+ }
+
+ dma_base->DMACCSrcAddr = (uint32_t)buffer;
+ dma_base->DMACCDestAddr = (uint32_t)_base + MODSERIAL_THR;
+ dma_base->DMACCLLI = 0;
+ dma_base->DMACCControl = DMA_CHANNEL_TCIE | DMA_CHANNEL_SRC_INC | (uint32_t)length;
+
+ uint32_t DestPeripheral = DMA_CHANNEL_DST_PERIPHERAL_UART0_TX;
+ switch ( _uidx ) {
+ case 0: DestPeripheral = DMA_CHANNEL_DST_PERIPHERAL_UART0_TX; break;
+ case 1: DestPeripheral = DMA_CHANNEL_DST_PERIPHERAL_UART1_TX; break;
+ case 2: DestPeripheral = DMA_CHANNEL_DST_PERIPHERAL_UART2_TX; break;
+ case 3: DestPeripheral = DMA_CHANNEL_DST_PERIPHERAL_UART3_TX; break;
+ default: error("No _uidx to identify DMA peripheral destination."); // Redundent.
+ }
+
+ /* Enable SSP0 DMA. */
+ //LPC_SSP0->DMACR = 0x3;
+
+ // Enable Channel
+ dma_base->DMACCConfig = DMA_CHANNEL_ENABLE |
+ DestPeripheral |
+ DMA_TRANSFER_TYPE_M2P |
+ DMA_MASK_IE |
+ DMA_MASK_ITC;
+
+ /* Wait until at least one byte has arrived into the RX FIFO
+ and then start-up the Channel1 DMA to begin transferring them. */
+ // while((LPC_SSP0->SR & (1UL << 2)) == 0);
+
+ /* Enable Channel1 */
+ /*
+ LPC_GPDMACH1->DMACCConfig = DMA_CHANNEL_ENABLE |
+ DMA_CHANNEL_SRC_PERIPHERAL_SSP0_RX |
+ DMA_TRANSFER_TYPE_P2M |
+ DMA_MASK_IE |
+ DMA_MASK_ITC;
+ */
+
+ /* SSP0 CS line and "page_read_in_progress" flag are now
+ under DMA/SSP0 interrupt control. See the DMA ISR handlers
+ and SSP0 ISR handlers for more information. */
+
+ return 1;
+}
+
+void
+MODSERIAL::isr_tx_dma(void)
+{
+
+}
+
+void
+MODSERIAL::isr_rx_dma(void)
+{
+
+}
+
+LPC_GPDMACH_TypeDef *
+MODSERIAL::dmaSetup(dmaChannel q)
+{
+ if (LPC_SC->PCONP & (1UL << 29) == 0 ) {
+ LPC_SC->PCONP |= (1UL << 29);
+ LPC_GPDMA->DMACConfig = 1;
+ }
+
+ if ( old_dma_vector == NULL ) old_dma_vector = NVIC_GetVector(DMA_IRQn);
+ NVIC_SetVector(DMA_IRQn, (uint32_t)isr_dma_core);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ modserial_this[_uidx] = this;
+
+ LPC_GPDMA->DMACIntTCClear = (1UL << (int)dmaInUse);
+
+ LPC_GPDMACH_TypeDef *dma_base = dmaSelectChannel( q );
+ return dma_base;
+}
+
+void
+MODSERIAL::this_reset(void)
+{
+ modserial_this[_uidx] = (class MODSERIAL *)NULL;
+}
+
+extern "C" void isr_dma_core(void)
+{
+ for (int i = 0; i < 4; i++) {
+ if (modserial_this[i] != (class MODSERIAL *)NULL) {
+ if (modserial_this[i]->dmaInUse[MODSERIAL::RxIrq] != MODSERIAL::NotInUse) {
+ modserial_this[i]->isr_rx_dma();
+ }
+ if (modserial_this[i]->dmaInUse[MODSERIAL::TxIrq] != MODSERIAL::NotInUse) {
+ modserial_this[i]->isr_tx_dma();
+ }
+ }
+ }
+ if (old_dma_vector) {
+ ((MODSERIALFN)old_dma_vector)();
+ }
+}
+
+}; // namespace AjK ends