Kim GiJeong
/
cocoa_STM_ver_BIPOLAR
cocoa_STM_ver_BIPOLAR
INIT_HW/INIT_HW.cpp
- Committer:
- GiJeongKim
- Date:
- 2019-08-20
- Revision:
- 1:be9b2f6d39c2
- Parent:
- 0:51c43836c1d7
File content as of revision 1:be9b2f6d39c2:
#include "mbed.h" #include "FastPWM.h" #include "setting.h" void Init_ADC(void){ // ADC Setup RCC->APB2ENR |= RCC_APB2ENR_ADC3EN; // clock for ADC3 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // Enable clock for GPIOC RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // Enable clock for GPIOA ADC->CCR = 0x00000016; // Regular simultaneous mode only ADC1->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC1 ON ADC1->SQR3 = 0x0000000E; //channel // use PC_4 as input- ADC1_IN14 ADC2->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC2 ON ADC2->SQR3 = 0x00000008; // use PB_0 as input - ADC2_IN8 ADC3->CR2 |= ADC_CR2_ADON; // ADC3 ON ADC3->SQR3 = 0x0000000B; // use PC_1, - ADC3_IN11 GPIOC->MODER |= 0b1100001100; //each channel // PC_4, PC_1 are analog inputs GPIOB->MODER |= 0x3; // PB_0 as analog input ADC1->SMPR1 |= 0x1000; // 15 cycles on CH_14, 0b 001000000000000 ADC2->SMPR1 |= 0x1000000; // 15 cycles on CH_8, 2^24 = 16^6 ADC3->SMPR2 |= 0b1000; // 15 cycles on CH_11, 0b 001000; } void Init_PWM(){ RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clock FastPWM pwm_a(PIN_V); // 단순히 핀 설정용 FastPWM pwm_b(PIN_W); //ISR Setup NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ TIM1->DIER |= TIM_DIER_UIE; // enable update interrupt TIM1->CR1 = 0x40; // CMS = 10, interrupt only when counting up // Center-aligned mode TIM1->CR1 |= TIM_CR1_UDIS; TIM1->CR1 |= TIM_CR1_ARPE; // autoreload on, TIM1->RCR |= 0x001; // update event once per up/down count of tim1 TIM1->EGR |= TIM_EGR_UG; //PWM Setup TIM1->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock TIM1->ARR = PWM_ARR; // set auto reload, 40 khz // TIM1->CCER |= ~(TIM_CCER_CC1NP); // Interupt when low side is on. TIM1->CR1 |= TIM_CR1_CEN; // enable TIM1 // for complementary TIM1->CCER|=0b1111; }