Kim GiJeong
/
cocoa_STM_ver_BIPOLAR
cocoa_STM_ver_BIPOLAR
INIT_HW/INIT_HW.cpp@1:be9b2f6d39c2, 2019-08-20 (annotated)
- Committer:
- GiJeongKim
- Date:
- Tue Aug 20 12:35:26 2019 +0000
- Revision:
- 1:be9b2f6d39c2
- Parent:
- 0:51c43836c1d7
abc;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GiJeongKim | 0:51c43836c1d7 | 1 | #include "mbed.h" |
GiJeongKim | 0:51c43836c1d7 | 2 | #include "FastPWM.h" |
GiJeongKim | 0:51c43836c1d7 | 3 | #include "setting.h" |
GiJeongKim | 0:51c43836c1d7 | 4 | |
GiJeongKim | 0:51c43836c1d7 | 5 | void Init_ADC(void){ |
GiJeongKim | 0:51c43836c1d7 | 6 | // ADC Setup |
GiJeongKim | 0:51c43836c1d7 | 7 | RCC->APB2ENR |= RCC_APB2ENR_ADC3EN; // clock for ADC3 |
GiJeongKim | 0:51c43836c1d7 | 8 | RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2 |
GiJeongKim | 0:51c43836c1d7 | 9 | RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1 |
GiJeongKim | 0:51c43836c1d7 | 10 | |
GiJeongKim | 0:51c43836c1d7 | 11 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // Enable clock for GPIOC |
GiJeongKim | 0:51c43836c1d7 | 12 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // Enable clock for GPIOA |
GiJeongKim | 0:51c43836c1d7 | 13 | |
GiJeongKim | 0:51c43836c1d7 | 14 | ADC->CCR = 0x00000016; // Regular simultaneous mode only |
GiJeongKim | 0:51c43836c1d7 | 15 | ADC1->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC1 ON |
GiJeongKim | 0:51c43836c1d7 | 16 | ADC1->SQR3 = 0x0000000E; //channel // use PC_4 as input- ADC1_IN14 |
GiJeongKim | 0:51c43836c1d7 | 17 | ADC2->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC2 ON |
GiJeongKim | 0:51c43836c1d7 | 18 | ADC2->SQR3 = 0x00000008; // use PB_0 as input - ADC2_IN8 |
GiJeongKim | 0:51c43836c1d7 | 19 | ADC3->CR2 |= ADC_CR2_ADON; // ADC3 ON |
GiJeongKim | 0:51c43836c1d7 | 20 | ADC3->SQR3 = 0x0000000B; // use PC_1, - ADC3_IN11 |
GiJeongKim | 0:51c43836c1d7 | 21 | GPIOC->MODER |= 0b1100001100; //each channel // PC_4, PC_1 are analog inputs |
GiJeongKim | 0:51c43836c1d7 | 22 | GPIOB->MODER |= 0x3; // PB_0 as analog input |
GiJeongKim | 0:51c43836c1d7 | 23 | |
GiJeongKim | 0:51c43836c1d7 | 24 | ADC1->SMPR1 |= 0x1000; // 15 cycles on CH_14, 0b 001000000000000 |
GiJeongKim | 0:51c43836c1d7 | 25 | ADC2->SMPR1 |= 0x1000000; // 15 cycles on CH_8, 2^24 = 16^6 |
GiJeongKim | 0:51c43836c1d7 | 26 | ADC3->SMPR2 |= 0b1000; // 15 cycles on CH_11, 0b 001000; |
GiJeongKim | 0:51c43836c1d7 | 27 | |
GiJeongKim | 0:51c43836c1d7 | 28 | } |
GiJeongKim | 0:51c43836c1d7 | 29 | |
GiJeongKim | 0:51c43836c1d7 | 30 | |
GiJeongKim | 0:51c43836c1d7 | 31 | |
GiJeongKim | 0:51c43836c1d7 | 32 | void Init_PWM(){ |
GiJeongKim | 0:51c43836c1d7 | 33 | |
GiJeongKim | 1:be9b2f6d39c2 | 34 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clock |
GiJeongKim | 1:be9b2f6d39c2 | 35 | |
GiJeongKim | 1:be9b2f6d39c2 | 36 | FastPWM pwm_a(PIN_V); // 단순히 핀 설정용 |
GiJeongKim | 1:be9b2f6d39c2 | 37 | FastPWM pwm_b(PIN_W); |
GiJeongKim | 0:51c43836c1d7 | 38 | |
GiJeongKim | 0:51c43836c1d7 | 39 | //ISR Setup |
GiJeongKim | 0:51c43836c1d7 | 40 | |
GiJeongKim | 1:be9b2f6d39c2 | 41 | NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ |
GiJeongKim | 0:51c43836c1d7 | 42 | |
GiJeongKim | 1:be9b2f6d39c2 | 43 | TIM1->DIER |= TIM_DIER_UIE; // enable update interrupt |
GiJeongKim | 1:be9b2f6d39c2 | 44 | TIM1->CR1 = 0x40; // CMS = 10, interrupt only when counting up // Center-aligned mode |
GiJeongKim | 1:be9b2f6d39c2 | 45 | TIM1->CR1 |= TIM_CR1_UDIS; |
GiJeongKim | 1:be9b2f6d39c2 | 46 | TIM1->CR1 |= TIM_CR1_ARPE; // autoreload on, |
GiJeongKim | 1:be9b2f6d39c2 | 47 | TIM1->RCR |= 0x001; // update event once per up/down count of tim1 |
GiJeongKim | 1:be9b2f6d39c2 | 48 | TIM1->EGR |= TIM_EGR_UG; |
GiJeongKim | 1:be9b2f6d39c2 | 49 | |
GiJeongKim | 1:be9b2f6d39c2 | 50 | |
GiJeongKim | 0:51c43836c1d7 | 51 | |
GiJeongKim | 0:51c43836c1d7 | 52 | //PWM Setup |
GiJeongKim | 0:51c43836c1d7 | 53 | |
GiJeongKim | 1:be9b2f6d39c2 | 54 | TIM1->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock |
GiJeongKim | 1:be9b2f6d39c2 | 55 | TIM1->ARR = PWM_ARR; // set auto reload, 40 khz |
GiJeongKim | 1:be9b2f6d39c2 | 56 | // TIM1->CCER |= ~(TIM_CCER_CC1NP); // Interupt when low side is on. |
GiJeongKim | 1:be9b2f6d39c2 | 57 | TIM1->CR1 |= TIM_CR1_CEN; // enable TIM1 |
GiJeongKim | 0:51c43836c1d7 | 58 | |
GiJeongKim | 1:be9b2f6d39c2 | 59 | // for complementary |
GiJeongKim | 1:be9b2f6d39c2 | 60 | TIM1->CCER|=0b1111; |
GiJeongKim | 1:be9b2f6d39c2 | 61 | } |