Eric Lewiston
Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
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STM32L4xx_HAL_Driver
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stm32l4xx_ll_bus.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of BUS LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_BUS_H 00040 #define __STM32L4xx_LL_BUS_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined(RCC) 00054 00055 /** @defgroup BUS_LL BUS 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 /* Exported constants --------------------------------------------------------*/ 00068 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00073 * @{ 00074 */ 00075 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF 00076 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00077 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00078 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN 00079 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00080 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN 00081 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN 00082 /** 00083 * @} 00084 */ 00085 00086 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00087 * @{ 00088 */ 00089 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN 00090 #define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF 00091 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN 00092 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN 00093 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN 00094 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN 00095 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN 00096 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN 00097 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN 00098 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN 00099 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00100 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN 00101 #if defined(AES) 00102 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00103 #endif 00104 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00105 /** 00106 * @} 00107 */ 00108 00109 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00110 * @{ 00111 */ 00112 #define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF 00113 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00114 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00115 /** 00116 * @} 00117 */ 00118 00119 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00120 * @{ 00121 */ 00122 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF 00123 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN 00124 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN 00125 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN 00126 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN 00127 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN 00128 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN 00129 #if defined(LCD) 00130 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN 00131 #endif 00132 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN 00133 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN 00134 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN 00135 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN 00136 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN 00137 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN 00138 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN 00139 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN 00140 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN 00141 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN 00142 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN 00143 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN 00144 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN 00145 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN 00146 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN 00147 /** 00148 * @} 00149 */ 00150 00151 00152 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 00153 * @{ 00154 */ 00155 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFF 00156 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN 00157 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN 00158 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00164 * @{ 00165 */ 00166 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF 00167 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00168 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN 00169 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 00170 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00171 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00172 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00173 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00174 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00175 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00176 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00177 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00178 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00179 #define LL_APB2_GRP1_PERIPH_DFSDM RCC_APB2ENR_DFSDMEN 00180 /** 00181 * @} 00182 */ 00183 00184 /** 00185 * @} 00186 */ 00187 00188 /* Exported macro ------------------------------------------------------------*/ 00189 /* Exported functions --------------------------------------------------------*/ 00190 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00191 * @{ 00192 */ 00193 00194 /** @defgroup BUS_LL_EF_AHB1 AHB1 00195 * @{ 00196 */ 00197 00198 /** 00199 * @brief Enable AHB1 peripherals clock. 00200 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00201 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00202 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n 00203 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00204 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock 00205 * @param Periphs This parameter can be a combination of the following values: 00206 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00207 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00208 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00209 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00210 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00211 * @retval None 00212 */ 00213 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00214 { 00215 SET_BIT(RCC->AHB1ENR, Periphs); 00216 } 00217 00218 /** 00219 * @brief Check if AHB1 peripheral clock is enabled or not 00220 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00221 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00222 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n 00223 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00224 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock 00225 * @param Periphs This parameter can be a combination of the following values: 00226 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00227 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00228 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00229 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00230 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00231 * @retval uint32_t 00232 */ 00233 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00234 { 00235 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 00236 } 00237 00238 /** 00239 * @brief Disable AHB1 peripherals clock. 00240 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00241 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00242 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n 00243 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00244 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock 00245 * @param Periphs This parameter can be a combination of the following values: 00246 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00247 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00248 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00249 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00250 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00251 * @retval None 00252 */ 00253 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00254 { 00255 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00256 } 00257 00258 /** 00259 * @brief Force AHB1 peripherals reset. 00260 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00261 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00262 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n 00263 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00264 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset 00265 * @param Periphs This parameter can be a combination of the following values: 00266 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00267 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00268 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00269 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00270 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00271 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00272 * @retval None 00273 */ 00274 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00275 { 00276 SET_BIT(RCC->AHB1RSTR, Periphs); 00277 } 00278 00279 /** 00280 * @brief Release AHB1 peripherals reset. 00281 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00282 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00283 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n 00284 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00285 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset 00286 * @param Periphs This parameter can be a combination of the following values: 00287 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00288 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00289 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00290 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00291 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00292 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00293 * @retval None 00294 */ 00295 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00296 { 00297 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00298 } 00299 00300 /** 00301 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes 00302 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00303 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00304 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00305 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00306 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00307 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep 00308 * @param Periphs This parameter can be a combination of the following values: 00309 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00310 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00311 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00312 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00313 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00314 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00315 * @retval None 00316 */ 00317 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 00318 { 00319 SET_BIT(RCC->AHB1SMENR, Periphs); 00320 } 00321 00322 /** 00323 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes 00324 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00325 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00326 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00327 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00328 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00329 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep 00330 * @param Periphs This parameter can be a combination of the following values: 00331 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00333 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00334 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00335 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00336 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00337 * @retval None 00338 */ 00339 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 00340 { 00341 CLEAR_BIT(RCC->AHB1SMENR, Periphs); 00342 } 00343 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup BUS_LL_EF_AHB2 AHB2 00349 * @{ 00350 */ 00351 00352 /** 00353 * @brief Enable AHB2 peripherals clock. 00354 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n 00355 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n 00356 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n 00357 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n 00358 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n 00359 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n 00360 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n 00361 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n 00362 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n 00363 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n 00364 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00365 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock 00366 * @param Periphs This parameter can be a combination of the following values: 00367 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00368 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00369 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00370 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00371 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00372 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00373 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00374 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00375 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00376 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00377 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00378 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00379 * (*) value not defined in all devices. 00380 * @retval None 00381 */ 00382 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00383 { 00384 SET_BIT(RCC->AHB2ENR, Periphs); 00385 } 00386 00387 /** 00388 * @brief Check if AHB2 peripheral clock is enabled or not 00389 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n 00390 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n 00391 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n 00392 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n 00393 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n 00394 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n 00395 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n 00396 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n 00397 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n 00398 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n 00399 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00400 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock 00401 * @param Periphs This parameter can be a combination of the following values: 00402 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00403 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00404 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00405 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00406 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00407 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00408 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00409 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00410 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00411 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00412 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00413 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00414 * (*) value not defined in all devices. 00415 * @retval uint32_t 00416 */ 00417 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00418 { 00419 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 00420 } 00421 00422 /** 00423 * @brief Disable AHB2 peripherals clock. 00424 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n 00425 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n 00426 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n 00427 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n 00428 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n 00429 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n 00430 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n 00431 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n 00432 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n 00433 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n 00434 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00435 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock 00436 * @param Periphs This parameter can be a combination of the following values: 00437 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00438 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00439 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00440 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00441 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00442 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00443 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00444 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00445 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00446 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00447 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00448 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00449 * (*) value not defined in all devices. 00450 * @retval None 00451 */ 00452 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00453 { 00454 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00455 } 00456 00457 /** 00458 * @brief Force AHB2 peripherals reset. 00459 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n 00460 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n 00461 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n 00462 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n 00463 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n 00464 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n 00465 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n 00466 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n 00467 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n 00468 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n 00469 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00470 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset 00471 * @param Periphs This parameter can be a combination of the following values: 00472 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00473 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00474 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00475 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00476 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00477 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00478 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00479 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00480 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00481 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00482 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00483 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00484 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00485 * (*) value not defined in all devices. 00486 * @retval None 00487 */ 00488 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00489 { 00490 SET_BIT(RCC->AHB2RSTR, Periphs); 00491 } 00492 00493 /** 00494 * @brief Release AHB2 peripherals reset. 00495 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n 00496 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n 00497 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n 00498 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n 00499 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n 00500 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n 00501 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n 00502 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n 00503 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n 00504 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n 00505 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00506 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset 00507 * @param Periphs This parameter can be a combination of the following values: 00508 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00509 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00510 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00511 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00512 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00513 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00514 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00515 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00516 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00517 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00518 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00519 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00520 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00521 * (*) value not defined in all devices. 00522 * @retval None 00523 */ 00524 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00525 { 00526 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00527 } 00528 00529 /** 00530 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes 00531 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00532 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00533 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00534 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00535 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00536 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00537 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00538 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00539 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00540 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00541 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00542 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00543 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep 00544 * @param Periphs This parameter can be a combination of the following values: 00545 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00551 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00552 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00553 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00554 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00555 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00556 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00557 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00558 * (*) value not defined in all devices. 00559 * @retval None 00560 */ 00561 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 00562 { 00563 SET_BIT(RCC->AHB2SMENR, Periphs); 00564 } 00565 00566 /** 00567 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes 00568 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00569 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00570 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00571 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00572 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00573 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00574 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00575 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00576 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00577 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00578 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00579 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00580 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep 00581 * @param Periphs This parameter can be a combination of the following values: 00582 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00583 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00584 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00585 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD 00586 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE 00587 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF 00588 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG 00589 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00590 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00591 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS 00592 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00593 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00594 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00595 * (*) value not defined in all devices. 00596 * @retval None 00597 */ 00598 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 00599 { 00600 CLEAR_BIT(RCC->AHB2SMENR, Periphs); 00601 } 00602 00603 /** 00604 * @} 00605 */ 00606 00607 /** @defgroup BUS_LL_EF_AHB3 AHB3 00608 * @{ 00609 */ 00610 00611 /** 00612 * @brief Enable AHB3 peripherals clock. 00613 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00614 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 00615 * @param Periphs This parameter can be a combination of the following values: 00616 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00617 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00618 * @retval None 00619 */ 00620 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00621 { 00622 SET_BIT(RCC->AHB3ENR, Periphs); 00623 } 00624 00625 /** 00626 * @brief Check if AHB3 peripheral clock is enabled or not 00627 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00628 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 00629 * @param Periphs This parameter can be a combination of the following values: 00630 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00631 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00632 * @retval uint32_t 00633 */ 00634 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 00635 { 00636 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 00637 } 00638 00639 /** 00640 * @brief Disable AHB3 peripherals clock. 00641 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 00642 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 00643 * @param Periphs This parameter can be a combination of the following values: 00644 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00645 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00646 * @retval None 00647 */ 00648 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 00649 { 00650 CLEAR_BIT(RCC->AHB3ENR, Periphs); 00651 } 00652 00653 /** 00654 * @brief Force AHB3 peripherals reset. 00655 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 00656 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 00657 * @param Periphs This parameter can be a combination of the following values: 00658 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 00659 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00660 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00661 * @retval None 00662 */ 00663 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 00664 { 00665 SET_BIT(RCC->AHB3RSTR, Periphs); 00666 } 00667 00668 /** 00669 * @brief Release AHB3 peripherals reset. 00670 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 00671 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 00672 * @param Periphs This parameter can be a combination of the following values: 00673 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00674 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00675 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00676 * @retval None 00677 */ 00678 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 00679 { 00680 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 00681 } 00682 00683 /** 00684 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes 00685 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00686 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep 00687 * @param Periphs This parameter can be a combination of the following values: 00688 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00689 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00690 * @retval None 00691 */ 00692 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) 00693 { 00694 SET_BIT(RCC->AHB3SMENR, Periphs); 00695 } 00696 00697 /** 00698 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes 00699 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n 00700 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep 00701 * @param Periphs This parameter can be a combination of the following values: 00702 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 00703 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00704 * @retval None 00705 */ 00706 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) 00707 { 00708 CLEAR_BIT(RCC->AHB3SMENR, Periphs); 00709 } 00710 00711 /** 00712 * @} 00713 */ 00714 00715 /** @defgroup BUS_LL_EF_APB1 APB1 00716 * @{ 00717 */ 00718 00719 /** 00720 * @brief Enable APB1 peripherals clock. 00721 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n 00722 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n 00723 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n 00724 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n 00725 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n 00726 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n 00727 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n 00728 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n 00729 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n 00730 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n 00731 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n 00732 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n 00733 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n 00734 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n 00735 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n 00736 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n 00737 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n 00738 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n 00739 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n 00740 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n 00741 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n 00742 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock 00743 * @param Periphs This parameter can be a combination of the following values: 00744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00746 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 00747 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 00748 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00749 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00750 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00751 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00752 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 00753 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00754 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00755 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 00756 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 00757 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 00758 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00759 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 00760 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00761 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00762 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00763 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00764 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00765 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00766 * (*) value not defined in all devices. 00767 * @retval None 00768 */ 00769 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 00770 { 00771 SET_BIT(RCC->APB1ENR1, Periphs); 00772 } 00773 00774 /** 00775 * @brief Enable APB1 peripherals clock. 00776 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n 00777 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n 00778 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock 00779 * @param Periphs This parameter can be a combination of the following values: 00780 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00781 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00782 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 00783 * @retval None 00784 */ 00785 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 00786 { 00787 SET_BIT(RCC->APB1ENR2, Periphs); 00788 } 00789 00790 /** 00791 * @brief Check if APB1 peripheral clock is enabled or not 00792 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n 00793 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n 00794 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n 00795 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n 00796 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n 00797 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n 00798 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n 00799 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n 00800 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n 00801 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n 00802 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n 00803 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n 00804 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n 00805 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n 00806 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n 00807 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n 00808 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n 00809 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n 00810 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n 00811 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n 00812 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n 00813 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock 00814 * @param Periphs This parameter can be a combination of the following values: 00815 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00816 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00817 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 00818 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 00819 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00820 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00821 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00822 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00823 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 00824 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00825 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00826 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 00827 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 00828 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 00829 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00830 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 00831 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00832 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00833 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00834 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00835 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00836 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00837 * (*) value not defined in all devices. 00838 * @retval uint32_t 00839 */ 00840 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 00841 { 00842 return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); 00843 } 00844 00845 /** 00846 * @brief Check if APB1 peripheral clock is enabled or not 00847 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n 00848 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n 00849 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock 00850 * @param Periphs This parameter can be a combination of the following values: 00851 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00852 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00853 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 00854 * @retval uint32_t 00855 */ 00856 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 00857 { 00858 return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); 00859 } 00860 00861 /** 00862 * @brief Disable APB1 peripherals clock. 00863 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n 00864 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n 00865 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n 00866 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n 00867 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n 00868 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n 00869 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n 00870 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n 00871 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n 00872 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n 00873 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n 00874 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n 00875 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n 00876 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n 00877 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n 00878 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n 00879 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n 00880 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n 00881 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n 00882 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n 00883 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n 00884 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock 00885 * @param Periphs This parameter can be a combination of the following values: 00886 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00887 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00888 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 00889 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 00890 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00891 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00892 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00893 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00894 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 00895 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00896 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00897 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 00898 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 00899 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 00900 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00901 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 00902 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00903 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00904 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00905 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00906 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00907 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00908 * (*) value not defined in all devices. 00909 * @retval None 00910 */ 00911 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 00912 { 00913 CLEAR_BIT(RCC->APB1ENR1, Periphs); 00914 } 00915 00916 /** 00917 * @brief Disable APB1 peripherals clock. 00918 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n 00919 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n 00920 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock 00921 * @param Periphs This parameter can be a combination of the following values: 00922 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00923 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00924 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 00925 * @retval None 00926 */ 00927 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 00928 { 00929 CLEAR_BIT(RCC->APB1ENR2, Periphs); 00930 } 00931 00932 /** 00933 * @brief Force APB1 peripherals reset. 00934 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n 00935 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n 00936 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n 00937 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n 00938 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n 00939 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n 00940 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n 00941 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n 00942 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n 00943 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n 00944 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n 00945 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n 00946 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n 00947 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n 00948 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n 00949 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n 00950 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n 00951 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n 00952 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n 00953 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n 00954 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset 00955 * @param Periphs This parameter can be a combination of the following values: 00956 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 00957 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00958 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00959 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 00960 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 00961 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00962 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00963 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00964 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 00965 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00966 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00967 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 00968 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 00969 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 00970 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00971 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 00972 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00973 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00974 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00975 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00976 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00977 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00978 * (*) value not defined in all devices. 00979 * @retval None 00980 */ 00981 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 00982 { 00983 SET_BIT(RCC->APB1RSTR1, Periphs); 00984 } 00985 00986 /** 00987 * @brief Force APB1 peripherals reset. 00988 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n 00989 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n 00990 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset 00991 * @param Periphs This parameter can be a combination of the following values: 00992 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 00993 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00994 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00995 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 00996 * @retval None 00997 */ 00998 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 00999 { 01000 SET_BIT(RCC->APB1RSTR2, Periphs); 01001 } 01002 01003 /** 01004 * @brief Release APB1 peripherals reset. 01005 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n 01006 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n 01007 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n 01008 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n 01009 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n 01010 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n 01011 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n 01012 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n 01013 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n 01014 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n 01015 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n 01016 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n 01017 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n 01018 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n 01019 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n 01020 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n 01021 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n 01022 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n 01023 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n 01024 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n 01025 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset 01026 * @param Periphs This parameter can be a combination of the following values: 01027 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01034 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01035 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01036 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01037 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01038 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01039 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01040 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01041 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01042 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01043 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01044 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01045 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01046 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01047 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01048 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01049 * (*) value not defined in all devices. 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01053 { 01054 CLEAR_BIT(RCC->APB1RSTR1, Periphs); 01055 } 01056 01057 /** 01058 * @brief Release APB1 peripherals reset. 01059 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n 01060 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n 01061 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset 01062 * @param Periphs This parameter can be a combination of the following values: 01063 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01064 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01065 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01066 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01067 * @retval None 01068 */ 01069 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 01070 { 01071 CLEAR_BIT(RCC->APB1RSTR2, Periphs); 01072 } 01073 01074 /** 01075 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01076 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01077 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01078 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01079 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01080 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01081 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01082 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01083 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01084 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01085 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01086 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01087 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01088 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01089 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01090 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01091 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01092 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01093 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01094 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01095 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01096 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01097 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep 01098 * @param Periphs This parameter can be a combination of the following values: 01099 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01100 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01101 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01102 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01103 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01104 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01105 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01106 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01107 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01108 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01109 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01110 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01111 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01112 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01113 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01114 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01115 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01116 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01117 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01118 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01119 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01120 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01121 * (*) value not defined in all devices. 01122 * @retval None 01123 */ 01124 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 01125 { 01126 SET_BIT(RCC->APB1SMENR1, Periphs); 01127 } 01128 01129 /** 01130 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01131 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01132 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01133 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep 01134 * @param Periphs This parameter can be a combination of the following values: 01135 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01136 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01137 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01138 * @retval None 01139 */ 01140 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) 01141 { 01142 SET_BIT(RCC->APB1SMENR2, Periphs); 01143 } 01144 01145 /** 01146 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01147 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01148 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01149 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01150 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01151 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01152 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01153 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01154 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01155 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01156 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01157 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01158 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01159 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01160 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01161 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01162 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01163 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01164 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01165 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01166 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01167 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01168 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep 01169 * @param Periphs This parameter can be a combination of the following values: 01170 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01171 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 01172 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 01173 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01174 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01176 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01177 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01178 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 01179 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01180 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01181 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 01182 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 01183 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 01184 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01185 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01186 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01187 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01188 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01189 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01190 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01191 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01192 * (*) value not defined in all devices. 01193 * @retval None 01194 */ 01195 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 01196 { 01197 CLEAR_BIT(RCC->APB1SMENR1, Periphs); 01198 } 01199 01200 /** 01201 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01202 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01203 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01204 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep 01205 * @param Periphs This parameter can be a combination of the following values: 01206 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01207 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01208 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01209 * @retval None 01210 */ 01211 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) 01212 { 01213 CLEAR_BIT(RCC->APB1SMENR2, Periphs); 01214 } 01215 01216 /** 01217 * @} 01218 */ 01219 01220 /** @defgroup BUS_LL_EF_APB2 APB2 01221 * @{ 01222 */ 01223 01224 /** 01225 * @brief Enable APB2 peripherals clock. 01226 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01227 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n 01228 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 01229 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01230 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01231 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01232 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01233 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 01234 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 01235 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 01236 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01237 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01238 * APB2ENR DFSDMEN LL_APB2_GRP1_EnableClock 01239 * @param Periphs This parameter can be a combination of the following values: 01240 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01241 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01242 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01243 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01244 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01245 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01246 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01247 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01248 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01249 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01250 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01251 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01252 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01253 * @retval None 01254 */ 01255 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01256 { 01257 SET_BIT(RCC->APB2ENR, Periphs); 01258 } 01259 01260 /** 01261 * @brief Check if APB2 peripheral clock is enabled or not 01262 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01263 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n 01264 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n 01265 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01266 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01267 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01268 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01269 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 01270 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 01271 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 01272 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01273 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01274 * APB2ENR DFSDMEN LL_APB2_GRP1_IsEnabledClock 01275 * @param Periphs This parameter can be a combination of the following values: 01276 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01277 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01278 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01279 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01280 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01281 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01282 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01283 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01284 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01285 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01286 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01287 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01288 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01289 * @retval uint32_t 01290 */ 01291 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01292 { 01293 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 01294 } 01295 01296 /** 01297 * @brief Disable APB2 peripherals clock. 01298 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01299 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n 01300 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01301 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01302 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01303 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01304 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 01305 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 01306 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 01307 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01308 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01309 * APB2ENR DFSDMEN LL_APB2_GRP1_DisableClock 01310 * @param Periphs This parameter can be a combination of the following values: 01311 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01312 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01313 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01314 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01315 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01316 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01317 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01318 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01319 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01320 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01321 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01322 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01323 * @retval None 01324 */ 01325 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01326 { 01327 CLEAR_BIT(RCC->APB2ENR, Periphs); 01328 } 01329 01330 /** 01331 * @brief Force APB2 peripherals reset. 01332 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01333 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n 01334 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01335 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01336 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01337 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01338 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 01339 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 01340 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 01341 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01342 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01343 * APB2RSTR DFSDMRST LL_APB2_GRP1_ForceReset 01344 * @param Periphs This parameter can be a combination of the following values: 01345 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01346 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01347 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01348 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01349 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01350 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01351 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01352 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01353 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01354 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01355 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01356 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01357 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01358 * @retval None 01359 */ 01360 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01361 { 01362 SET_BIT(RCC->APB2RSTR, Periphs); 01363 } 01364 01365 /** 01366 * @brief Release APB2 peripherals reset. 01367 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01368 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n 01369 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01370 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01371 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01372 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01373 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 01374 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 01375 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 01376 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01377 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01378 * APB2RSTR DFSDMRST LL_APB2_GRP1_ReleaseReset 01379 * @param Periphs This parameter can be a combination of the following values: 01380 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01381 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01382 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01383 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01384 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01385 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01386 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01387 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01388 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01389 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01390 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01391 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01392 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01393 * @retval None 01394 */ 01395 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01396 { 01397 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01398 } 01399 01400 /** 01401 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes 01402 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01403 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01404 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01405 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01406 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01407 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01408 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01409 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01410 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01411 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01412 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01413 * APB2SMENR DFSDMSMEN LL_APB2_GRP1_EnableClockStopSleep 01414 * @param Periphs This parameter can be a combination of the following values: 01415 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01416 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01417 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01418 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01420 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01421 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01422 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01423 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01424 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01425 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01426 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01427 * @retval None 01428 */ 01429 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 01430 { 01431 SET_BIT(RCC->APB2SMENR, Periphs); 01432 } 01433 01434 /** 01435 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes 01436 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01437 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01438 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01439 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01440 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01441 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01442 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01443 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01444 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01445 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01446 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01447 * APB2SMENR DFSDMSMEN LL_APB2_GRP1_DisableClockStopSleep 01448 * @param Periphs This parameter can be a combination of the following values: 01449 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01450 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 01451 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01452 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01453 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 01454 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01455 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01456 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01457 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 01458 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01459 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 01460 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM 01461 * @retval None 01462 */ 01463 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 01464 { 01465 CLEAR_BIT(RCC->APB2SMENR, Periphs); 01466 } 01467 01468 /** 01469 * @} 01470 */ 01471 01472 01473 /** 01474 * @} 01475 */ 01476 01477 /** 01478 * @} 01479 */ 01480 01481 #endif /* defined(RCC) */ 01482 01483 /** 01484 * @} 01485 */ 01486 01487 #ifdef __cplusplus 01488 } 01489 #endif 01490 01491 #endif /* __STM32L4xx_LL_BUS_H */ 01492 01493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01494
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