Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
Fork of STM32L4xx_HAL_Driver by
APB1
[BUS Exported Functions]
Functions | |
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs) |
Enable APB1 peripherals clock. | |
__STATIC_INLINE void | LL_APB1_GRP2_EnableClock (uint32_t Periphs) |
Enable APB1 peripherals clock. | |
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs) |
Check if APB1 peripheral clock is enabled or not APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock. | |
__STATIC_INLINE uint32_t | LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs) |
Check if APB1 peripheral clock is enabled or not APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock. | |
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs) |
Disable APB1 peripherals clock. | |
__STATIC_INLINE void | LL_APB1_GRP2_DisableClock (uint32_t Periphs) |
Disable APB1 peripherals clock. | |
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs) |
Force APB1 peripherals reset. | |
__STATIC_INLINE void | LL_APB1_GRP2_ForceReset (uint32_t Periphs) |
Force APB1 peripherals reset. | |
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs) |
Release APB1 peripherals reset. | |
__STATIC_INLINE void | LL_APB1_GRP2_ReleaseReset (uint32_t Periphs) |
Release APB1 peripherals reset. | |
__STATIC_INLINE void | LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs) |
Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep. | |
__STATIC_INLINE void | LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs) |
Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep. | |
__STATIC_INLINE void | LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs) |
Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep. | |
__STATIC_INLINE void | LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs) |
Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep. |
Function Documentation
__STATIC_INLINE void LL_APB1_GRP1_DisableClock | ( | uint32_t | Periphs ) |
Disable APB1 peripherals clock.
APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock
APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock
APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock
APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock
APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock
APB1ENR1 PWREN LL_APB1_GRP1_DisableClock
APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_WWDG
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 911 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep | ( | uint32_t | Periphs ) |
Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_WWDG
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 1195 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP1_EnableClock | ( | uint32_t | Periphs ) |
Enable APB1 peripherals clock.
APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock
APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock
APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock
APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock
APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock
APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock
APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock
APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock
APB1ENR1 PWREN LL_APB1_GRP1_EnableClock
APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_WWDG
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 769 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep | ( | uint32_t | Periphs ) |
Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep
APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_WWDG
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 1124 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP1_ForceReset | ( | uint32_t | Periphs ) |
Force APB1 peripherals reset.
APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset
APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset
APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset
APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_ALL
- LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 981 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock | ( | uint32_t | Periphs ) |
Check if APB1 peripheral clock is enabled or not APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock
APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_WWDG
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
uint32_t
Definition at line 840 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset | ( | uint32_t | Periphs ) |
Release APB1 peripherals reset.
APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset
APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP1_PERIPH_ALL
- LL_APB1_GRP1_PERIPH_TIM2
- LL_APB1_GRP1_PERIPH_TIM3
- LL_APB1_GRP1_PERIPH_TIM4
- LL_APB1_GRP1_PERIPH_TIM5
- LL_APB1_GRP1_PERIPH_TIM6
- LL_APB1_GRP1_PERIPH_TIM7
- LL_APB1_GRP1_PERIPH_LCD (*)
- LL_APB1_GRP1_PERIPH_SPI2
- LL_APB1_GRP1_PERIPH_SPI3
- LL_APB1_GRP1_PERIPH_USART2
- LL_APB1_GRP1_PERIPH_USART3
- LL_APB1_GRP1_PERIPH_UART4
- LL_APB1_GRP1_PERIPH_UART5
- LL_APB1_GRP1_PERIPH_I2C1
- LL_APB1_GRP1_PERIPH_I2C2
- LL_APB1_GRP1_PERIPH_I2C3
- LL_APB1_GRP1_PERIPH_CAN1
- LL_APB1_GRP1_PERIPH_PWR
- LL_APB1_GRP1_PERIPH_DAC1
- LL_APB1_GRP1_PERIPH_OPAMP
- LL_APB1_GRP1_PERIPH_LPTIM1 (*) value not defined in all devices.
- Return values:
-
None
Definition at line 1052 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_DisableClock | ( | uint32_t | Periphs ) |
Disable APB1 peripherals clock.
APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 927 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep | ( | uint32_t | Periphs ) |
Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 1211 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_EnableClock | ( | uint32_t | Periphs ) |
Enable APB1 peripherals clock.
APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 785 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep | ( | uint32_t | Periphs ) |
Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep
APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 1140 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_ForceReset | ( | uint32_t | Periphs ) |
Force APB1 peripherals reset.
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_ALL
- LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 998 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock | ( | uint32_t | Periphs ) |
Check if APB1 peripheral clock is enabled or not APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock
APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock.
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
uint32_t
Definition at line 856 of file stm32l4xx_ll_bus.h.
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset | ( | uint32_t | Periphs ) |
Release APB1 peripherals reset.
APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset
APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
- Parameters:
-
Periphs This parameter can be a combination of the following values: - LL_APB1_GRP2_PERIPH_ALL
- LL_APB1_GRP2_PERIPH_LPUART1
- LL_APB1_GRP2_PERIPH_SWPMI1
- LL_APB1_GRP2_PERIPH_LPTIM2
- Return values:
-
None
Definition at line 1069 of file stm32l4xx_ll_bus.h.
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