Andrew Schaeffer / Mbed 2 deprecated OU_Davis_Old_Robot

This is the project for the Old Model Robots for OU's Dr. Davis's Configurable Robots Research. This is being published so future robots can be set up easily.

Dependencies:   FatFileSystem MCP3008 Motor PinDetect QTR_8A SRF05 SSD1308_128x64_I2C mbed

PowerControl/EthernetPowerControl.cpp@0:bcad524c1856, 2017-11-01 (annotated)

Committer:
DrewSchaef
Date:
Wed Nov 01 15:57:59 2017 +0000
Revision:
0:bcad524c1856
Published the project to allow access for future work on the Configurable Robots Research Project(s).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DrewSchaef 0:bcad524c1856 1 #include "EthernetPowerControl.h"
DrewSchaef 0:bcad524c1856 2
DrewSchaef 0:bcad524c1856 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
DrewSchaef 0:bcad524c1856 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
DrewSchaef 0:bcad524c1856 5 unsigned int tout;
DrewSchaef 0:bcad524c1856 6 /* Hardware MII Management for LPC176x devices. */
DrewSchaef 0:bcad524c1856 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
DrewSchaef 0:bcad524c1856 8 LPC_EMAC->MWTD = Value;
DrewSchaef 0:bcad524c1856 9
DrewSchaef 0:bcad524c1856 10 /* Wait utill operation completed */
DrewSchaef 0:bcad524c1856 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
DrewSchaef 0:bcad524c1856 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
DrewSchaef 0:bcad524c1856 13 break;
DrewSchaef 0:bcad524c1856 14 }
DrewSchaef 0:bcad524c1856 15 }
DrewSchaef 0:bcad524c1856 16 }
DrewSchaef 0:bcad524c1856 17
DrewSchaef 0:bcad524c1856 18 static unsigned short read_PHY (unsigned int PhyReg) {
DrewSchaef 0:bcad524c1856 19 /* Read a PHY register 'PhyReg'. */
DrewSchaef 0:bcad524c1856 20 unsigned int tout, val;
DrewSchaef 0:bcad524c1856 21
DrewSchaef 0:bcad524c1856 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
DrewSchaef 0:bcad524c1856 23 LPC_EMAC->MCMD = MCMD_READ;
DrewSchaef 0:bcad524c1856 24
DrewSchaef 0:bcad524c1856 25 /* Wait until operation completed */
DrewSchaef 0:bcad524c1856 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
DrewSchaef 0:bcad524c1856 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
DrewSchaef 0:bcad524c1856 28 break;
DrewSchaef 0:bcad524c1856 29 }
DrewSchaef 0:bcad524c1856 30 }
DrewSchaef 0:bcad524c1856 31 LPC_EMAC->MCMD = 0;
DrewSchaef 0:bcad524c1856 32 val = LPC_EMAC->MRDD;
DrewSchaef 0:bcad524c1856 33
DrewSchaef 0:bcad524c1856 34 return (val);
DrewSchaef 0:bcad524c1856 35 }
DrewSchaef 0:bcad524c1856 36
DrewSchaef 0:bcad524c1856 37 void EMAC_Init()
DrewSchaef 0:bcad524c1856 38 {
DrewSchaef 0:bcad524c1856 39 unsigned int tout,regv;
DrewSchaef 0:bcad524c1856 40 /* Power Up the EMAC controller. */
DrewSchaef 0:bcad524c1856 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
DrewSchaef 0:bcad524c1856 42
DrewSchaef 0:bcad524c1856 43 LPC_PINCON->PINSEL2 = 0x50150105;
DrewSchaef 0:bcad524c1856 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
DrewSchaef 0:bcad524c1856 45 LPC_PINCON->PINSEL3 |= 0x00000005;
DrewSchaef 0:bcad524c1856 46
DrewSchaef 0:bcad524c1856 47 /* Reset all EMAC internal modules. */
DrewSchaef 0:bcad524c1856 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
DrewSchaef 0:bcad524c1856 49 MAC1_SIM_RES | MAC1_SOFT_RES;
DrewSchaef 0:bcad524c1856 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
DrewSchaef 0:bcad524c1856 51
DrewSchaef 0:bcad524c1856 52 /* A short delay after reset. */
DrewSchaef 0:bcad524c1856 53 for (tout = 100; tout; tout--);
DrewSchaef 0:bcad524c1856 54
DrewSchaef 0:bcad524c1856 55 /* Initialize MAC control registers. */
DrewSchaef 0:bcad524c1856 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
DrewSchaef 0:bcad524c1856 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
DrewSchaef 0:bcad524c1856 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
DrewSchaef 0:bcad524c1856 59 LPC_EMAC->CLRT = CLRT_DEF;
DrewSchaef 0:bcad524c1856 60 LPC_EMAC->IPGR = IPGR_DEF;
DrewSchaef 0:bcad524c1856 61
DrewSchaef 0:bcad524c1856 62 /* Enable Reduced MII interface. */
DrewSchaef 0:bcad524c1856 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
DrewSchaef 0:bcad524c1856 64
DrewSchaef 0:bcad524c1856 65 /* Reset Reduced MII Logic. */
DrewSchaef 0:bcad524c1856 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
DrewSchaef 0:bcad524c1856 67 for (tout = 100; tout; tout--);
DrewSchaef 0:bcad524c1856 68 LPC_EMAC->SUPP = 0;
DrewSchaef 0:bcad524c1856 69
DrewSchaef 0:bcad524c1856 70 /* Put the DP83848C in reset mode */
DrewSchaef 0:bcad524c1856 71 write_PHY (PHY_REG_BMCR, 0x8000);
DrewSchaef 0:bcad524c1856 72
DrewSchaef 0:bcad524c1856 73 /* Wait for hardware reset to end. */
DrewSchaef 0:bcad524c1856 74 for (tout = 0; tout < 0x100000; tout++) {
DrewSchaef 0:bcad524c1856 75 regv = read_PHY (PHY_REG_BMCR);
DrewSchaef 0:bcad524c1856 76 if (!(regv & 0x8000)) {
DrewSchaef 0:bcad524c1856 77 /* Reset complete */
DrewSchaef 0:bcad524c1856 78 break;
DrewSchaef 0:bcad524c1856 79 }
DrewSchaef 0:bcad524c1856 80 }
DrewSchaef 0:bcad524c1856 81 }
DrewSchaef 0:bcad524c1856 82
DrewSchaef 0:bcad524c1856 83
DrewSchaef 0:bcad524c1856 84 void PHY_PowerDown()
DrewSchaef 0:bcad524c1856 85 {
DrewSchaef 0:bcad524c1856 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
DrewSchaef 0:bcad524c1856 87 EMAC_Init(); //init EMAC if it is not already init'd
DrewSchaef 0:bcad524c1856 88
DrewSchaef 0:bcad524c1856 89 unsigned int regv;
DrewSchaef 0:bcad524c1856 90 regv = read_PHY(PHY_REG_BMCR);
DrewSchaef 0:bcad524c1856 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
DrewSchaef 0:bcad524c1856 92 regv = read_PHY(PHY_REG_BMCR);
DrewSchaef 0:bcad524c1856 93
DrewSchaef 0:bcad524c1856 94 //shouldn't need the EMAC now.
DrewSchaef 0:bcad524c1856 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
DrewSchaef 0:bcad524c1856 96
DrewSchaef 0:bcad524c1856 97 //and turn off the PHY OSC
DrewSchaef 0:bcad524c1856 98 LPC_GPIO1->FIODIR |= 0x8000000;
DrewSchaef 0:bcad524c1856 99 LPC_GPIO1->FIOCLR = 0x8000000;
DrewSchaef 0:bcad524c1856 100 }
DrewSchaef 0:bcad524c1856 101
DrewSchaef 0:bcad524c1856 102 void PHY_PowerUp()
DrewSchaef 0:bcad524c1856 103 {
DrewSchaef 0:bcad524c1856 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
DrewSchaef 0:bcad524c1856 105 EMAC_Init(); //init EMAC if it is not already init'd
DrewSchaef 0:bcad524c1856 106
DrewSchaef 0:bcad524c1856 107 LPC_GPIO1->FIODIR |= 0x8000000;
DrewSchaef 0:bcad524c1856 108 LPC_GPIO1->FIOSET = 0x8000000;
DrewSchaef 0:bcad524c1856 109
DrewSchaef 0:bcad524c1856 110 //wait for osc to be stable
DrewSchaef 0:bcad524c1856 111 wait_ms(200);
DrewSchaef 0:bcad524c1856 112
DrewSchaef 0:bcad524c1856 113 unsigned int regv;
DrewSchaef 0:bcad524c1856 114 regv = read_PHY(PHY_REG_BMCR);
DrewSchaef 0:bcad524c1856 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
DrewSchaef 0:bcad524c1856 116 regv = read_PHY(PHY_REG_BMCR);
DrewSchaef 0:bcad524c1856 117 }
DrewSchaef 0:bcad524c1856 118
DrewSchaef 0:bcad524c1856 119 void PHY_EnergyDetect_Enable()
DrewSchaef 0:bcad524c1856 120 {
DrewSchaef 0:bcad524c1856 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
DrewSchaef 0:bcad524c1856 122 EMAC_Init(); //init EMAC if it is not already init'd
DrewSchaef 0:bcad524c1856 123
DrewSchaef 0:bcad524c1856 124 unsigned int regv;
DrewSchaef 0:bcad524c1856 125 regv = read_PHY(PHY_REG_EDCR);
DrewSchaef 0:bcad524c1856 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
DrewSchaef 0:bcad524c1856 127 regv = read_PHY(PHY_REG_EDCR);
DrewSchaef 0:bcad524c1856 128 }
DrewSchaef 0:bcad524c1856 129
DrewSchaef 0:bcad524c1856 130 void PHY_EnergyDetect_Disable()
DrewSchaef 0:bcad524c1856 131 {
DrewSchaef 0:bcad524c1856 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
DrewSchaef 0:bcad524c1856 133 EMAC_Init(); //init EMAC if it is not already init'd
DrewSchaef 0:bcad524c1856 134 unsigned int regv;
DrewSchaef 0:bcad524c1856 135 regv = read_PHY(PHY_REG_EDCR);
DrewSchaef 0:bcad524c1856 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
DrewSchaef 0:bcad524c1856 137 regv = read_PHY(PHY_REG_EDCR);
DrewSchaef 0:bcad524c1856 138 }