John Karatka / mbed

mbed

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targets/TARGET_STM/stm_spi_api.c@180:b0033dcd6934, 2017-12-07 (annotated)

Committer:
AnnaBridge
Date:
Thu Dec 07 14:01:42 2017 +0000
Revision:
180:b0033dcd6934
Parent:
174:e131a1973e81
Child:
182:57724642e740
mbed-dev library. Release version 157

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2015, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "mbed_error.h"
AnnaBridge 180:b0033dcd6934 32 #include "mbed_debug.h"
<> 149:156823d33999 33 #include "spi_api.h"
<> 149:156823d33999 34
<> 149:156823d33999 35 #if DEVICE_SPI
<> 149:156823d33999 36 #include <stdbool.h>
<> 149:156823d33999 37 #include <math.h>
<> 149:156823d33999 38 #include <string.h>
<> 149:156823d33999 39 #include "cmsis.h"
<> 149:156823d33999 40 #include "pinmap.h"
<> 149:156823d33999 41 #include "PeripheralPins.h"
AnnaBridge 168:9672193075cf 42 #include "spi_device.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 149:156823d33999 46 #else
<> 149:156823d33999 47 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49
<> 149:156823d33999 50 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 51 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 149:156823d33999 52 #else
<> 149:156823d33999 53 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55
<> 149:156823d33999 56 #ifndef DEBUG_STDIO
<> 149:156823d33999 57 # define DEBUG_STDIO 0
<> 149:156823d33999 58 #endif
<> 149:156823d33999 59
<> 149:156823d33999 60 #if DEBUG_STDIO
<> 149:156823d33999 61 # include <stdio.h>
<> 149:156823d33999 62 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 149:156823d33999 63 #else
<> 149:156823d33999 64 # define DEBUG_PRINTF(...) {}
<> 149:156823d33999 65 #endif
<> 149:156823d33999 66
AnnaBridge 174:e131a1973e81 67 /* Consider 10ms as the default timeout for sending/receving 1 byte */
AnnaBridge 174:e131a1973e81 68 #define TIMEOUT_1_BYTE 10
AnnaBridge 174:e131a1973e81 69
<> 149:156823d33999 70 void init_spi(spi_t *obj)
<> 149:156823d33999 71 {
<> 149:156823d33999 72 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 73 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 74
<> 149:156823d33999 75 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 76
<> 149:156823d33999 77 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 149:156823d33999 78 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 149:156823d33999 79 error("Cannot initialize SPI");
<> 149:156823d33999 80 }
<> 149:156823d33999 81
AnnaBridge 174:e131a1973e81 82 /* In case of standard 4 wires SPI,PI can be kept enabled all time
AnnaBridge 174:e131a1973e81 83 * and SCK will only be generated during the write operations. But in case
AnnaBridge 174:e131a1973e81 84 * of 3 wires, it should be only enabled during rd/wr unitary operations,
AnnaBridge 174:e131a1973e81 85 * which is handled inside STM32 HAL layer.
AnnaBridge 174:e131a1973e81 86 */
AnnaBridge 174:e131a1973e81 87 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 174:e131a1973e81 88 __HAL_SPI_ENABLE(handle);
AnnaBridge 174:e131a1973e81 89 }
<> 149:156823d33999 90 }
<> 149:156823d33999 91
<> 149:156823d33999 92 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 93 {
<> 149:156823d33999 94 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 95 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 96
<> 149:156823d33999 97 // Determine the SPI to use
<> 149:156823d33999 98 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 99 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 100 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 101 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 102
<> 149:156823d33999 103 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 104 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 105
<> 149:156823d33999 106 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 107 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 149:156823d33999 108
<> 149:156823d33999 109 #if defined SPI1_BASE
<> 149:156823d33999 110 // Enable SPI clock
<> 149:156823d33999 111 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 112 __HAL_RCC_SPI1_CLK_ENABLE();
<> 149:156823d33999 113 spiobj->spiIRQ = SPI1_IRQn;
<> 149:156823d33999 114 }
<> 149:156823d33999 115 #endif
<> 149:156823d33999 116
<> 149:156823d33999 117 #if defined SPI2_BASE
<> 149:156823d33999 118 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 119 __HAL_RCC_SPI2_CLK_ENABLE();
<> 149:156823d33999 120 spiobj->spiIRQ = SPI2_IRQn;
<> 149:156823d33999 121 }
<> 149:156823d33999 122 #endif
<> 149:156823d33999 123
<> 149:156823d33999 124 #if defined SPI3_BASE
<> 149:156823d33999 125 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 126 __HAL_RCC_SPI3_CLK_ENABLE();
<> 149:156823d33999 127 spiobj->spiIRQ = SPI3_IRQn;
<> 149:156823d33999 128 }
<> 149:156823d33999 129 #endif
<> 149:156823d33999 130
<> 149:156823d33999 131 #if defined SPI4_BASE
<> 149:156823d33999 132 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 133 __HAL_RCC_SPI4_CLK_ENABLE();
<> 149:156823d33999 134 spiobj->spiIRQ = SPI4_IRQn;
<> 149:156823d33999 135 }
<> 149:156823d33999 136 #endif
<> 149:156823d33999 137
<> 149:156823d33999 138 #if defined SPI5_BASE
<> 149:156823d33999 139 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 140 __HAL_RCC_SPI5_CLK_ENABLE();
<> 149:156823d33999 141 spiobj->spiIRQ = SPI5_IRQn;
<> 149:156823d33999 142 }
<> 149:156823d33999 143 #endif
<> 149:156823d33999 144
<> 149:156823d33999 145 #if defined SPI6_BASE
<> 149:156823d33999 146 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 147 __HAL_RCC_SPI6_CLK_ENABLE();
<> 149:156823d33999 148 spiobj->spiIRQ = SPI6_IRQn;
<> 149:156823d33999 149 }
<> 149:156823d33999 150 #endif
<> 149:156823d33999 151
<> 149:156823d33999 152 // Configure the SPI pins
<> 149:156823d33999 153 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 154 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 155 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 156 spiobj->pin_miso = miso;
<> 149:156823d33999 157 spiobj->pin_mosi = mosi;
<> 149:156823d33999 158 spiobj->pin_sclk = sclk;
<> 149:156823d33999 159 spiobj->pin_ssel = ssel;
<> 149:156823d33999 160 if (ssel != NC) {
<> 149:156823d33999 161 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 162 } else {
<> 149:156823d33999 163 handle->Init.NSS = SPI_NSS_SOFT;
<> 149:156823d33999 164 }
<> 149:156823d33999 165
<> 149:156823d33999 166 /* Fill default value */
<> 149:156823d33999 167 handle->Instance = SPI_INST(obj);
<> 149:156823d33999 168 handle->Init.Mode = SPI_MODE_MASTER;
<> 149:156823d33999 169 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
AnnaBridge 174:e131a1973e81 170
AnnaBridge 174:e131a1973e81 171 if (miso != NC) {
AnnaBridge 174:e131a1973e81 172 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 174:e131a1973e81 173 } else {
AnnaBridge 174:e131a1973e81 174 handle->Init.Direction = SPI_DIRECTION_1LINE;
AnnaBridge 174:e131a1973e81 175 }
AnnaBridge 174:e131a1973e81 176
<> 149:156823d33999 177 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 178 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
AnnaBridge 165:e614a9f1c9e2 179 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 149:156823d33999 180 handle->Init.CRCPolynomial = 7;
<> 149:156823d33999 181 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 149:156823d33999 182 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
AnnaBridge 165:e614a9f1c9e2 183 handle->Init.TIMode = SPI_TIMODE_DISABLE;
<> 149:156823d33999 184
<> 149:156823d33999 185 init_spi(obj);
<> 149:156823d33999 186 }
<> 149:156823d33999 187
<> 149:156823d33999 188 void spi_free(spi_t *obj)
<> 149:156823d33999 189 {
<> 149:156823d33999 190 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 191 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 192
<> 149:156823d33999 193 DEBUG_PRINTF("spi_free\r\n");
<> 149:156823d33999 194
<> 149:156823d33999 195 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 196 HAL_SPI_DeInit(handle);
<> 149:156823d33999 197
<> 149:156823d33999 198 #if defined SPI1_BASE
<> 149:156823d33999 199 // Reset SPI and disable clock
<> 149:156823d33999 200 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 201 __HAL_RCC_SPI1_FORCE_RESET();
<> 149:156823d33999 202 __HAL_RCC_SPI1_RELEASE_RESET();
<> 149:156823d33999 203 __HAL_RCC_SPI1_CLK_DISABLE();
<> 149:156823d33999 204 }
<> 149:156823d33999 205 #endif
<> 149:156823d33999 206 #if defined SPI2_BASE
<> 149:156823d33999 207 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 208 __HAL_RCC_SPI2_FORCE_RESET();
<> 149:156823d33999 209 __HAL_RCC_SPI2_RELEASE_RESET();
<> 149:156823d33999 210 __HAL_RCC_SPI2_CLK_DISABLE();
<> 149:156823d33999 211 }
<> 149:156823d33999 212 #endif
<> 149:156823d33999 213
<> 149:156823d33999 214 #if defined SPI3_BASE
<> 149:156823d33999 215 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 216 __HAL_RCC_SPI3_FORCE_RESET();
<> 149:156823d33999 217 __HAL_RCC_SPI3_RELEASE_RESET();
<> 149:156823d33999 218 __HAL_RCC_SPI3_CLK_DISABLE();
<> 149:156823d33999 219 }
<> 149:156823d33999 220 #endif
<> 149:156823d33999 221
<> 149:156823d33999 222 #if defined SPI4_BASE
<> 149:156823d33999 223 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 224 __HAL_RCC_SPI4_FORCE_RESET();
<> 149:156823d33999 225 __HAL_RCC_SPI4_RELEASE_RESET();
<> 149:156823d33999 226 __HAL_RCC_SPI4_CLK_DISABLE();
<> 149:156823d33999 227 }
<> 149:156823d33999 228 #endif
<> 149:156823d33999 229
<> 149:156823d33999 230 #if defined SPI5_BASE
<> 149:156823d33999 231 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 232 __HAL_RCC_SPI5_FORCE_RESET();
<> 149:156823d33999 233 __HAL_RCC_SPI5_RELEASE_RESET();
<> 149:156823d33999 234 __HAL_RCC_SPI5_CLK_DISABLE();
<> 149:156823d33999 235 }
<> 149:156823d33999 236 #endif
<> 149:156823d33999 237
<> 149:156823d33999 238 #if defined SPI6_BASE
<> 149:156823d33999 239 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 240 __HAL_RCC_SPI6_FORCE_RESET();
<> 149:156823d33999 241 __HAL_RCC_SPI6_RELEASE_RESET();
<> 149:156823d33999 242 __HAL_RCC_SPI6_CLK_DISABLE();
<> 149:156823d33999 243 }
<> 149:156823d33999 244 #endif
<> 149:156823d33999 245
<> 149:156823d33999 246 // Configure GPIOs
<> 149:156823d33999 247 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 248 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 249 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 250 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 251 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 252 }
<> 149:156823d33999 253 }
<> 149:156823d33999 254
<> 149:156823d33999 255 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 256 {
<> 149:156823d33999 257 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 258 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 259
<> 149:156823d33999 260 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 149:156823d33999 261
<> 149:156823d33999 262 // Save new values
<> 149:156823d33999 263 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 149:156823d33999 264
<> 149:156823d33999 265 switch (mode) {
<> 149:156823d33999 266 case 0:
<> 149:156823d33999 267 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 268 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 269 break;
<> 149:156823d33999 270 case 1:
<> 149:156823d33999 271 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 272 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 273 break;
<> 149:156823d33999 274 case 2:
<> 149:156823d33999 275 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 276 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 277 break;
<> 149:156823d33999 278 default:
<> 149:156823d33999 279 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 280 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 281 break;
<> 149:156823d33999 282 }
<> 149:156823d33999 283
<> 149:156823d33999 284 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 285 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 286 }
<> 149:156823d33999 287
<> 149:156823d33999 288 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 149:156823d33999 289
AnnaBridge 180:b0033dcd6934 290 if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
AnnaBridge 180:b0033dcd6934 291 /* SPI slave implemtation in MBED does not support the 3 wires SPI.
AnnaBridge 180:b0033dcd6934 292 * (e.g. when MISO is not connected). So we're forcing slave in
AnnaBridge 180:b0033dcd6934 293 * 2LINES mode. As MISO is not connected, slave will only read
AnnaBridge 180:b0033dcd6934 294 * from master, and cannot write to it. Inform user.
AnnaBridge 180:b0033dcd6934 295 */
AnnaBridge 180:b0033dcd6934 296 debug("3 wires SPI slave not supported - slave will only read\r\n");
AnnaBridge 180:b0033dcd6934 297 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 180:b0033dcd6934 298 }
AnnaBridge 180:b0033dcd6934 299
<> 149:156823d33999 300 init_spi(obj);
<> 149:156823d33999 301 }
<> 149:156823d33999 302
<> 149:156823d33999 303 /*
<> 149:156823d33999 304 * Only the IP clock input is family dependant so it computed
<> 149:156823d33999 305 * separately in spi_get_clock_freq
<> 149:156823d33999 306 */
<> 149:156823d33999 307 extern int spi_get_clock_freq(spi_t *obj);
<> 149:156823d33999 308
<> 149:156823d33999 309 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
<> 149:156823d33999 310 SPI_BAUDRATEPRESCALER_4,
<> 149:156823d33999 311 SPI_BAUDRATEPRESCALER_8,
<> 149:156823d33999 312 SPI_BAUDRATEPRESCALER_16,
<> 149:156823d33999 313 SPI_BAUDRATEPRESCALER_32,
<> 149:156823d33999 314 SPI_BAUDRATEPRESCALER_64,
<> 149:156823d33999 315 SPI_BAUDRATEPRESCALER_128,
<> 149:156823d33999 316 SPI_BAUDRATEPRESCALER_256};
<> 149:156823d33999 317
<> 149:156823d33999 318 void spi_frequency(spi_t *obj, int hz) {
<> 149:156823d33999 319 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 320 int spi_hz = 0;
<> 149:156823d33999 321 uint8_t prescaler_rank = 0;
<> 159:612c381a210f 322 uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1;
<> 149:156823d33999 323 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 324
<> 159:612c381a210f 325 /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
<> 159:612c381a210f 326 spi_hz = spi_get_clock_freq(obj) / 2;
<> 149:156823d33999 327
<> 149:156823d33999 328 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 159:612c381a210f 329 while ((spi_hz > hz) && (prescaler_rank < last_index)) {
<> 149:156823d33999 330 spi_hz = spi_hz / 2;
<> 149:156823d33999 331 prescaler_rank++;
<> 149:156823d33999 332 }
<> 149:156823d33999 333
<> 159:612c381a210f 334 /* Use the best fit pre-scaler */
<> 159:612c381a210f 335 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
<> 159:612c381a210f 336
<> 159:612c381a210f 337 /* In case maximum pre-scaler still gives too high freq, raise an error */
<> 159:612c381a210f 338 if (spi_hz > hz) {
<> 160:d5399cc887bb 339 DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
<> 149:156823d33999 340 }
<> 149:156823d33999 341
<> 159:612c381a210f 342 DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
<> 159:612c381a210f 343
<> 149:156823d33999 344 init_spi(obj);
<> 149:156823d33999 345 }
<> 149:156823d33999 346
<> 149:156823d33999 347 static inline int ssp_readable(spi_t *obj)
<> 149:156823d33999 348 {
<> 149:156823d33999 349 int status;
<> 149:156823d33999 350 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 351 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 352
<> 149:156823d33999 353 // Check if data is received
<> 149:156823d33999 354 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 149:156823d33999 355 return status;
<> 149:156823d33999 356 }
<> 149:156823d33999 357
<> 149:156823d33999 358 static inline int ssp_writeable(spi_t *obj)
<> 149:156823d33999 359 {
<> 149:156823d33999 360 int status;
<> 149:156823d33999 361 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 362 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 363
<> 149:156823d33999 364 // Check if data is transmitted
<> 149:156823d33999 365 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 149:156823d33999 366 return status;
<> 149:156823d33999 367 }
<> 149:156823d33999 368
<> 149:156823d33999 369 static inline int ssp_busy(spi_t *obj)
<> 149:156823d33999 370 {
<> 149:156823d33999 371 int status;
<> 149:156823d33999 372 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 373 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 374 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
<> 149:156823d33999 375 return status;
<> 149:156823d33999 376 }
<> 149:156823d33999 377
<> 149:156823d33999 378 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 379 {
<> 149:156823d33999 380 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 381 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 382
AnnaBridge 174:e131a1973e81 383 if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
AnnaBridge 174:e131a1973e81 384 return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE);
AnnaBridge 174:e131a1973e81 385 }
AnnaBridge 174:e131a1973e81 386
AnnaBridge 168:9672193075cf 387 #if defined(LL_SPI_RX_FIFO_TH_HALF)
AnnaBridge 168:9672193075cf 388 /* Configure the default data size */
AnnaBridge 168:9672193075cf 389 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 390 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
AnnaBridge 168:9672193075cf 391 } else {
AnnaBridge 168:9672193075cf 392 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
AnnaBridge 168:9672193075cf 393 }
AnnaBridge 168:9672193075cf 394 #endif
<> 149:156823d33999 395
AnnaBridge 168:9672193075cf 396 /* Here we're using LL which means direct registers access
AnnaBridge 168:9672193075cf 397 * There is no error management, so we may end up looping
AnnaBridge 168:9672193075cf 398 * infinitely here in case of faulty device for insatnce,
AnnaBridge 168:9672193075cf 399 * but this will increase performances significantly
AnnaBridge 168:9672193075cf 400 */
<> 149:156823d33999 401
AnnaBridge 168:9672193075cf 402 /* Wait TXE flag to transmit data */
AnnaBridge 168:9672193075cf 403 while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
AnnaBridge 168:9672193075cf 404
AnnaBridge 168:9672193075cf 405 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 406 LL_SPI_TransmitData16(SPI_INST(obj), value);
<> 149:156823d33999 407 } else {
AnnaBridge 168:9672193075cf 408 LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
AnnaBridge 168:9672193075cf 409 }
AnnaBridge 168:9672193075cf 410
AnnaBridge 168:9672193075cf 411 /* Then wait RXE flag before reading */
AnnaBridge 168:9672193075cf 412 while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
AnnaBridge 168:9672193075cf 413
AnnaBridge 168:9672193075cf 414 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 415 return LL_SPI_ReceiveData16(SPI_INST(obj));
AnnaBridge 168:9672193075cf 416 } else {
AnnaBridge 168:9672193075cf 417 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 418 }
<> 149:156823d33999 419 }
<> 149:156823d33999 420
Kojto 171:19eb464bc2be 421 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 171:19eb464bc2be 422 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 167:e84263d55307 423 {
AnnaBridge 174:e131a1973e81 424 struct spi_s *spiobj = SPI_S(obj);
AnnaBridge 174:e131a1973e81 425 SPI_HandleTypeDef *handle = &(spiobj->handle);
AnnaBridge 167:e84263d55307 426 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 174:e131a1973e81 427 int i = 0;
AnnaBridge 174:e131a1973e81 428 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 174:e131a1973e81 429 for (i = 0; i < total; i++) {
AnnaBridge 174:e131a1973e81 430 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 174:e131a1973e81 431 char in = spi_master_write(obj, out);
AnnaBridge 174:e131a1973e81 432 if (i < rx_length) {
AnnaBridge 174:e131a1973e81 433 rx_buffer[i] = in;
AnnaBridge 174:e131a1973e81 434 }
AnnaBridge 174:e131a1973e81 435 }
AnnaBridge 174:e131a1973e81 436 } else {
AnnaBridge 174:e131a1973e81 437 /* In case of 1 WIRE only, first handle TX, then Rx */
AnnaBridge 174:e131a1973e81 438 if (tx_length != 0) {
AnnaBridge 174:e131a1973e81 439 if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) {
AnnaBridge 174:e131a1973e81 440 /* report an error */
AnnaBridge 174:e131a1973e81 441 total = 0;
AnnaBridge 174:e131a1973e81 442 }
AnnaBridge 174:e131a1973e81 443 }
AnnaBridge 174:e131a1973e81 444 if (rx_length != 0) {
AnnaBridge 174:e131a1973e81 445 if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) {
AnnaBridge 174:e131a1973e81 446 /* report an error */
AnnaBridge 174:e131a1973e81 447 total = 0;
AnnaBridge 174:e131a1973e81 448 }
AnnaBridge 167:e84263d55307 449 }
AnnaBridge 167:e84263d55307 450 }
AnnaBridge 167:e84263d55307 451
AnnaBridge 167:e84263d55307 452 return total;
AnnaBridge 167:e84263d55307 453 }
AnnaBridge 167:e84263d55307 454
<> 149:156823d33999 455 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 456 {
<> 149:156823d33999 457 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 149:156823d33999 458 };
<> 149:156823d33999 459
<> 149:156823d33999 460 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 461 {
<> 149:156823d33999 462 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 463 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 464 while (!ssp_readable(obj));
AnnaBridge 174:e131a1973e81 465 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 174:e131a1973e81 466 return LL_SPI_ReceiveData16(SPI_INST(obj));
<> 149:156823d33999 467 } else {
AnnaBridge 174:e131a1973e81 468 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 469 }
<> 149:156823d33999 470 }
<> 149:156823d33999 471
<> 149:156823d33999 472 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 473 {
<> 149:156823d33999 474 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 475 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 476 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 477 while (!ssp_writeable(obj));
<> 149:156823d33999 478 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 479 // Force 8-bit access to the data register
<> 149:156823d33999 480 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 481 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 482 *p_spi_dr = (uint8_t)value;
<> 149:156823d33999 483 } else { // SPI_DATASIZE_16BIT
<> 149:156823d33999 484 spi->DR = (uint16_t)value;
<> 149:156823d33999 485 }
<> 149:156823d33999 486 }
<> 149:156823d33999 487
<> 149:156823d33999 488 int spi_busy(spi_t *obj)
<> 149:156823d33999 489 {
<> 149:156823d33999 490 return ssp_busy(obj);
<> 149:156823d33999 491 }
<> 149:156823d33999 492
<> 149:156823d33999 493 #ifdef DEVICE_SPI_ASYNCH
<> 149:156823d33999 494 typedef enum {
<> 149:156823d33999 495 SPI_TRANSFER_TYPE_NONE = 0,
<> 149:156823d33999 496 SPI_TRANSFER_TYPE_TX = 1,
<> 149:156823d33999 497 SPI_TRANSFER_TYPE_RX = 2,
<> 149:156823d33999 498 SPI_TRANSFER_TYPE_TXRX = 3,
<> 149:156823d33999 499 } transfer_type_t;
<> 149:156823d33999 500
<> 149:156823d33999 501
<> 149:156823d33999 502 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 149:156823d33999 503 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 149:156823d33999 504 {
<> 149:156823d33999 505 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 506 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 507 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 508 // the HAL expects number of transfers instead of number of bytes
<> 149:156823d33999 509 // so for 16 bit transfer width the count needs to be halved
<> 149:156823d33999 510 size_t words;
<> 149:156823d33999 511
<> 149:156823d33999 512 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 149:156823d33999 513
<> 149:156823d33999 514 obj->spi.transfer_type = transfer_type;
<> 149:156823d33999 515
<> 149:156823d33999 516 if (is16bit) {
<> 149:156823d33999 517 words = length / 2;
<> 149:156823d33999 518 } else {
<> 149:156823d33999 519 words = length;
<> 149:156823d33999 520 }
<> 149:156823d33999 521
<> 149:156823d33999 522 // enable the interrupt
<> 149:156823d33999 523 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 524 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 525 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 526 NVIC_SetPriority(irq_n, 1);
<> 149:156823d33999 527 NVIC_EnableIRQ(irq_n);
<> 149:156823d33999 528
<> 149:156823d33999 529 // enable the right hal transfer
<> 149:156823d33999 530 int rc = 0;
<> 149:156823d33999 531 switch(transfer_type) {
<> 149:156823d33999 532 case SPI_TRANSFER_TYPE_TXRX:
<> 149:156823d33999 533 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
<> 149:156823d33999 534 break;
<> 149:156823d33999 535 case SPI_TRANSFER_TYPE_TX:
<> 149:156823d33999 536 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
<> 149:156823d33999 537 break;
<> 149:156823d33999 538 case SPI_TRANSFER_TYPE_RX:
<> 149:156823d33999 539 // the receive function also "transmits" the receive buffer so in order
<> 149:156823d33999 540 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 149:156823d33999 541 memset(rx, SPI_FILL_WORD, length);
<> 149:156823d33999 542 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
<> 149:156823d33999 543 break;
<> 149:156823d33999 544 default:
<> 149:156823d33999 545 length = 0;
<> 149:156823d33999 546 }
<> 149:156823d33999 547
<> 149:156823d33999 548 if (rc) {
<> 149:156823d33999 549 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 149:156823d33999 550 length = 0;
<> 149:156823d33999 551 }
<> 149:156823d33999 552
<> 149:156823d33999 553 return length;
<> 149:156823d33999 554 }
<> 149:156823d33999 555
<> 149:156823d33999 556 // asynchronous API
<> 149:156823d33999 557 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 558 {
<> 149:156823d33999 559 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 560 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 561
<> 149:156823d33999 562 // TODO: DMA usage is currently ignored
<> 149:156823d33999 563 (void) hint;
<> 149:156823d33999 564
<> 149:156823d33999 565 // check which use-case we have
<> 149:156823d33999 566 bool use_tx = (tx != NULL && tx_length > 0);
<> 149:156823d33999 567 bool use_rx = (rx != NULL && rx_length > 0);
<> 149:156823d33999 568 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 569
<> 149:156823d33999 570 // don't do anything, if the buffers aren't valid
<> 149:156823d33999 571 if (!use_tx && !use_rx)
<> 149:156823d33999 572 return;
<> 149:156823d33999 573
<> 149:156823d33999 574 // copy the buffers to the SPI object
<> 149:156823d33999 575 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 576 obj->tx_buff.length = tx_length;
<> 149:156823d33999 577 obj->tx_buff.pos = 0;
<> 149:156823d33999 578 obj->tx_buff.width = is16bit ? 16 : 8;
<> 149:156823d33999 579
<> 149:156823d33999 580 obj->rx_buff.buffer = rx;
<> 149:156823d33999 581 obj->rx_buff.length = rx_length;
<> 149:156823d33999 582 obj->rx_buff.pos = 0;
<> 149:156823d33999 583 obj->rx_buff.width = obj->tx_buff.width;
<> 149:156823d33999 584
<> 149:156823d33999 585 obj->spi.event = event;
<> 149:156823d33999 586
<> 149:156823d33999 587 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 149:156823d33999 588
<> 149:156823d33999 589 // register the thunking handler
<> 149:156823d33999 590 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 591 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 149:156823d33999 592
<> 149:156823d33999 593 // enable the right hal transfer
<> 149:156823d33999 594 if (use_tx && use_rx) {
<> 149:156823d33999 595 // we cannot manage different rx / tx sizes, let's use smaller one
<> 149:156823d33999 596 size_t size = (tx_length < rx_length)? tx_length : rx_length;
<> 149:156823d33999 597 if(tx_length != rx_length) {
<> 149:156823d33999 598 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 149:156823d33999 599 obj->tx_buff.length = size;
<> 149:156823d33999 600 obj->rx_buff.length = size;
<> 149:156823d33999 601 }
<> 149:156823d33999 602 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 149:156823d33999 603 } else if (use_tx) {
<> 149:156823d33999 604 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 149:156823d33999 605 } else if (use_rx) {
<> 149:156823d33999 606 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 149:156823d33999 607 }
<> 149:156823d33999 608 }
<> 149:156823d33999 609
<> 153:fa9ff456f731 610 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 611 {
<> 149:156823d33999 612 int event = 0;
<> 149:156823d33999 613
<> 149:156823d33999 614 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 615 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 149:156823d33999 616
<> 153:fa9ff456f731 617 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 149:156823d33999 618 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 619 int error = obj->spi.handle.ErrorCode;
<> 149:156823d33999 620 if(error != HAL_SPI_ERROR_NONE) {
<> 149:156823d33999 621 // something went wrong and the transfer has definitely completed
<> 149:156823d33999 622 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 623
<> 149:156823d33999 624 if (error & HAL_SPI_ERROR_OVR) {
<> 149:156823d33999 625 // buffer overrun
<> 149:156823d33999 626 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 627 }
<> 149:156823d33999 628 } else {
<> 149:156823d33999 629 // else we're done
<> 149:156823d33999 630 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 631 }
<> 153:fa9ff456f731 632 // enable the interrupt
<> 153:fa9ff456f731 633 NVIC_DisableIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 634 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 149:156823d33999 635 }
<> 149:156823d33999 636
<> 149:156823d33999 637
<> 149:156823d33999 638 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 149:156823d33999 639 }
<> 149:156823d33999 640
<> 149:156823d33999 641 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 642 {
<> 149:156823d33999 643 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 644 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 645 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 149:156823d33999 646
<> 149:156823d33999 647 switch(state) {
<> 149:156823d33999 648 case HAL_SPI_STATE_RESET:
<> 149:156823d33999 649 case HAL_SPI_STATE_READY:
<> 149:156823d33999 650 case HAL_SPI_STATE_ERROR:
<> 149:156823d33999 651 return 0;
<> 149:156823d33999 652 default:
<> 149:156823d33999 653 return 1;
<> 149:156823d33999 654 }
<> 149:156823d33999 655 }
<> 149:156823d33999 656
<> 149:156823d33999 657 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 658 {
<> 149:156823d33999 659 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 660 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 661
<> 149:156823d33999 662 // disable interrupt
<> 149:156823d33999 663 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 664 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 665 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 666
<> 149:156823d33999 667 // clean-up
<> 149:156823d33999 668 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 669 HAL_SPI_DeInit(handle);
<> 149:156823d33999 670 HAL_SPI_Init(handle);
<> 149:156823d33999 671 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 672 }
<> 149:156823d33999 673
<> 149:156823d33999 674 #endif //DEVICE_SPI_ASYNCH
<> 149:156823d33999 675
<> 149:156823d33999 676 #endif