Dieter Graef / DISCO_F746NG_USBDevice

partly working USB Device lib for STM32F746NG Discovery both Interface are working

Dependents:   DISCO-F746NG-USB_Device McLighTT project_Keyboard_to_the_Keyboard MIDIInstrumentPADProject ... more

USBDevice/USBRegs_STM32.h@0:0a2eaa300982, 2016-07-31 (annotated)

Committer:
DieterGraef
Date:
Sun Jul 31 17:47:35 2016 +0000
Revision:
0:0a2eaa300982
partly working USB Device library - serial and MIDI is working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DieterGraef 0:0a2eaa300982 1 /**
DieterGraef 0:0a2eaa300982 2 ******************************************************************************
DieterGraef 0:0a2eaa300982 3 * @file usb_regs.h
DieterGraef 0:0a2eaa300982 4 * @author MCD Application Team
DieterGraef 0:0a2eaa300982 5 * @version V2.1.0
DieterGraef 0:0a2eaa300982 6 * @date 19-March-2012
DieterGraef 0:0a2eaa300982 7 * @brief hardware registers
DieterGraef 0:0a2eaa300982 8 ******************************************************************************
DieterGraef 0:0a2eaa300982 9 * @attention
DieterGraef 0:0a2eaa300982 10 *
DieterGraef 0:0a2eaa300982 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
DieterGraef 0:0a2eaa300982 12 *
DieterGraef 0:0a2eaa300982 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
DieterGraef 0:0a2eaa300982 14 * You may not use this file except in compliance with the License.
DieterGraef 0:0a2eaa300982 15 * You may obtain a copy of the License at:
DieterGraef 0:0a2eaa300982 16 *
DieterGraef 0:0a2eaa300982 17 * http://www.st.com/software_license_agreement_liberty_v2
DieterGraef 0:0a2eaa300982 18 *
DieterGraef 0:0a2eaa300982 19 * Unless required by applicable law or agreed to in writing, software
DieterGraef 0:0a2eaa300982 20 * distributed under the License is distributed on an "AS IS" BASIS,
DieterGraef 0:0a2eaa300982 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
DieterGraef 0:0a2eaa300982 22 * See the License for the specific language governing permissions and
DieterGraef 0:0a2eaa300982 23 * limitations under the License.
DieterGraef 0:0a2eaa300982 24 *
DieterGraef 0:0a2eaa300982 25 ******************************************************************************
DieterGraef 0:0a2eaa300982 26 */
DieterGraef 0:0a2eaa300982 27
DieterGraef 0:0a2eaa300982 28 #ifndef __USB_OTG_REGS_H__
DieterGraef 0:0a2eaa300982 29 #define __USB_OTG_REGS_H__
DieterGraef 0:0a2eaa300982 30
DieterGraef 0:0a2eaa300982 31 typedef struct //000h
DieterGraef 0:0a2eaa300982 32 {
DieterGraef 0:0a2eaa300982 33 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
DieterGraef 0:0a2eaa300982 34 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
DieterGraef 0:0a2eaa300982 35 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
DieterGraef 0:0a2eaa300982 36 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
DieterGraef 0:0a2eaa300982 37 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
DieterGraef 0:0a2eaa300982 38 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
DieterGraef 0:0a2eaa300982 39 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
DieterGraef 0:0a2eaa300982 40 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
DieterGraef 0:0a2eaa300982 41 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
DieterGraef 0:0a2eaa300982 42 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
DieterGraef 0:0a2eaa300982 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
DieterGraef 0:0a2eaa300982 44 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
DieterGraef 0:0a2eaa300982 45 uint32_t Reserved30[2]; /*!< Reserved 030h */
DieterGraef 0:0a2eaa300982 46 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
DieterGraef 0:0a2eaa300982 47 __IO uint32_t CID; /*!< User ID Register 03Ch */
DieterGraef 0:0a2eaa300982 48 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
DieterGraef 0:0a2eaa300982 49 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
DieterGraef 0:0a2eaa300982 50 uint32_t Reserved6; /*!< Reserved 050h */
DieterGraef 0:0a2eaa300982 51 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
DieterGraef 0:0a2eaa300982 52 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
DieterGraef 0:0a2eaa300982 53 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
DieterGraef 0:0a2eaa300982 54 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
DieterGraef 0:0a2eaa300982 55 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
DieterGraef 0:0a2eaa300982 56 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
DieterGraef 0:0a2eaa300982 57 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
DieterGraef 0:0a2eaa300982 58 }
DieterGraef 0:0a2eaa300982 59 USB_OTG_GREGS;
DieterGraef 0:0a2eaa300982 60
DieterGraef 0:0a2eaa300982 61 typedef struct // 800h
DieterGraef 0:0a2eaa300982 62 {
DieterGraef 0:0a2eaa300982 63 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
DieterGraef 0:0a2eaa300982 64 __IO uint32_t DCTL; /*!< dev Control Register 804h */
DieterGraef 0:0a2eaa300982 65 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
DieterGraef 0:0a2eaa300982 66 uint32_t Reserved0C; /*!< Reserved 80Ch */
DieterGraef 0:0a2eaa300982 67 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
DieterGraef 0:0a2eaa300982 68 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
DieterGraef 0:0a2eaa300982 69 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
DieterGraef 0:0a2eaa300982 70 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
DieterGraef 0:0a2eaa300982 71 uint32_t Reserved20; /*!< Reserved 820h */
DieterGraef 0:0a2eaa300982 72 uint32_t Reserved9; /*!< Reserved 824h */
DieterGraef 0:0a2eaa300982 73 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
DieterGraef 0:0a2eaa300982 74 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
DieterGraef 0:0a2eaa300982 75 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
DieterGraef 0:0a2eaa300982 76 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
DieterGraef 0:0a2eaa300982 77 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
DieterGraef 0:0a2eaa300982 78 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
DieterGraef 0:0a2eaa300982 79 uint32_t Reserved40; /*!< dedicated EP mask 840h */
DieterGraef 0:0a2eaa300982 80 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
DieterGraef 0:0a2eaa300982 81 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
DieterGraef 0:0a2eaa300982 82 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
DieterGraef 0:0a2eaa300982 83 }
DieterGraef 0:0a2eaa300982 84 USB_OTG_DREGS;
DieterGraef 0:0a2eaa300982 85
DieterGraef 0:0a2eaa300982 86 typedef struct
DieterGraef 0:0a2eaa300982 87 {
DieterGraef 0:0a2eaa300982 88 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
DieterGraef 0:0a2eaa300982 89 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
DieterGraef 0:0a2eaa300982 90 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
DieterGraef 0:0a2eaa300982 91 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
DieterGraef 0:0a2eaa300982 92 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
DieterGraef 0:0a2eaa300982 93 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
DieterGraef 0:0a2eaa300982 94 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
DieterGraef 0:0a2eaa300982 95 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
DieterGraef 0:0a2eaa300982 96 }
DieterGraef 0:0a2eaa300982 97 USB_OTG_INEPREGS;
DieterGraef 0:0a2eaa300982 98
DieterGraef 0:0a2eaa300982 99 typedef struct
DieterGraef 0:0a2eaa300982 100 {
DieterGraef 0:0a2eaa300982 101 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
DieterGraef 0:0a2eaa300982 102 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
DieterGraef 0:0a2eaa300982 103 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
DieterGraef 0:0a2eaa300982 104 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
DieterGraef 0:0a2eaa300982 105 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
DieterGraef 0:0a2eaa300982 106 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
DieterGraef 0:0a2eaa300982 107 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
DieterGraef 0:0a2eaa300982 108 }
DieterGraef 0:0a2eaa300982 109 USB_OTG_OUTEPREGS;
DieterGraef 0:0a2eaa300982 110
DieterGraef 0:0a2eaa300982 111 typedef struct
DieterGraef 0:0a2eaa300982 112 {
DieterGraef 0:0a2eaa300982 113 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
DieterGraef 0:0a2eaa300982 114 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
DieterGraef 0:0a2eaa300982 115 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
DieterGraef 0:0a2eaa300982 116 uint32_t Reserved40C; /*!< Reserved 40Ch */
DieterGraef 0:0a2eaa300982 117 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
DieterGraef 0:0a2eaa300982 118 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
DieterGraef 0:0a2eaa300982 119 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
DieterGraef 0:0a2eaa300982 120 }
DieterGraef 0:0a2eaa300982 121 USB_OTG_HREGS;
DieterGraef 0:0a2eaa300982 122
DieterGraef 0:0a2eaa300982 123 typedef struct
DieterGraef 0:0a2eaa300982 124 {
DieterGraef 0:0a2eaa300982 125 __IO uint32_t HCCHAR;
DieterGraef 0:0a2eaa300982 126 __IO uint32_t HCSPLT;
DieterGraef 0:0a2eaa300982 127 __IO uint32_t HCINT;
DieterGraef 0:0a2eaa300982 128 __IO uint32_t HCINTMSK;
DieterGraef 0:0a2eaa300982 129 __IO uint32_t HCTSIZ;
DieterGraef 0:0a2eaa300982 130 uint32_t Reserved[3];
DieterGraef 0:0a2eaa300982 131 }
DieterGraef 0:0a2eaa300982 132 USB_OTG_HC_REGS;
DieterGraef 0:0a2eaa300982 133
DieterGraef 0:0a2eaa300982 134 typedef struct
DieterGraef 0:0a2eaa300982 135 {
DieterGraef 0:0a2eaa300982 136 USB_OTG_GREGS GREGS;
DieterGraef 0:0a2eaa300982 137 uint32_t RESERVED0[176 ];
DieterGraef 0:0a2eaa300982 138 USB_OTG_HREGS HREGS;
DieterGraef 0:0a2eaa300982 139 uint32_t RESERVED1[9];
DieterGraef 0:0a2eaa300982 140 __IO uint32_t HPRT;
DieterGraef 0:0a2eaa300982 141 uint32_t RESERVED2[47];
DieterGraef 0:0a2eaa300982 142 USB_OTG_HC_REGS HC_REGS[8];
DieterGraef 0:0a2eaa300982 143 uint32_t RESERVED3[128];
DieterGraef 0:0a2eaa300982 144 USB_OTG_DREGS DREGS;
DieterGraef 0:0a2eaa300982 145 uint32_t RESERVED4[30];
DieterGraef 0:0a2eaa300982 146 USB_OTG_INEPREGS INEP_REGS[4];
DieterGraef 0:0a2eaa300982 147 uint32_t RESERVED5[96];
DieterGraef 0:0a2eaa300982 148 USB_OTG_OUTEPREGS OUTEP_REGS[4];
DieterGraef 0:0a2eaa300982 149 uint32_t RESERVED6[160];
DieterGraef 0:0a2eaa300982 150 __IO uint32_t PCGCCTL;
DieterGraef 0:0a2eaa300982 151 uint32_t RESERVED7[127];
DieterGraef 0:0a2eaa300982 152 __IO uint32_t FIFO[4][1024];
DieterGraef 0:0a2eaa300982 153 }
DieterGraef 0:0a2eaa300982 154 USB_OTG_CORE_REGS;
DieterGraef 0:0a2eaa300982 155
DieterGraef 0:0a2eaa300982 156
DieterGraef 0:0a2eaa300982 157 #define OTG_FS_BASE USB_OTG_FS_PERIPH_BASE
DieterGraef 0:0a2eaa300982 158 #define OTG_HS_BASE USB_OTG_HS_PERIPH_BASE
DieterGraef 0:0a2eaa300982 159 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
DieterGraef 0:0a2eaa300982 160 #define OTG_HS ((USB_OTG_CORE_REGS *) OTG_HS_BASE)
DieterGraef 0:0a2eaa300982 161
DieterGraef 0:0a2eaa300982 162 #endif //__USB_OTG_REGS_H__
DieterGraef 0:0a2eaa300982 163
DieterGraef 0:0a2eaa300982 164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DieterGraef 0:0a2eaa300982 165