Deepti AST / Envt_Shield_F4_API

Environmental Shield API

BSP/Components/uvis3/uvis3.h@0:9e645e6ed2ce, 2014-08-19 (annotated)

Committer:
Deepti
Date:
Tue Aug 19 07:13:15 2014 +0000
Revision:
0:9e645e6ed2ce
Environment Shield API

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Deepti 0:9e645e6ed2ce 1 /**
Deepti 0:9e645e6ed2ce 2 ******************************************************************************
Deepti 0:9e645e6ed2ce 3 * @file uvis3.h
Deepti 0:9e645e6ed2ce 4 * @author AST Robotics Team
Deepti 0:9e645e6ed2ce 5 * @version V0.0.1
Deepti 0:9e645e6ed2ce 6 * @date 18-February-2014
Deepti 0:9e645e6ed2ce 7 * @brief This file contains definitions uvis3.c
Deepti 0:9e645e6ed2ce 8 * firmware driver.
Deepti 0:9e645e6ed2ce 9 ******************************************************************************
Deepti 0:9e645e6ed2ce 10 * @attention
Deepti 0:9e645e6ed2ce 11 *
Deepti 0:9e645e6ed2ce 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Deepti 0:9e645e6ed2ce 13 *
Deepti 0:9e645e6ed2ce 14 * Redistribution and use in source and binary forms, with or without modification,
Deepti 0:9e645e6ed2ce 15 * are permitted provided that the following conditions are met:
Deepti 0:9e645e6ed2ce 16 * 1. Redistributions of source code must retain the above copyright notice,
Deepti 0:9e645e6ed2ce 17 * this list of conditions and the following disclaimer.
Deepti 0:9e645e6ed2ce 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Deepti 0:9e645e6ed2ce 19 * this list of conditions and the following disclaimer in the documentation
Deepti 0:9e645e6ed2ce 20 * and/or other materials provided with the distribution.
Deepti 0:9e645e6ed2ce 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Deepti 0:9e645e6ed2ce 22 * may be used to endorse or promote products derived from this software
Deepti 0:9e645e6ed2ce 23 * without specific prior written permission.
Deepti 0:9e645e6ed2ce 24 *
Deepti 0:9e645e6ed2ce 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Deepti 0:9e645e6ed2ce 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Deepti 0:9e645e6ed2ce 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Deepti 0:9e645e6ed2ce 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Deepti 0:9e645e6ed2ce 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Deepti 0:9e645e6ed2ce 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Deepti 0:9e645e6ed2ce 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Deepti 0:9e645e6ed2ce 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Deepti 0:9e645e6ed2ce 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Deepti 0:9e645e6ed2ce 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Deepti 0:9e645e6ed2ce 35 *
Deepti 0:9e645e6ed2ce 36 ******************************************************************************
Deepti 0:9e645e6ed2ce 37 */
Deepti 0:9e645e6ed2ce 38
Deepti 0:9e645e6ed2ce 39
Deepti 0:9e645e6ed2ce 40 /* Define to prevent recursive inclusion -------------------------------------*/
Deepti 0:9e645e6ed2ce 41 #ifndef __UVIS3_H
Deepti 0:9e645e6ed2ce 42 #define __UVIS3_H
Deepti 0:9e645e6ed2ce 43
Deepti 0:9e645e6ed2ce 44 #ifdef __cplusplus
Deepti 0:9e645e6ed2ce 45 extern "C" {
Deepti 0:9e645e6ed2ce 46 #endif
Deepti 0:9e645e6ed2ce 47
Deepti 0:9e645e6ed2ce 48 /* Includes ------------------------------------------------------------------*/
Deepti 0:9e645e6ed2ce 49 #include "../Common/uv.h"
Deepti 0:9e645e6ed2ce 50
Deepti 0:9e645e6ed2ce 51 /** @addtogroup BSP
Deepti 0:9e645e6ed2ce 52 * @{
Deepti 0:9e645e6ed2ce 53 */
Deepti 0:9e645e6ed2ce 54
Deepti 0:9e645e6ed2ce 55 /** @addtogroup UVIS3
Deepti 0:9e645e6ed2ce 56 * @{
Deepti 0:9e645e6ed2ce 57 */
Deepti 0:9e645e6ed2ce 58
Deepti 0:9e645e6ed2ce 59 /** @defgroup UVIS3_Exported_Constants
Deepti 0:9e645e6ed2ce 60 * @{
Deepti 0:9e645e6ed2ce 61 */
Deepti 0:9e645e6ed2ce 62
Deepti 0:9e645e6ed2ce 63 /******************************************************************************/
Deepti 0:9e645e6ed2ce 64 /*************************** START REGISTER MAPPING **************************/
Deepti 0:9e645e6ed2ce 65 /******************************************************************************/
Deepti 0:9e645e6ed2ce 66 /**
Deepti 0:9e645e6ed2ce 67 * @brief Device Address
Deepti 0:9e645e6ed2ce 68 */
Deepti 0:9e645e6ed2ce 69 #define UVIS3_ADDRESS 0x8E
Deepti 0:9e645e6ed2ce 70
Deepti 0:9e645e6ed2ce 71
Deepti 0:9e645e6ed2ce 72 /**
Deepti 0:9e645e6ed2ce 73 * @brief Device identifier register.
Deepti 0:9e645e6ed2ce 74 * \code
Deepti 0:9e645e6ed2ce 75 * Read
Deepti 0:9e645e6ed2ce 76 * Default value: 0xBD
Deepti 0:9e645e6ed2ce 77 * 7:0 This read-only register contains the device identifier that,
Deepti 0:9e645e6ed2ce 78 for UVIS3, is set to 0xCA.
Deepti 0:9e645e6ed2ce 79 * \endcode
Deepti 0:9e645e6ed2ce 80 */
Deepti 0:9e645e6ed2ce 81 #define UVIS3_WHO_AM_I_ADDR 0x0F
Deepti 0:9e645e6ed2ce 82
Deepti 0:9e645e6ed2ce 83
Deepti 0:9e645e6ed2ce 84 /**
Deepti 0:9e645e6ed2ce 85 * @brief UVIS3 control register 1
Deepti 0:9e645e6ed2ce 86 * \code
Deepti 0:9e645e6ed2ce 87 * Read/write
Deepti 0:9e645e6ed2ce 88 * Default value: 0x80.
Deepti 0:9e645e6ed2ce 89 * 7 PD: power down control. 1 - disable; 0 - enable.
Deepti 0:9e645e6ed2ce 90 * 6:2 reserved.
Deepti 0:9e645e6ed2ce 91 * 1 BDU: Block Data Update. 0 - continuous update; 1 -output registers not
Deepti 0:9e645e6ed2ce 92 updated until MSB and LSB reading. //CHECK
Deepti 0:9e645e6ed2ce 93 * 0 ODR: Output Data Rate. 0 - ODR disabled (one shot mode); 1 ODR at 1 Hz.
Deepti 0:9e645e6ed2ce 94 * \endcode
Deepti 0:9e645e6ed2ce 95 */
Deepti 0:9e645e6ed2ce 96 #define UVIS3_CTRL_REG1_ADDR 0x20
Deepti 0:9e645e6ed2ce 97
Deepti 0:9e645e6ed2ce 98
Deepti 0:9e645e6ed2ce 99 /**
Deepti 0:9e645e6ed2ce 100 * @brief UVIS3 control register 2
Deepti 0:9e645e6ed2ce 101 * \code
Deepti 0:9e645e6ed2ce 102 * Read/write
Deepti 0:9e645e6ed2ce 103 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 104 * 7 BOOT: reboot memory content. 1 - reload flash content; 0 - normal mode.
Deepti 0:9e645e6ed2ce 105 * 6:5 reserved.
Deepti 0:9e645e6ed2ce 106 * 4: I2C_DIS: Disable I2C interface. 0: enable; 1: disable.
Deepti 0:9e645e6ed2ce 107 * 3 SIM: SPI Serial Interface Mode Selection. 0: 4 wires interface;
Deepti 0:9e645e6ed2ce 108 1: 3 wires interface.
Deepti 0:9e645e6ed2ce 109 * 2:1 Reserved
Deepti 0:9e645e6ed2ce 110 * 0: One shot enable. 0: waiting for start of conversion;
Deepti 0:9e645e6ed2ce 111 1: start for a new dataset.
Deepti 0:9e645e6ed2ce 112 * \endcode
Deepti 0:9e645e6ed2ce 113 */
Deepti 0:9e645e6ed2ce 114 #define UVIS3_CTRL_REG2_ADDR 0x21
Deepti 0:9e645e6ed2ce 115
Deepti 0:9e645e6ed2ce 116
Deepti 0:9e645e6ed2ce 117 /**
Deepti 0:9e645e6ed2ce 118 * @brief UVIS3 control register 3
Deepti 0:9e645e6ed2ce 119 * \code
Deepti 0:9e645e6ed2ce 120 * Read/write
Deepti 0:9e645e6ed2ce 121 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 122 * 7 INT_H_L: Interrupt active high, low. 0: active high; 1: active low.
Deepti 0:9e645e6ed2ce 123 * 6 PP_OD: Push-pull/open drain selection on interrupt pads. 0: push-pull;
Deepti 0:9e645e6ed2ce 124 1: open drain.
Deepti 0:9e645e6ed2ce 125 * 5:2 Reserved
Deepti 0:9e645e6ed2ce 126 * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits.
Deepti 0:9e645e6ed2ce 127 Default value: 00.
Deepti 0:9e645e6ed2ce 128 * | INT1_S2 | INT1_S1 | INT1 pin |
Deepti 0:9e645e6ed2ce 129 * -------------------------------------------------
Deepti 0:9e645e6ed2ce 130 * | 0 | 0 | Data ready |
Deepti 0:9e645e6ed2ce 131 * | 0 | 1 | UV index High |
Deepti 0:9e645e6ed2ce 132 * | 1 | 0 | UV index Low |
Deepti 0:9e645e6ed2ce 133 * | 1 | 1 | UV index High or Low |
Deepti 0:9e645e6ed2ce 134 * \endcode
Deepti 0:9e645e6ed2ce 135 */
Deepti 0:9e645e6ed2ce 136 #define UVIS3_CTRL_REG3_ADDR 0x22
Deepti 0:9e645e6ed2ce 137
Deepti 0:9e645e6ed2ce 138
Deepti 0:9e645e6ed2ce 139 /**
Deepti 0:9e645e6ed2ce 140 * @brief INT1 interrupt configuration
Deepti 0:9e645e6ed2ce 141 * \code
Deepti 0:9e645e6ed2ce 142 * Read/write
Deepti 0:9e645e6ed2ce 143 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 144 * 7:4 Reserved.
Deepti 0:9e645e6ed2ce 145 * 3: DIFF_EN: interrupt logical block enable. 0: interrupt logick block
Deepti 0:9e645e6ed2ce 146 disable; 1: enable.
Deepti 0:9e645e6ed2ce 147 * 2: LIR: Latch interrupt request into INT_SOURCE register with (24h), with
Deepti 0:9e645e6ed2ce 148 the INT_SOURCE register cleared by reading INT_SOURCE reg (24h).
Deepti 0:9e645e6ed2ce 149 0: interrupt request not latched;1: latched.
Deepti 0:9e645e6ed2ce 150 * 1: UVLE: Enable interrupt generation on differential UV low event. 0: disable
Deepti 0:9e645e6ed2ce 151 interrupt request;1: enable interrupt request
Deepti 0:9e645e6ed2ce 152 * 0: UVHE: Enable interrupt generation on differential UV high event SIM;
Deepti 0:9e645e6ed2ce 153 0: disable interrupt request;1: enable interrupt request
Deepti 0:9e645e6ed2ce 154 * \endcode
Deepti 0:9e645e6ed2ce 155 */
Deepti 0:9e645e6ed2ce 156 #define UVIS3_INT_CFG_ADDR 0x23
Deepti 0:9e645e6ed2ce 157
Deepti 0:9e645e6ed2ce 158
Deepti 0:9e645e6ed2ce 159
Deepti 0:9e645e6ed2ce 160 /**
Deepti 0:9e645e6ed2ce 161 * @brief Interrupt source configuration register
Deepti 0:9e645e6ed2ce 162 * \code
Deepti 0:9e645e6ed2ce 163 * Read/write
Deepti 0:9e645e6ed2ce 164 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 165 * 7:3 Reserved.
Deepti 0:9e645e6ed2ce 166 * 2: IA: Interrupt Active. 0: no interrupt has been generated;
Deepti 0:9e645e6ed2ce 167 1: one or more interrupt events have been generated.
Deepti 0:9e645e6ed2ce 168 * 1: UVL: Differential UV low. 0: no interrupt; 1: UVL event has occurred.
Deepti 0:9e645e6ed2ce 169 * 0: UVH: Differential UV high. 0: no interrupt; 1: UVH event has occurred.
Deepti 0:9e645e6ed2ce 170 * \endcode
Deepti 0:9e645e6ed2ce 171 */
Deepti 0:9e645e6ed2ce 172 #define UVIS3_INT_SRC_ADDR 0x24
Deepti 0:9e645e6ed2ce 173
Deepti 0:9e645e6ed2ce 174
Deepti 0:9e645e6ed2ce 175
Deepti 0:9e645e6ed2ce 176 /**
Deepti 0:9e645e6ed2ce 177 * @brief Differential UV interrupt threshold
Deepti 0:9e645e6ed2ce 178 * \code
Deepti 0:9e645e6ed2ce 179 * Read/write
Deepti 0:9e645e6ed2ce 180 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 181 * 7:0 Differential UV Interrupt Threshold values.
Deepti 0:9e645e6ed2ce 182 * \endcode
Deepti 0:9e645e6ed2ce 183 */
Deepti 0:9e645e6ed2ce 184 #define UVIS3_DIFF_UV_TSH_ADDR 0x25
Deepti 0:9e645e6ed2ce 185
Deepti 0:9e645e6ed2ce 186
Deepti 0:9e645e6ed2ce 187 /**
Deepti 0:9e645e6ed2ce 188 * @brief Status register
Deepti 0:9e645e6ed2ce 189 * \code
Deepti 0:9e645e6ed2ce 190 * Read/write
Deepti 0:9e645e6ed2ce 191 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 192 * 7:1 Reserved.
Deepti 0:9e645e6ed2ce 193 * 0: UV_DA: UV data available. 0: UV data index not available; 1: UV data
Deepti 0:9e645e6ed2ce 194 index available.
Deepti 0:9e645e6ed2ce 195 * \endcode
Deepti 0:9e645e6ed2ce 196 */
Deepti 0:9e645e6ed2ce 197 #define UVIS3_STATUS_REG_ADDR 0x27
Deepti 0:9e645e6ed2ce 198
Deepti 0:9e645e6ed2ce 199
Deepti 0:9e645e6ed2ce 200 /**
Deepti 0:9e645e6ed2ce 201 * @brief UV index data
Deepti 0:9e645e6ed2ce 202 * \code
Deepti 0:9e645e6ed2ce 203 * Read/write
Deepti 0:9e645e6ed2ce 204 * Default value: 0x00.
Deepti 0:9e645e6ed2ce 205 * 7:0 UV index data output values.
Deepti 0:9e645e6ed2ce 206 * \endcode
Deepti 0:9e645e6ed2ce 207 */
Deepti 0:9e645e6ed2ce 208 #define UVIS3_UVDATA_OUT_ADDR 0x28
Deepti 0:9e645e6ed2ce 209
Deepti 0:9e645e6ed2ce 210
Deepti 0:9e645e6ed2ce 211 /******************************************************************************/
Deepti 0:9e645e6ed2ce 212 /**************************** END REGISTER MAPPING ***************************/
Deepti 0:9e645e6ed2ce 213 /******************************************************************************/
Deepti 0:9e645e6ed2ce 214
Deepti 0:9e645e6ed2ce 215 /**
Deepti 0:9e645e6ed2ce 216 * @brief Device Identifier. Default value of the WHO_AM_I register.
Deepti 0:9e645e6ed2ce 217 */
Deepti 0:9e645e6ed2ce 218 #define I_AM_UVIS3 ((uint8_t)0xCA)
Deepti 0:9e645e6ed2ce 219
Deepti 0:9e645e6ed2ce 220 /** @defgroup Power_Mode_selection CTRL_REG1
Deepti 0:9e645e6ed2ce 221 * @{
Deepti 0:9e645e6ed2ce 222 */
Deepti 0:9e645e6ed2ce 223 #define UVIS3_MODE_ACTIVE ((uint8_t)0x00)
Deepti 0:9e645e6ed2ce 224 #define UVIS3_MODE_POWERDOWN ((uint8_t)0x80)
Deepti 0:9e645e6ed2ce 225
Deepti 0:9e645e6ed2ce 226 #define UVIS3_MODE_MASK ((uint8_t)0x80)
Deepti 0:9e645e6ed2ce 227
Deepti 0:9e645e6ed2ce 228 /**
Deepti 0:9e645e6ed2ce 229 * @}
Deepti 0:9e645e6ed2ce 230 */
Deepti 0:9e645e6ed2ce 231
Deepti 0:9e645e6ed2ce 232 /** @defgroup OutPut_DataRate_Selection CTRL_REG1
Deepti 0:9e645e6ed2ce 233 * @{
Deepti 0:9e645e6ed2ce 234 */
Deepti 0:9e645e6ed2ce 235 #define UVIS3_ODR_ONE_SHOT ((uint8_t)0x00)
Deepti 0:9e645e6ed2ce 236 #define UVIS3_ODR_1HZ ((uint8_t)0x01)
Deepti 0:9e645e6ed2ce 237
Deepti 0:9e645e6ed2ce 238 #define UVIS3_ODR_MASK ((uint8_t)0x01)
Deepti 0:9e645e6ed2ce 239
Deepti 0:9e645e6ed2ce 240 /**
Deepti 0:9e645e6ed2ce 241 * @}
Deepti 0:9e645e6ed2ce 242 */
Deepti 0:9e645e6ed2ce 243
Deepti 0:9e645e6ed2ce 244 /** @defgroup Boot_Mode_selection CTRL_REG2
Deepti 0:9e645e6ed2ce 245 * @{
Deepti 0:9e645e6ed2ce 246 */
Deepti 0:9e645e6ed2ce 247 #define UVIS3_BOOT_NORMALMODE ((uint8_t)0x00)
Deepti 0:9e645e6ed2ce 248 #define UVIS3_BOOT_REBOOTMEMORY ((uint8_t)0x80)
Deepti 0:9e645e6ed2ce 249
Deepti 0:9e645e6ed2ce 250 #define UVIS3_BOOT_MASK ((uint8_t)0x80)
Deepti 0:9e645e6ed2ce 251
Deepti 0:9e645e6ed2ce 252 /**
Deepti 0:9e645e6ed2ce 253 * @}
Deepti 0:9e645e6ed2ce 254 */
Deepti 0:9e645e6ed2ce 255
Deepti 0:9e645e6ed2ce 256
Deepti 0:9e645e6ed2ce 257 /** @defgroup UVIS3_Exported_Functions
Deepti 0:9e645e6ed2ce 258 * @{
Deepti 0:9e645e6ed2ce 259 */
Deepti 0:9e645e6ed2ce 260 /* Sensor Configuration Functions */
Deepti 0:9e645e6ed2ce 261 void UVIS3_Init(UV_InitTypeDef *UVIS3_Init);
Deepti 0:9e645e6ed2ce 262 uint8_t UVIS3_ReadID(void);
Deepti 0:9e645e6ed2ce 263 void UVIS3_RebootCmd(void);
Deepti 0:9e645e6ed2ce 264 void UVIS3_GetIndex(float* pfData);
Deepti 0:9e645e6ed2ce 265
Deepti 0:9e645e6ed2ce 266 /* Interrupt Configuration Functions */
Deepti 0:9e645e6ed2ce 267 void UVIS3_INT1InterruptConfig(uint16_t Int1Config);
Deepti 0:9e645e6ed2ce 268 void UVIS3_EnableIT(void);
Deepti 0:9e645e6ed2ce 269 void UVIS3_DisableIT(void);
Deepti 0:9e645e6ed2ce 270
Deepti 0:9e645e6ed2ce 271 /* Uv sensor driver structure */
Deepti 0:9e645e6ed2ce 272 extern UV_DrvTypeDef Uvis3Drv;
Deepti 0:9e645e6ed2ce 273
Deepti 0:9e645e6ed2ce 274 /* Uv sensor IO functions */
Deepti 0:9e645e6ed2ce 275 void UV_IO_Init(void);
Deepti 0:9e645e6ed2ce 276 void UV_IO_DeInit(void);
Deepti 0:9e645e6ed2ce 277 void UV_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t WriteAddr, uint16_t NumByteToWrite);
Deepti 0:9e645e6ed2ce 278 void UV_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, uint16_t NumByteToRead);
Deepti 0:9e645e6ed2ce 279
Deepti 0:9e645e6ed2ce 280 /**
Deepti 0:9e645e6ed2ce 281 * @}
Deepti 0:9e645e6ed2ce 282 */
Deepti 0:9e645e6ed2ce 283
Deepti 0:9e645e6ed2ce 284 /**
Deepti 0:9e645e6ed2ce 285 * @}
Deepti 0:9e645e6ed2ce 286 */
Deepti 0:9e645e6ed2ce 287
Deepti 0:9e645e6ed2ce 288 /**
Deepti 0:9e645e6ed2ce 289 * @}
Deepti 0:9e645e6ed2ce 290 */
Deepti 0:9e645e6ed2ce 291
Deepti 0:9e645e6ed2ce 292 #ifdef __cplusplus
Deepti 0:9e645e6ed2ce 293 }
Deepti 0:9e645e6ed2ce 294 #endif
Deepti 0:9e645e6ed2ce 295
Deepti 0:9e645e6ed2ce 296 #endif /* __UVIS3_H */
Deepti 0:9e645e6ed2ce 297
Deepti 0:9e645e6ed2ce 298
Deepti 0:9e645e6ed2ce 299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Deepti 0:9e645e6ed2ce 300