R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information
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TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct
- Committer:
- jamesadevine
- Date:
- 2016-04-07
- Revision:
- 1:a7c51b5e0534
- Child:
- 2:e32c8485c88f
File content as of revision 1:a7c51b5e0534:
;WITHOUT SOFTDEVICE: ;LR_IROM1 0x00000000 0x00040000 { ; ER_IROM1 0x00000000 0x00040000 { ; *.o (RESET, +First) ; *(InRoot$$Sections) ; .ANY (+RO) ; } ; RW_IRAM1 0x20000000 0x00004000 { ; .ANY (+RW +ZI) ; } ;} ; ;WITH SOFTDEVICE: LR_IROM1 0x18000 0x0028000 { ER_IROM1 0x18000 0x0028000 { *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } RW_IRAM1 0x20002000 0x00002000 { .ANY (+RW +ZI) } }