David Saul / mbed-dev-bin

R1 code for micro:bit based train controller code, requires second micro:bit running rx code to operate - see https://meanderingpi.wordpress.com/ for more information

Fork of mbed-dev-bin by Lancaster University

TARGET_NRF51_MICROBIT/TOOLCHAIN_ARM_STD/nRF51822.sct@1:a7c51b5e0534, 2016-04-07 (annotated)

Committer:
jamesadevine
Date:
Thu Apr 07 17:50:29 2016 +0000
Revision:
1:a7c51b5e0534
Child:
2:e32c8485c88f
Added correct nrf51.h ; Added scatter file.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jamesadevine 1:a7c51b5e0534 1 ;WITHOUT SOFTDEVICE:
jamesadevine 1:a7c51b5e0534 2 ;LR_IROM1 0x00000000 0x00040000 {
jamesadevine 1:a7c51b5e0534 3 ; ER_IROM1 0x00000000 0x00040000 {
jamesadevine 1:a7c51b5e0534 4 ; *.o (RESET, +First)
jamesadevine 1:a7c51b5e0534 5 ; *(InRoot$$Sections)
jamesadevine 1:a7c51b5e0534 6 ; .ANY (+RO)
jamesadevine 1:a7c51b5e0534 7 ; }
jamesadevine 1:a7c51b5e0534 8 ; RW_IRAM1 0x20000000 0x00004000 {
jamesadevine 1:a7c51b5e0534 9 ; .ANY (+RW +ZI)
jamesadevine 1:a7c51b5e0534 10 ; }
jamesadevine 1:a7c51b5e0534 11 ;}
jamesadevine 1:a7c51b5e0534 12 ;
jamesadevine 1:a7c51b5e0534 13 ;WITH SOFTDEVICE:
jamesadevine 1:a7c51b5e0534 14
jamesadevine 1:a7c51b5e0534 15 LR_IROM1 0x18000 0x0028000 {
jamesadevine 1:a7c51b5e0534 16 ER_IROM1 0x18000 0x0028000 {
jamesadevine 1:a7c51b5e0534 17 *.o (RESET, +First)
jamesadevine 1:a7c51b5e0534 18 *(InRoot$$Sections)
jamesadevine 1:a7c51b5e0534 19 .ANY (+RO)
jamesadevine 1:a7c51b5e0534 20 }
jamesadevine 1:a7c51b5e0534 21 RW_IRAM1 0x20002000 0x00002000 {
jamesadevine 1:a7c51b5e0534 22 .ANY (+RW +ZI)
jamesadevine 1:a7c51b5e0534 23 }
jamesadevine 1:a7c51b5e0534 24 }
jamesadevine 1:a7c51b5e0534 25
jamesadevine 1:a7c51b5e0534 26