Daniel Lee / BSP_DISCO_F413ZH

Patched for Audio example - Add status check when DFSDM's filter and channel de-init.

Dependents:   DISCO_F413ZH-AUDIO-demo

The base repository is https://os.mbed.com/teams/ST/code/BSP_DISCO_F413ZH/. I've just added workaround patch for Audio-in demo on DISCO_F413ZH board(Microphone U16, U17)

Drivers/BSP/STM32F413H-Discovery/stm32f413h_discovery_qspi.c@4:c051317d4051, 2020-01-31 (annotated)

Committer:
Daniel_Lee
Date:
Fri Jan 31 07:17:05 2020 +0000
Revision:
4:c051317d4051
Parent:
3:42b354f5069c 
Patched for Audio example;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
arostm 0:4af3ca173992 1 /**
arostm 0:4af3ca173992 2 ******************************************************************************
arostm 0:4af3ca173992 3 * @file stm32f413h_discovery_qspi.c
arostm 0:4af3ca173992 4 * @author MCD Application Team
arostm 0:4af3ca173992 5 * @brief This file includes a standard driver for the N25Q128A QSPI
arostm 0:4af3ca173992 6 * memory mounted on STM32F413H-DISCOVERY board.
arostm 0:4af3ca173992 7 @verbatim
arostm 0:4af3ca173992 8 ==============================================================================
arostm 0:4af3ca173992 9 ##### How to use this driver #####
arostm 0:4af3ca173992 10 ==============================================================================
arostm 0:4af3ca173992 11 [..]
arostm 0:4af3ca173992 12 (#) This driver is used to drive the N25Q128A QSPI external
arostm 0:4af3ca173992 13 memory mounted on STM32F413H-DISCOVERY board.
arostm 0:4af3ca173992 14
arostm 0:4af3ca173992 15 (#) This driver need a specific component driver (N25Q128A) to be included with.
arostm 0:4af3ca173992 16
arostm 0:4af3ca173992 17 (#) Initialization steps:
arostm 0:4af3ca173992 18 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
arostm 0:4af3ca173992 19 function includes the MSP layer hardware resources initialization and the
arostm 0:4af3ca173992 20 QSPI interface with the external memory.
arostm 0:4af3ca173992 21
arostm 0:4af3ca173992 22 (#) QSPI memory operations
arostm 0:4af3ca173992 23 (++) QSPI memory can be accessed with read/write operations once it is
arostm 0:4af3ca173992 24 initialized.
arostm 0:4af3ca173992 25 Read/write operation can be performed with AHB access using the functions
arostm 0:4af3ca173992 26 BSP_QSPI_Read()/BSP_QSPI_Write().
arostm 0:4af3ca173992 27 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
arostm 0:4af3ca173992 28 (see the QSPI memory data sheet)
arostm 0:4af3ca173992 29 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
arostm 0:4af3ca173992 30 specifying the block address. You can perform an erase operation of the whole
arostm 0:4af3ca173992 31 chip by calling the function BSP_QSPI_Erase_Chip().
arostm 0:4af3ca173992 32 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
arostm 0:4af3ca173992 33 (see the QSPI memory data sheet)
arostm 0:4af3ca173992 34 @endverbatim
arostm 0:4af3ca173992 35 ******************************************************************************
arostm 0:4af3ca173992 36 * @attention
arostm 0:4af3ca173992 37 *
arostm 0:4af3ca173992 38 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
arostm 0:4af3ca173992 39 *
arostm 0:4af3ca173992 40 * Redistribution and use in source and binary forms, with or without modification,
arostm 0:4af3ca173992 41 * are permitted provided that the following conditions are met:
arostm 0:4af3ca173992 42 * 1. Redistributions of source code must retain the above copyright notice,
arostm 0:4af3ca173992 43 * this list of conditions and the following disclaimer.
arostm 0:4af3ca173992 44 * 2. Redistributions in binary form must reproduce the above copyright notice,
arostm 0:4af3ca173992 45 * this list of conditions and the following disclaimer in the documentation
arostm 0:4af3ca173992 46 * and/or other materials provided with the distribution.
arostm 0:4af3ca173992 47 * 3. Neither the name of STMicroelectronics nor the names of its contributors
arostm 0:4af3ca173992 48 * may be used to endorse or promote products derived from this software
arostm 0:4af3ca173992 49 * without specific prior written permission.
arostm 0:4af3ca173992 50 *
arostm 0:4af3ca173992 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
arostm 0:4af3ca173992 52 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
arostm 0:4af3ca173992 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
arostm 0:4af3ca173992 54 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
arostm 0:4af3ca173992 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
arostm 0:4af3ca173992 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
arostm 0:4af3ca173992 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
arostm 0:4af3ca173992 58 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
arostm 0:4af3ca173992 59 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
arostm 0:4af3ca173992 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
arostm 0:4af3ca173992 61 *
arostm 0:4af3ca173992 62 ******************************************************************************
arostm 0:4af3ca173992 63 */
arostm 0:4af3ca173992 64
arostm 0:4af3ca173992 65 /* Includes ------------------------------------------------------------------*/
arostm 0:4af3ca173992 66 #include "stm32f413h_discovery_qspi.h"
arostm 0:4af3ca173992 67
arostm 0:4af3ca173992 68 /** @addtogroup BSP
arostm 0:4af3ca173992 69 * @{
arostm 0:4af3ca173992 70 */
arostm 0:4af3ca173992 71
arostm 0:4af3ca173992 72 /** @addtogroup STM32F413H_DISCOVERY
arostm 0:4af3ca173992 73 * @{
arostm 0:4af3ca173992 74 */
arostm 0:4af3ca173992 75
arostm 0:4af3ca173992 76 /** @defgroup STM32F413H_DISCOVERY_QSPI STM32F413H_DISCOVERY QSPI
arostm 0:4af3ca173992 77 * @{
arostm 0:4af3ca173992 78 */
arostm 0:4af3ca173992 79
arostm 0:4af3ca173992 80
arostm 0:4af3ca173992 81 /* Private variables ---------------------------------------------------------*/
arostm 0:4af3ca173992 82
arostm 0:4af3ca173992 83 /** @defgroup STM32F413H_DISCOVERY_QSPI_Private_Variables STM32F413H DISCOVERY Private Variables
arostm 0:4af3ca173992 84 * @{
arostm 0:4af3ca173992 85 */
arostm 0:4af3ca173992 86 QSPI_HandleTypeDef QSPIHandle;
arostm 0:4af3ca173992 87
arostm 0:4af3ca173992 88 /**
arostm 0:4af3ca173992 89 * @}
arostm 0:4af3ca173992 90 */
arostm 0:4af3ca173992 91
arostm 0:4af3ca173992 92 /* Private functions ---------------------------------------------------------*/
arostm 0:4af3ca173992 93
arostm 0:4af3ca173992 94 /** @defgroup STM32F413H_DISCOVERY_QSPI_Private_FunctionsPrototypes STM32F413H DISCOVERY Private Functions Prototypes
arostm 0:4af3ca173992 95 * @{
arostm 0:4af3ca173992 96 */
arostm 0:4af3ca173992 97 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
arostm 0:4af3ca173992 98 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
arostm 0:4af3ca173992 99 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
arostm 0:4af3ca173992 100 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
arostm 0:4af3ca173992 101
arostm 0:4af3ca173992 102 /**
arostm 0:4af3ca173992 103 * @}
arostm 0:4af3ca173992 104 */
arostm 0:4af3ca173992 105
arostm 0:4af3ca173992 106 /** @defgroup STM32F413H_DISCOVERY_QSPI_Exported_Functions STM32F413H DISCOVERY Exported Functions
arostm 0:4af3ca173992 107 * @{
arostm 0:4af3ca173992 108 */
arostm 0:4af3ca173992 109
arostm 0:4af3ca173992 110 /**
arostm 0:4af3ca173992 111 * @brief Initializes the QSPI interface.
arostm 0:4af3ca173992 112 * @retval QSPI memory status
arostm 0:4af3ca173992 113 */
arostm 0:4af3ca173992 114 uint8_t BSP_QSPI_Init(void)
arostm 0:4af3ca173992 115 {
arostm 0:4af3ca173992 116 QSPIHandle.Instance = QUADSPI;
arostm 0:4af3ca173992 117
arostm 0:4af3ca173992 118 /* Call the DeInit function to reset the driver */
arostm 0:4af3ca173992 119 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
arostm 0:4af3ca173992 120 {
arostm 0:4af3ca173992 121 return QSPI_ERROR;
arostm 0:4af3ca173992 122 }
arostm 0:4af3ca173992 123
arostm 0:4af3ca173992 124 /* System level initialization */
arostm 0:4af3ca173992 125 BSP_QSPI_MspInit(&QSPIHandle, NULL);
arostm 0:4af3ca173992 126
arostm 0:4af3ca173992 127 /* QSPI initialization */
arostm 0:4af3ca173992 128 QSPIHandle.Init.ClockPrescaler = 0; /* QSPI freq = 100 MHz/(0+1) = 100 Mhz */
arostm 0:4af3ca173992 129 QSPIHandle.Init.FifoThreshold = 4;
arostm 0:4af3ca173992 130 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
arostm 0:4af3ca173992 131 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
arostm 0:4af3ca173992 132 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE; /* Min 50ns for nonRead commands */
arostm 0:4af3ca173992 133 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
arostm 0:4af3ca173992 134 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
arostm 0:4af3ca173992 135 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
arostm 0:4af3ca173992 136
arostm 0:4af3ca173992 137 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
arostm 0:4af3ca173992 138 {
arostm 0:4af3ca173992 139 return QSPI_ERROR;
arostm 0:4af3ca173992 140 }
arostm 0:4af3ca173992 141
arostm 0:4af3ca173992 142 /* QSPI memory reset */
arostm 0:4af3ca173992 143 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
arostm 0:4af3ca173992 144 {
arostm 0:4af3ca173992 145 return QSPI_NOT_SUPPORTED;
arostm 0:4af3ca173992 146 }
arostm 0:4af3ca173992 147
arostm 0:4af3ca173992 148 /* Configuration of the dummy cycles on QSPI memory side */
arostm 0:4af3ca173992 149 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
arostm 0:4af3ca173992 150 {
arostm 0:4af3ca173992 151 return QSPI_NOT_SUPPORTED;
arostm 0:4af3ca173992 152 }
arostm 0:4af3ca173992 153
arostm 0:4af3ca173992 154 return QSPI_OK;
arostm 0:4af3ca173992 155 }
arostm 0:4af3ca173992 156
arostm 0:4af3ca173992 157 /**
arostm 0:4af3ca173992 158 * @brief De-Initializes the QSPI interface.
arostm 0:4af3ca173992 159 * @retval QSPI memory status
arostm 0:4af3ca173992 160 */
arostm 0:4af3ca173992 161 uint8_t BSP_QSPI_DeInit(void)
arostm 0:4af3ca173992 162 {
arostm 0:4af3ca173992 163 QSPIHandle.Instance = QUADSPI;
arostm 0:4af3ca173992 164
arostm 0:4af3ca173992 165 /* Call the DeInit function to reset the driver */
arostm 0:4af3ca173992 166 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
arostm 0:4af3ca173992 167 {
arostm 0:4af3ca173992 168 return QSPI_ERROR;
arostm 0:4af3ca173992 169 }
arostm 0:4af3ca173992 170
arostm 0:4af3ca173992 171 /* System level De-initialization */
arostm 0:4af3ca173992 172 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
arostm 0:4af3ca173992 173
arostm 0:4af3ca173992 174 return QSPI_OK;
arostm 0:4af3ca173992 175 }
arostm 0:4af3ca173992 176
arostm 0:4af3ca173992 177 /**
arostm 0:4af3ca173992 178 * @brief Reads an amount of data from the QSPI memory.
arostm 0:4af3ca173992 179 * @param pData: Pointer to data to be read
arostm 0:4af3ca173992 180 * @param ReadAddr: Read start address
arostm 0:4af3ca173992 181 * @param Size: Size of data to read
arostm 0:4af3ca173992 182 * @retval QSPI memory status
arostm 0:4af3ca173992 183 */
arostm 0:4af3ca173992 184 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
arostm 0:4af3ca173992 185 {
arostm 0:4af3ca173992 186 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 187
arostm 0:4af3ca173992 188 /* Initialize the read command */
arostm 0:4af3ca173992 189 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 190 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
arostm 0:4af3ca173992 191 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
arostm 0:4af3ca173992 192 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
arostm 0:4af3ca173992 193 s_command.Address = ReadAddr;
arostm 0:4af3ca173992 194 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 195 s_command.DataMode = QSPI_DATA_4_LINES;
arostm 0:4af3ca173992 196 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
arostm 0:4af3ca173992 197 s_command.NbData = Size;
arostm 0:4af3ca173992 198 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 199 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 200 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 201
arostm 0:4af3ca173992 202 /* Configure the command */
arostm 0:4af3ca173992 203 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 204 {
arostm 0:4af3ca173992 205 return QSPI_ERROR;
arostm 0:4af3ca173992 206 }
arostm 0:4af3ca173992 207
arostm 0:4af3ca173992 208 /* Set S# timing for Read command: Min 20ns for N25Q128A memory */
arostm 0:4af3ca173992 209 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_2_CYCLE);
arostm 0:4af3ca173992 210
arostm 0:4af3ca173992 211 /* Reception of the data */
arostm 0:4af3ca173992 212 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 213 {
arostm 0:4af3ca173992 214 return QSPI_ERROR;
arostm 0:4af3ca173992 215 }
arostm 0:4af3ca173992 216
arostm 0:4af3ca173992 217 /* Restore S# timing for nonRead commands */
arostm 0:4af3ca173992 218 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_5_CYCLE);
arostm 0:4af3ca173992 219
arostm 0:4af3ca173992 220 return QSPI_OK;
arostm 0:4af3ca173992 221 }
arostm 0:4af3ca173992 222
arostm 0:4af3ca173992 223 /**
arostm 0:4af3ca173992 224 * @brief Writes an amount of data to the QSPI memory.
arostm 0:4af3ca173992 225 * @param pData: Pointer to data to be written
arostm 0:4af3ca173992 226 * @param WriteAddr: Write start address
arostm 0:4af3ca173992 227 * @param Size: Size of data to write
arostm 0:4af3ca173992 228 * @retval QSPI memory status
arostm 0:4af3ca173992 229 */
arostm 0:4af3ca173992 230 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
arostm 0:4af3ca173992 231 {
arostm 0:4af3ca173992 232 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 233 uint32_t end_addr, current_size, current_addr;
arostm 0:4af3ca173992 234
arostm 0:4af3ca173992 235 /* Calculation of the size between the write address and the end of the page */
arostm 0:4af3ca173992 236 current_size = N25Q128A_PAGE_SIZE - (WriteAddr % N25Q128A_PAGE_SIZE);
arostm 0:4af3ca173992 237
arostm 0:4af3ca173992 238 /* Check if the size of the data is less than the remaining place in the page */
arostm 0:4af3ca173992 239 if (current_size > Size)
arostm 0:4af3ca173992 240 {
arostm 0:4af3ca173992 241 current_size = Size;
arostm 0:4af3ca173992 242 }
arostm 0:4af3ca173992 243
arostm 0:4af3ca173992 244 /* Initialize the adress variables */
arostm 0:4af3ca173992 245 current_addr = WriteAddr;
arostm 0:4af3ca173992 246 end_addr = WriteAddr + Size;
arostm 0:4af3ca173992 247
arostm 0:4af3ca173992 248 /* Initialize the program command */
arostm 0:4af3ca173992 249 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 250 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
arostm 0:4af3ca173992 251 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
arostm 0:4af3ca173992 252 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
arostm 0:4af3ca173992 253 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 254 s_command.DataMode = QSPI_DATA_4_LINES;
arostm 0:4af3ca173992 255 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 256 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 257 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 258 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 259
arostm 0:4af3ca173992 260 /* Perform the write page by page */
arostm 0:4af3ca173992 261 do
arostm 0:4af3ca173992 262 {
arostm 0:4af3ca173992 263 s_command.Address = current_addr;
arostm 0:4af3ca173992 264 s_command.NbData = current_size;
arostm 0:4af3ca173992 265
arostm 0:4af3ca173992 266 /* Enable write operations */
arostm 0:4af3ca173992 267 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
arostm 0:4af3ca173992 268 {
arostm 0:4af3ca173992 269 return QSPI_ERROR;
arostm 0:4af3ca173992 270 }
arostm 0:4af3ca173992 271
arostm 0:4af3ca173992 272 /* Configure the command */
arostm 0:4af3ca173992 273 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 274 {
arostm 0:4af3ca173992 275 return QSPI_ERROR;
arostm 0:4af3ca173992 276 }
arostm 0:4af3ca173992 277
arostm 0:4af3ca173992 278 /* Transmission of the data */
arostm 0:4af3ca173992 279 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 280 {
arostm 0:4af3ca173992 281 return QSPI_ERROR;
arostm 0:4af3ca173992 282 }
arostm 0:4af3ca173992 283
arostm 0:4af3ca173992 284 /* Configure automatic polling mode to wait for end of program */
arostm 0:4af3ca173992 285 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
arostm 0:4af3ca173992 286 {
arostm 0:4af3ca173992 287 return QSPI_ERROR;
arostm 0:4af3ca173992 288 }
arostm 0:4af3ca173992 289
arostm 0:4af3ca173992 290 /* Update the address and size variables for next page programming */
arostm 0:4af3ca173992 291 current_addr += current_size;
arostm 0:4af3ca173992 292 pData += current_size;
arostm 0:4af3ca173992 293 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
arostm 0:4af3ca173992 294 } while (current_addr < end_addr);
arostm 0:4af3ca173992 295
arostm 0:4af3ca173992 296 return QSPI_OK;
arostm 0:4af3ca173992 297 }
arostm 0:4af3ca173992 298
arostm 0:4af3ca173992 299 /**
arostm 0:4af3ca173992 300 * @brief Erases the specified block of the QSPI memory.
arostm 0:4af3ca173992 301 * @param BlockAddress: Block address to erase
arostm 0:4af3ca173992 302 * @retval QSPI memory status
arostm 0:4af3ca173992 303 */
arostm 0:4af3ca173992 304 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
arostm 0:4af3ca173992 305 {
arostm 0:4af3ca173992 306 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 307
arostm 0:4af3ca173992 308 /* Initialize the erase command */
arostm 0:4af3ca173992 309 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 310 s_command.Instruction = SUBSECTOR_ERASE_CMD;
arostm 0:4af3ca173992 311 s_command.AddressMode = QSPI_ADDRESS_1_LINE;
arostm 0:4af3ca173992 312 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
arostm 0:4af3ca173992 313 s_command.Address = BlockAddress;
arostm 0:4af3ca173992 314 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 315 s_command.DataMode = QSPI_DATA_NONE;
arostm 0:4af3ca173992 316 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 317 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 318 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 319 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 320
arostm 0:4af3ca173992 321 /* Enable write operations */
arostm 0:4af3ca173992 322 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
arostm 0:4af3ca173992 323 {
arostm 0:4af3ca173992 324 return QSPI_ERROR;
arostm 0:4af3ca173992 325 }
arostm 0:4af3ca173992 326
arostm 0:4af3ca173992 327 /* Send the command */
arostm 0:4af3ca173992 328 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 329 {
arostm 0:4af3ca173992 330 return QSPI_ERROR;
arostm 0:4af3ca173992 331 }
arostm 0:4af3ca173992 332
arostm 0:4af3ca173992 333 /* Configure automatic polling mode to wait for end of erase */
arostm 0:4af3ca173992 334 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
arostm 0:4af3ca173992 335 {
arostm 0:4af3ca173992 336 return QSPI_ERROR;
arostm 0:4af3ca173992 337 }
arostm 0:4af3ca173992 338
arostm 0:4af3ca173992 339 return QSPI_OK;
arostm 0:4af3ca173992 340 }
arostm 0:4af3ca173992 341
arostm 0:4af3ca173992 342 /**
arostm 0:4af3ca173992 343 * @brief Erases the entire QSPI memory.
arostm 0:4af3ca173992 344 * @retval QSPI memory status
arostm 0:4af3ca173992 345 */
arostm 0:4af3ca173992 346 uint8_t BSP_QSPI_Erase_Chip(void)
arostm 0:4af3ca173992 347 {
arostm 0:4af3ca173992 348 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 349
arostm 0:4af3ca173992 350 /* Initialize the erase command */
arostm 0:4af3ca173992 351 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 352 s_command.Instruction = BULK_ERASE_CMD;
arostm 0:4af3ca173992 353 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 354 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 355 s_command.DataMode = QSPI_DATA_NONE;
arostm 0:4af3ca173992 356 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 357 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 358 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 359 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 360
arostm 0:4af3ca173992 361 /* Enable write operations */
arostm 0:4af3ca173992 362 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
arostm 0:4af3ca173992 363 {
arostm 0:4af3ca173992 364 return QSPI_ERROR;
arostm 0:4af3ca173992 365 }
arostm 0:4af3ca173992 366
arostm 0:4af3ca173992 367 /* Send the command */
arostm 0:4af3ca173992 368 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 369 {
arostm 0:4af3ca173992 370 return QSPI_ERROR;
arostm 0:4af3ca173992 371 }
arostm 0:4af3ca173992 372
arostm 0:4af3ca173992 373 /* Configure automatic polling mode to wait for end of erase */
arostm 0:4af3ca173992 374 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
arostm 0:4af3ca173992 375 {
arostm 0:4af3ca173992 376 return QSPI_ERROR;
arostm 0:4af3ca173992 377 }
arostm 0:4af3ca173992 378
arostm 0:4af3ca173992 379 return QSPI_OK;
arostm 0:4af3ca173992 380 }
arostm 0:4af3ca173992 381
arostm 0:4af3ca173992 382 /**
arostm 0:4af3ca173992 383 * @brief Reads current status of the QSPI memory.
arostm 0:4af3ca173992 384 * @retval QSPI memory status
arostm 0:4af3ca173992 385 */
arostm 0:4af3ca173992 386 uint8_t BSP_QSPI_GetStatus(void)
arostm 0:4af3ca173992 387 {
arostm 0:4af3ca173992 388 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 389 uint8_t reg;
arostm 0:4af3ca173992 390
arostm 0:4af3ca173992 391 /* Initialize the read flag status register command */
arostm 0:4af3ca173992 392 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 393 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
arostm 0:4af3ca173992 394 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 395 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 396 s_command.DataMode = QSPI_DATA_1_LINE;
arostm 0:4af3ca173992 397 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 398 s_command.NbData = 1;
arostm 0:4af3ca173992 399 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 400 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 401 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 402
arostm 0:4af3ca173992 403 /* Configure the command */
arostm 0:4af3ca173992 404 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 405 {
arostm 0:4af3ca173992 406 return QSPI_ERROR;
arostm 0:4af3ca173992 407 }
arostm 0:4af3ca173992 408
arostm 0:4af3ca173992 409 /* Reception of the data */
arostm 0:4af3ca173992 410 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 411 {
arostm 0:4af3ca173992 412 return QSPI_ERROR;
arostm 0:4af3ca173992 413 }
arostm 0:4af3ca173992 414
arostm 0:4af3ca173992 415 /* Check the value of the register */
arostm 0:4af3ca173992 416 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
arostm 0:4af3ca173992 417 {
arostm 0:4af3ca173992 418 return QSPI_ERROR;
arostm 0:4af3ca173992 419 }
arostm 0:4af3ca173992 420 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
arostm 0:4af3ca173992 421 {
arostm 0:4af3ca173992 422 return QSPI_SUSPENDED;
arostm 0:4af3ca173992 423 }
arostm 0:4af3ca173992 424 else if ((reg & N25Q128A_FSR_READY) != 0)
arostm 0:4af3ca173992 425 {
arostm 0:4af3ca173992 426 return QSPI_OK;
arostm 0:4af3ca173992 427 }
arostm 0:4af3ca173992 428 else
arostm 0:4af3ca173992 429 {
arostm 0:4af3ca173992 430 return QSPI_BUSY;
arostm 0:4af3ca173992 431 }
arostm 0:4af3ca173992 432 }
arostm 0:4af3ca173992 433
arostm 0:4af3ca173992 434 /**
arostm 0:4af3ca173992 435 * @brief Return the configuration of the QSPI memory.
arostm 0:4af3ca173992 436 * @param pInfo: pointer on the configuration structure
arostm 0:4af3ca173992 437 * @retval QSPI memory status
arostm 0:4af3ca173992 438 */
arostm 0:4af3ca173992 439 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
arostm 0:4af3ca173992 440 {
arostm 0:4af3ca173992 441 /* Configure the structure with the memory configuration */
arostm 0:4af3ca173992 442 pInfo->FlashSize = N25Q128A_FLASH_SIZE;
arostm 0:4af3ca173992 443 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE;
arostm 0:4af3ca173992 444 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
arostm 0:4af3ca173992 445 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE;
arostm 0:4af3ca173992 446 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
arostm 0:4af3ca173992 447
arostm 0:4af3ca173992 448 return QSPI_OK;
arostm 0:4af3ca173992 449 }
arostm 0:4af3ca173992 450
arostm 0:4af3ca173992 451 /**
arostm 0:4af3ca173992 452 * @brief Configure the QSPI in memory-mapped mode
arostm 0:4af3ca173992 453 * @retval QSPI memory status
arostm 0:4af3ca173992 454 */
arostm 0:4af3ca173992 455 uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
arostm 0:4af3ca173992 456 {
arostm 0:4af3ca173992 457 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 458 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
arostm 0:4af3ca173992 459
arostm 0:4af3ca173992 460 /* Configure the command for the read instruction */
arostm 0:4af3ca173992 461 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 462 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
arostm 0:4af3ca173992 463 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
arostm 0:4af3ca173992 464 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
arostm 0:4af3ca173992 465 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 466 s_command.DataMode = QSPI_DATA_4_LINES;
arostm 0:4af3ca173992 467 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
arostm 0:4af3ca173992 468 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 469 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 470 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 471
arostm 0:4af3ca173992 472 /* Configure the memory mapped mode */
arostm 0:4af3ca173992 473 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
arostm 0:4af3ca173992 474
arostm 0:4af3ca173992 475 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
arostm 0:4af3ca173992 476 {
arostm 0:4af3ca173992 477 return QSPI_ERROR;
arostm 0:4af3ca173992 478 }
arostm 0:4af3ca173992 479
arostm 0:4af3ca173992 480 return QSPI_OK;
arostm 0:4af3ca173992 481 }
arostm 0:4af3ca173992 482
arostm 0:4af3ca173992 483 /**
arostm 0:4af3ca173992 484 * @brief QSPI MSP Initialization
arostm 0:4af3ca173992 485 * This function configures the hardware resources used in this example:
arostm 0:4af3ca173992 486 * - Peripheral's clock enable
arostm 0:4af3ca173992 487 * - Peripheral's GPIO Configuration
arostm 0:4af3ca173992 488 * - NVIC configuration for QSPI interrupt
arostm 0:4af3ca173992 489 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 490 * @param Params : pointer on additional configuration parameters, can be NULL.
arostm 0:4af3ca173992 491 */
arostm 0:4af3ca173992 492 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
arostm 0:4af3ca173992 493 {
arostm 0:4af3ca173992 494 GPIO_InitTypeDef gpio_init_structure;
arostm 0:4af3ca173992 495
arostm 0:4af3ca173992 496 /* Prevent unused argument(s) compilation warning */
arostm 0:4af3ca173992 497 UNUSED(Params);
arostm 0:4af3ca173992 498
arostm 0:4af3ca173992 499 /*##-1- Enable peripherals and GPIO Clocks #################################*/
arostm 0:4af3ca173992 500 /* Enable the QuadSPI memory interface clock */
arostm 0:4af3ca173992 501 QSPI_CLK_ENABLE();
arostm 0:4af3ca173992 502 /* Reset the QuadSPI memory interface */
arostm 0:4af3ca173992 503 QSPI_FORCE_RESET();
arostm 0:4af3ca173992 504 QSPI_RELEASE_RESET();
arostm 0:4af3ca173992 505 /* Enable GPIO clocks */
arostm 0:4af3ca173992 506 QSPI_CS_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 507 QSPI_CLK_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 508 QSPI_D0_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 509 QSPI_D1_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 510 QSPI_D2_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 511 QSPI_D3_GPIO_CLK_ENABLE();
arostm 0:4af3ca173992 512
arostm 0:4af3ca173992 513 /*##-2- Configure peripheral GPIO ##########################################*/
arostm 0:4af3ca173992 514 /* QSPI CS GPIO pin configuration */
arostm 0:4af3ca173992 515 gpio_init_structure.Pin = QSPI_CS_PIN;
arostm 0:4af3ca173992 516 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
arostm 0:4af3ca173992 517 gpio_init_structure.Pull = GPIO_PULLUP;
arostm 0:4af3ca173992 518 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
arostm 0:4af3ca173992 519 gpio_init_structure.Alternate = GPIO_AF10_QSPI;
arostm 0:4af3ca173992 520 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 521
arostm 0:4af3ca173992 522 /* QSPI CLK GPIO pin configuration */
arostm 0:4af3ca173992 523 gpio_init_structure.Pin = QSPI_CLK_PIN;
arostm 0:4af3ca173992 524 gpio_init_structure.Pull = GPIO_NOPULL;
arostm 0:4af3ca173992 525 gpio_init_structure.Alternate = GPIO_AF9_QSPI;
arostm 0:4af3ca173992 526 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 527
arostm 0:4af3ca173992 528 /* QSPI D0 GPIO pin configuration */
arostm 0:4af3ca173992 529 gpio_init_structure.Pin = QSPI_D0_PIN;
arostm 0:4af3ca173992 530 gpio_init_structure.Alternate = GPIO_AF10_QSPI;
arostm 0:4af3ca173992 531 HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 532
arostm 0:4af3ca173992 533 /* QSPI D1 GPIO pin configuration */
arostm 0:4af3ca173992 534 gpio_init_structure.Pin = QSPI_D1_PIN;
arostm 0:4af3ca173992 535 gpio_init_structure.Alternate = GPIO_AF10_QSPI;
arostm 0:4af3ca173992 536 HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 537
arostm 0:4af3ca173992 538 /* QSPI D2 GPIO pin configuration */
arostm 0:4af3ca173992 539 gpio_init_structure.Pin = QSPI_D2_PIN;
arostm 0:4af3ca173992 540 gpio_init_structure.Alternate = GPIO_AF9_QSPI;
arostm 0:4af3ca173992 541 HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 542
arostm 0:4af3ca173992 543 /* QSPI D3 GPIO pin configuration */
arostm 0:4af3ca173992 544 gpio_init_structure.Pin = QSPI_D3_PIN;
arostm 0:4af3ca173992 545 gpio_init_structure.Alternate = GPIO_AF9_QSPI;
arostm 0:4af3ca173992 546 HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure);
arostm 0:4af3ca173992 547
arostm 0:4af3ca173992 548 /*##-3- Configure the NVIC for QSPI #########################################*/
arostm 0:4af3ca173992 549 /* NVIC configuration for QSPI interrupt */
arostm 0:4af3ca173992 550 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0x00);
arostm 0:4af3ca173992 551 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
arostm 0:4af3ca173992 552 }
arostm 0:4af3ca173992 553
arostm 0:4af3ca173992 554
arostm 0:4af3ca173992 555 /**
arostm 0:4af3ca173992 556 * @brief QSPI MSP De-Initialization
arostm 0:4af3ca173992 557 * This function frees the hardware resources used in this example:
arostm 0:4af3ca173992 558 * - Disable the Peripheral's clock
arostm 0:4af3ca173992 559 * - Revert GPIO and NVIC configuration to their default state
arostm 0:4af3ca173992 560 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 561 * @param Params : pointer on additional configuration parameters, can be NULL.
arostm 0:4af3ca173992 562 */
arostm 0:4af3ca173992 563 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
arostm 0:4af3ca173992 564 {
arostm 0:4af3ca173992 565 /* Prevent unused argument(s) compilation warning */
arostm 0:4af3ca173992 566 UNUSED(Params);
arostm 0:4af3ca173992 567
arostm 0:4af3ca173992 568 /*##-1- Disable the NVIC for QSPI ###########################################*/
arostm 0:4af3ca173992 569 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
arostm 0:4af3ca173992 570
arostm 0:4af3ca173992 571 /*##-2- Disable peripherals and GPIO Clocks ################################*/
arostm 0:4af3ca173992 572 /* De-Configure QSPI pins */
arostm 0:4af3ca173992 573 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
arostm 0:4af3ca173992 574 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
arostm 0:4af3ca173992 575 HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN);
arostm 0:4af3ca173992 576 HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN);
arostm 0:4af3ca173992 577 HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN);
arostm 0:4af3ca173992 578 HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN);
arostm 0:4af3ca173992 579
arostm 0:4af3ca173992 580 /*##-3- Reset peripherals ##################################################*/
arostm 0:4af3ca173992 581 /* Reset the QuadSPI memory interface */
arostm 0:4af3ca173992 582 QSPI_FORCE_RESET();
arostm 0:4af3ca173992 583 QSPI_RELEASE_RESET();
arostm 0:4af3ca173992 584
arostm 0:4af3ca173992 585 /* Disable the QuadSPI memory interface clock */
arostm 0:4af3ca173992 586 QSPI_CLK_DISABLE();
arostm 0:4af3ca173992 587 }
arostm 0:4af3ca173992 588
arostm 0:4af3ca173992 589 /**
arostm 0:4af3ca173992 590 * @}
arostm 0:4af3ca173992 591 */
arostm 0:4af3ca173992 592
arostm 0:4af3ca173992 593 /** @addtogroup STM32F413H_DISCOVERY_QSPI_Private_Functions
arostm 0:4af3ca173992 594 * @{
arostm 0:4af3ca173992 595 */
arostm 0:4af3ca173992 596
arostm 0:4af3ca173992 597 /**
arostm 0:4af3ca173992 598 * @brief This function reset the QSPI memory.
arostm 0:4af3ca173992 599 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 600 */
arostm 0:4af3ca173992 601 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
arostm 0:4af3ca173992 602 {
arostm 0:4af3ca173992 603 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 604
arostm 0:4af3ca173992 605 /* Initialize the reset enable command */
arostm 0:4af3ca173992 606 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 607 s_command.Instruction = RESET_ENABLE_CMD;
arostm 0:4af3ca173992 608 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 609 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 610 s_command.DataMode = QSPI_DATA_NONE;
arostm 0:4af3ca173992 611 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 612 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 613 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 614 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 615
arostm 0:4af3ca173992 616 /* Send the command */
arostm 0:4af3ca173992 617 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 618 {
arostm 0:4af3ca173992 619 return QSPI_ERROR;
arostm 0:4af3ca173992 620 }
arostm 0:4af3ca173992 621
arostm 0:4af3ca173992 622 /* Send the reset memory command */
arostm 0:4af3ca173992 623 s_command.Instruction = RESET_MEMORY_CMD;
arostm 0:4af3ca173992 624 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 625 {
arostm 0:4af3ca173992 626 return QSPI_ERROR;
arostm 0:4af3ca173992 627 }
arostm 0:4af3ca173992 628
arostm 0:4af3ca173992 629 /* Configure automatic polling mode to wait the memory is ready */
arostm 0:4af3ca173992 630 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
arostm 0:4af3ca173992 631 {
arostm 0:4af3ca173992 632 return QSPI_ERROR;
arostm 0:4af3ca173992 633 }
arostm 0:4af3ca173992 634
arostm 0:4af3ca173992 635 return QSPI_OK;
arostm 0:4af3ca173992 636 }
arostm 0:4af3ca173992 637
arostm 0:4af3ca173992 638 /**
arostm 0:4af3ca173992 639 * @brief This function configure the dummy cycles on memory side.
arostm 0:4af3ca173992 640 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 641 */
arostm 0:4af3ca173992 642 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
arostm 0:4af3ca173992 643 {
arostm 0:4af3ca173992 644 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 645 uint8_t reg;
arostm 0:4af3ca173992 646
arostm 0:4af3ca173992 647 /* Initialize the read volatile configuration register command */
arostm 0:4af3ca173992 648 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 649 s_command.Instruction = READ_VOL_CFG_REG_CMD;
arostm 0:4af3ca173992 650 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 651 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 652 s_command.DataMode = QSPI_DATA_1_LINE;
arostm 0:4af3ca173992 653 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 654 s_command.NbData = 1;
arostm 0:4af3ca173992 655 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 656 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 657 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 658
arostm 0:4af3ca173992 659 /* Configure the command */
arostm 0:4af3ca173992 660 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 661 {
arostm 0:4af3ca173992 662 return QSPI_ERROR;
arostm 0:4af3ca173992 663 }
arostm 0:4af3ca173992 664
arostm 0:4af3ca173992 665 /* Reception of the data */
arostm 0:4af3ca173992 666 if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 667 {
arostm 0:4af3ca173992 668 return QSPI_ERROR;
arostm 0:4af3ca173992 669 }
arostm 0:4af3ca173992 670
arostm 0:4af3ca173992 671 /* Enable write operations */
arostm 0:4af3ca173992 672 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
arostm 0:4af3ca173992 673 {
arostm 0:4af3ca173992 674 return QSPI_ERROR;
arostm 0:4af3ca173992 675 }
arostm 0:4af3ca173992 676
arostm 0:4af3ca173992 677 /* Update volatile configuration register (with new dummy cycles) */
arostm 0:4af3ca173992 678 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
arostm 0:4af3ca173992 679 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
arostm 0:4af3ca173992 680
arostm 0:4af3ca173992 681 /* Configure the write volatile configuration register command */
arostm 0:4af3ca173992 682 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 683 {
arostm 0:4af3ca173992 684 return QSPI_ERROR;
arostm 0:4af3ca173992 685 }
arostm 0:4af3ca173992 686
arostm 0:4af3ca173992 687 /* Transmission of the data */
arostm 0:4af3ca173992 688 if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 689 {
arostm 0:4af3ca173992 690 return QSPI_ERROR;
arostm 0:4af3ca173992 691 }
arostm 0:4af3ca173992 692
arostm 0:4af3ca173992 693 return QSPI_OK;
arostm 0:4af3ca173992 694 }
arostm 0:4af3ca173992 695
arostm 0:4af3ca173992 696 /**
arostm 0:4af3ca173992 697 * @brief This function send a Write Enable and wait it is effective.
arostm 0:4af3ca173992 698 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 699 */
arostm 0:4af3ca173992 700 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
arostm 0:4af3ca173992 701 {
arostm 0:4af3ca173992 702 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 703 QSPI_AutoPollingTypeDef s_config;
arostm 0:4af3ca173992 704
arostm 0:4af3ca173992 705 /* Enable write operations */
arostm 0:4af3ca173992 706 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 707 s_command.Instruction = WRITE_ENABLE_CMD;
arostm 0:4af3ca173992 708 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 709 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 710 s_command.DataMode = QSPI_DATA_NONE;
arostm 0:4af3ca173992 711 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 712 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 713 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 714 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 715
arostm 0:4af3ca173992 716 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 717 {
arostm 0:4af3ca173992 718 return QSPI_ERROR;
arostm 0:4af3ca173992 719 }
arostm 0:4af3ca173992 720
arostm 0:4af3ca173992 721 /* Configure automatic polling mode to wait for write enabling */
arostm 0:4af3ca173992 722 s_config.Match = N25Q128A_SR_WREN;
arostm 0:4af3ca173992 723 s_config.Mask = N25Q128A_SR_WREN;
arostm 0:4af3ca173992 724 s_config.MatchMode = QSPI_MATCH_MODE_AND;
arostm 0:4af3ca173992 725 s_config.StatusBytesSize = 1;
arostm 0:4af3ca173992 726 s_config.Interval = 0x10;
arostm 0:4af3ca173992 727 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
arostm 0:4af3ca173992 728
arostm 0:4af3ca173992 729 s_command.Instruction = READ_STATUS_REG_CMD;
arostm 0:4af3ca173992 730 s_command.DataMode = QSPI_DATA_1_LINE;
arostm 0:4af3ca173992 731
arostm 0:4af3ca173992 732 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
arostm 0:4af3ca173992 733 {
arostm 0:4af3ca173992 734 return QSPI_ERROR;
arostm 0:4af3ca173992 735 }
arostm 0:4af3ca173992 736
arostm 0:4af3ca173992 737 return QSPI_OK;
arostm 0:4af3ca173992 738 }
arostm 0:4af3ca173992 739
arostm 0:4af3ca173992 740 /**
arostm 0:4af3ca173992 741 * @brief This function read the SR of the memory and wait the EOP.
arostm 0:4af3ca173992 742 * @param hqspi: QSPI handle
arostm 0:4af3ca173992 743 * @param Timeout
arostm 0:4af3ca173992 744 */
arostm 0:4af3ca173992 745 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
arostm 0:4af3ca173992 746 {
arostm 0:4af3ca173992 747 QSPI_CommandTypeDef s_command;
arostm 0:4af3ca173992 748 QSPI_AutoPollingTypeDef s_config;
arostm 0:4af3ca173992 749
arostm 0:4af3ca173992 750 /* Configure automatic polling mode to wait for memory ready */
arostm 0:4af3ca173992 751 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
arostm 0:4af3ca173992 752 s_command.Instruction = READ_STATUS_REG_CMD;
arostm 0:4af3ca173992 753 s_command.AddressMode = QSPI_ADDRESS_NONE;
arostm 0:4af3ca173992 754 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
arostm 0:4af3ca173992 755 s_command.DataMode = QSPI_DATA_1_LINE;
arostm 0:4af3ca173992 756 s_command.DummyCycles = 0;
arostm 0:4af3ca173992 757 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
arostm 0:4af3ca173992 758 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
arostm 0:4af3ca173992 759 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
arostm 0:4af3ca173992 760
arostm 0:4af3ca173992 761 s_config.Match = 0;
arostm 0:4af3ca173992 762 s_config.Mask = N25Q128A_SR_WIP;
arostm 0:4af3ca173992 763 s_config.MatchMode = QSPI_MATCH_MODE_AND;
arostm 0:4af3ca173992 764 s_config.StatusBytesSize = 1;
arostm 0:4af3ca173992 765 s_config.Interval = 0x10;
arostm 0:4af3ca173992 766 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
arostm 0:4af3ca173992 767
arostm 0:4af3ca173992 768 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
arostm 0:4af3ca173992 769 {
arostm 0:4af3ca173992 770 return QSPI_ERROR;
arostm 0:4af3ca173992 771 }
arostm 0:4af3ca173992 772
arostm 0:4af3ca173992 773 return QSPI_OK;
arostm 0:4af3ca173992 774 }
arostm 0:4af3ca173992 775 /**
arostm 0:4af3ca173992 776 * @}
arostm 0:4af3ca173992 777 */
arostm 0:4af3ca173992 778
arostm 0:4af3ca173992 779 /**
arostm 0:4af3ca173992 780 * @}
arostm 0:4af3ca173992 781 */
arostm 0:4af3ca173992 782
arostm 0:4af3ca173992 783 /**
arostm 0:4af3ca173992 784 * @}
arostm 0:4af3ca173992 785 */
arostm 0:4af3ca173992 786
arostm 0:4af3ca173992 787 /**
arostm 0:4af3ca173992 788 * @}
arostm 0:4af3ca173992 789 */
arostm 0:4af3ca173992 790
arostm 0:4af3ca173992 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
arostm 0:4af3ca173992 792