Daniel Lee / BSP_DISCO_F413ZH

Patched for Audio example - Add status check when DFSDM's filter and channel de-init.

Dependents:   DISCO_F413ZH-AUDIO-demo

The base repository is https://os.mbed.com/teams/ST/code/BSP_DISCO_F413ZH/. I've just added workaround patch for Audio-in demo on DISCO_F413ZH board(Microphone U16, U17)

Drivers/BSP/STM32F413H-Discovery/stm32f413h_discovery_psram.c@4:c051317d4051, 2020-01-31 (annotated)

Committer:
Daniel_Lee
Date:
Fri Jan 31 07:17:05 2020 +0000
Revision:
4:c051317d4051
Parent:
3:42b354f5069c 
Patched for Audio example;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
arostm 0:4af3ca173992 1 /**
arostm 0:4af3ca173992 2 ******************************************************************************
arostm 0:4af3ca173992 3 * @file stm32f413h_discovery_psram.c
arostm 0:4af3ca173992 4 * @author MCD Application Team
arostm 0:4af3ca173992 5 * @brief This file includes the PSRAM driver for the IS61WV51216BLL-10MLI memory
arostm 0:4af3ca173992 6 * device mounted on STM32F413H-DISCOVERY boards.
arostm 0:4af3ca173992 7 @verbatim
arostm 0:4af3ca173992 8 How To use this driver:
arostm 0:4af3ca173992 9 -----------------------
arostm 0:4af3ca173992 10 - This driver is used to drive the IS61WV51216BLL-10M PSRAM external memory mounted
arostm 0:4af3ca173992 11 on STM32F413H-DisCovERYevaluation board.
arostm 0:4af3ca173992 12 - This driver does not need a specific component driver for the PSRAM device
arostm 0:4af3ca173992 13 to be included with.
arostm 0:4af3ca173992 14
arostm 0:4af3ca173992 15 Driver description:
arostm 0:4af3ca173992 16 ------------------
arostm 0:4af3ca173992 17 + Initialization steps:
arostm 0:4af3ca173992 18 o Initialize the PSRAM external memory using the BSP_PSRAM_Init() function. This
arostm 0:4af3ca173992 19 function includes the MSP layer hardware resources initialization and the
arostm 0:4af3ca173992 20 FSMC controller configuration to interface with the external PSRAM memory.
arostm 0:4af3ca173992 21
arostm 0:4af3ca173992 22 + PSRAM read/write operations
arostm 0:4af3ca173992 23 o PSRAM external memory can be accessed with read/write operations once it is
arostm 0:4af3ca173992 24 initialized.
arostm 0:4af3ca173992 25 Read/write operation can be performed with AHB access using the functions
arostm 0:4af3ca173992 26 BSP_PSRAM_ReadData()/BSP_PSRAM_WriteData(), or by DMA transfer using the functions
arostm 0:4af3ca173992 27 BSP_PSRAM_ReadData_DMA()/BSP_PSRAM_WriteData_DMA().
arostm 0:4af3ca173992 28 o The AHB access is performed with 16-bit width transaction, the DMA transfer
arostm 0:4af3ca173992 29 configuration is fixed at single (no burst) halfword transfer
arostm 0:4af3ca173992 30 (see the PSRAM_MspInit() static function).
arostm 0:4af3ca173992 31 o User can implement his own functions for read/write access with his desired
arostm 0:4af3ca173992 32 configurations.
arostm 0:4af3ca173992 33 o If interrupt mode is used for DMA transfer, the function BSP_PSRAM_DMA_IRQHandler()
arostm 0:4af3ca173992 34 is called in IRQ handler file, to serve the generated interrupt once the DMA
arostm 0:4af3ca173992 35 transfer is complete.
arostm 0:4af3ca173992 36 @endverbatim
arostm 0:4af3ca173992 37 ******************************************************************************
arostm 0:4af3ca173992 38 * @attention
arostm 0:4af3ca173992 39 *
arostm 0:4af3ca173992 40 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
arostm 0:4af3ca173992 41 *
arostm 0:4af3ca173992 42 * Redistribution and use in source and binary forms, with or without modification,
arostm 0:4af3ca173992 43 * are permitted provided that the following conditions are met:
arostm 0:4af3ca173992 44 * 1. Redistributions of source code must retain the above copyright notice,
arostm 0:4af3ca173992 45 * this list of conditions and the following disclaimer.
arostm 0:4af3ca173992 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
arostm 0:4af3ca173992 47 * this list of conditions and the following disclaimer in the documentation
arostm 0:4af3ca173992 48 * and/or other materials provided with the distribution.
arostm 0:4af3ca173992 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
arostm 0:4af3ca173992 50 * may be used to endorse or promote products derived from this software
arostm 0:4af3ca173992 51 * without specific prior written permission.
arostm 0:4af3ca173992 52 *
arostm 0:4af3ca173992 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
arostm 0:4af3ca173992 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
arostm 0:4af3ca173992 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
arostm 0:4af3ca173992 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
arostm 0:4af3ca173992 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
arostm 0:4af3ca173992 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
arostm 0:4af3ca173992 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
arostm 0:4af3ca173992 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
arostm 0:4af3ca173992 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
arostm 0:4af3ca173992 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
arostm 0:4af3ca173992 63 *
arostm 0:4af3ca173992 64 ******************************************************************************
arostm 0:4af3ca173992 65 */
arostm 0:4af3ca173992 66
arostm 0:4af3ca173992 67 /* Includes ------------------------------------------------------------------*/
arostm 0:4af3ca173992 68 #include "stm32f413h_discovery_psram.h"
arostm 0:4af3ca173992 69
arostm 0:4af3ca173992 70 /** @addtogroup BSP
arostm 0:4af3ca173992 71 * @{
arostm 0:4af3ca173992 72 */
arostm 0:4af3ca173992 73
arostm 0:4af3ca173992 74 /** @addtogroup STM32F413H_DISCOVERY
arostm 0:4af3ca173992 75 * @{
arostm 0:4af3ca173992 76 */
arostm 0:4af3ca173992 77
arostm 0:4af3ca173992 78 /** @defgroup STM32F413H_DISCOVERY_PSRAM STM32F413H_DISCOVERY PSRAM
arostm 0:4af3ca173992 79 * @{
arostm 0:4af3ca173992 80 */
arostm 0:4af3ca173992 81
arostm 0:4af3ca173992 82 /** @defgroup STM32F413H_DISCOVERY_PSRAM_Private_Variables STM32F413H DISCOVERY PSRAM Private Variables
arostm 0:4af3ca173992 83 * @{
arostm 0:4af3ca173992 84 */
arostm 0:4af3ca173992 85 SRAM_HandleTypeDef psramHandle;
arostm 0:4af3ca173992 86 static FSMC_NORSRAM_TimingTypeDef Timing;
arostm 0:4af3ca173992 87
arostm 0:4af3ca173992 88 /**
arostm 0:4af3ca173992 89 * @}
arostm 0:4af3ca173992 90 */
arostm 0:4af3ca173992 91
arostm 0:4af3ca173992 92 /** @defgroup STM32F413H_DISCOVERY_PSRAM_Private_Functions STM32F413H DISCOVERY PSRAM Private Functions
arostm 0:4af3ca173992 93 * @{
arostm 0:4af3ca173992 94 */
arostm 0:4af3ca173992 95
arostm 0:4af3ca173992 96 /**
arostm 0:4af3ca173992 97 * @brief Initializes the PSRAM device.
arostm 0:4af3ca173992 98 * @retval PSRAM status
arostm 0:4af3ca173992 99 */
arostm 0:4af3ca173992 100 uint8_t BSP_PSRAM_Init(void)
arostm 0:4af3ca173992 101 {
arostm 0:4af3ca173992 102 static uint8_t psram_status = PSRAM_ERROR;
arostm 0:4af3ca173992 103 /* SRAM device configuration */
arostm 0:4af3ca173992 104 psramHandle.Instance = FSMC_NORSRAM_DEVICE;
arostm 0:4af3ca173992 105 psramHandle.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
arostm 0:4af3ca173992 106
arostm 0:4af3ca173992 107 /* PSRAM device configuration */
arostm 0:4af3ca173992 108 /* Timing configuration derived from system clock (up to 100Mhz)*/
arostm 0:4af3ca173992 109 Timing.AddressSetupTime = 3;
arostm 0:4af3ca173992 110 Timing.AddressHoldTime = 1;
arostm 0:4af3ca173992 111 Timing.DataSetupTime = 4;
arostm 0:4af3ca173992 112 Timing.BusTurnAroundDuration = 1;
arostm 0:4af3ca173992 113 Timing.CLKDivision = 2;
arostm 0:4af3ca173992 114 Timing.DataLatency = 2;
arostm 0:4af3ca173992 115 Timing.AccessMode = FSMC_ACCESS_MODE_A;
arostm 0:4af3ca173992 116
arostm 0:4af3ca173992 117 psramHandle.Init.NSBank = FSMC_NORSRAM_BANK1;
arostm 0:4af3ca173992 118 psramHandle.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
arostm 0:4af3ca173992 119 psramHandle.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
arostm 0:4af3ca173992 120 psramHandle.Init.MemoryDataWidth = PSRAM_MEMORY_WIDTH;
arostm 0:4af3ca173992 121 psramHandle.Init.BurstAccessMode = PSRAM_BURSTACCESS;
arostm 0:4af3ca173992 122 psramHandle.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
arostm 0:4af3ca173992 123 psramHandle.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
arostm 0:4af3ca173992 124 psramHandle.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
arostm 0:4af3ca173992 125 psramHandle.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
arostm 0:4af3ca173992 126 psramHandle.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
arostm 0:4af3ca173992 127 psramHandle.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
arostm 0:4af3ca173992 128 psramHandle.Init.WriteBurst = PSRAM_WRITEBURST;
arostm 0:4af3ca173992 129 psramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
arostm 0:4af3ca173992 130
arostm 0:4af3ca173992 131 /* PSRAM controller initialization */
arostm 0:4af3ca173992 132 BSP_PSRAM_MspInit(&psramHandle, NULL); /* __weak function can be rewritten by the application */
arostm 0:4af3ca173992 133 if(HAL_SRAM_Init(&psramHandle, &Timing, &Timing) != HAL_OK)
arostm 0:4af3ca173992 134 {
arostm 0:4af3ca173992 135 psram_status = PSRAM_ERROR;
arostm 0:4af3ca173992 136 }
arostm 0:4af3ca173992 137 else
arostm 0:4af3ca173992 138 {
arostm 0:4af3ca173992 139 psram_status = PSRAM_OK;
arostm 0:4af3ca173992 140 }
arostm 0:4af3ca173992 141 return psram_status;
arostm 0:4af3ca173992 142 }
arostm 0:4af3ca173992 143
arostm 0:4af3ca173992 144 /**
arostm 0:4af3ca173992 145 * @brief DeInitializes the PSRAM device.
arostm 0:4af3ca173992 146 * @retval PSRAM status
arostm 0:4af3ca173992 147 */
arostm 0:4af3ca173992 148 uint8_t BSP_PSRAM_DeInit(void)
arostm 0:4af3ca173992 149 {
arostm 0:4af3ca173992 150 static uint8_t psram_status = PSRAM_ERROR;
arostm 0:4af3ca173992 151 /* PSRAM device de-initialization */
arostm 0:4af3ca173992 152 psramHandle.Instance = FSMC_NORSRAM_DEVICE;
arostm 0:4af3ca173992 153 psramHandle.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
arostm 0:4af3ca173992 154
arostm 0:4af3ca173992 155 if(HAL_SRAM_DeInit(&psramHandle) != HAL_OK)
arostm 0:4af3ca173992 156 {
arostm 0:4af3ca173992 157 psram_status = PSRAM_ERROR;
arostm 0:4af3ca173992 158 }
arostm 0:4af3ca173992 159 else
arostm 0:4af3ca173992 160 {
arostm 0:4af3ca173992 161 psram_status = PSRAM_OK;
arostm 0:4af3ca173992 162 }
arostm 0:4af3ca173992 163
arostm 0:4af3ca173992 164 /* PSRAM controller de-initialization */
arostm 0:4af3ca173992 165 BSP_PSRAM_MspDeInit(&psramHandle, NULL);
arostm 0:4af3ca173992 166
arostm 0:4af3ca173992 167 return psram_status;
arostm 0:4af3ca173992 168 }
arostm 0:4af3ca173992 169
arostm 0:4af3ca173992 170 /**
arostm 0:4af3ca173992 171 * @brief Reads an amount of data from the PSRAM device in polling mode.
arostm 0:4af3ca173992 172 * @param uwStartAddress: Read start address
arostm 0:4af3ca173992 173 * @param pData: Pointer to data to be read
arostm 0:4af3ca173992 174 * @param uwDataSize: Size of read data from the memory
arostm 0:4af3ca173992 175 * @retval PSRAM status
arostm 0:4af3ca173992 176 */
arostm 0:4af3ca173992 177 uint8_t BSP_PSRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
arostm 0:4af3ca173992 178 {
arostm 0:4af3ca173992 179 if(HAL_SRAM_Read_16b(&psramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
arostm 0:4af3ca173992 180 {
arostm 0:4af3ca173992 181 return PSRAM_ERROR;
arostm 0:4af3ca173992 182 }
arostm 0:4af3ca173992 183 else
arostm 0:4af3ca173992 184 {
arostm 0:4af3ca173992 185 return PSRAM_OK;
arostm 0:4af3ca173992 186 }
arostm 0:4af3ca173992 187 }
arostm 0:4af3ca173992 188
arostm 0:4af3ca173992 189 /**
arostm 0:4af3ca173992 190 * @brief Reads an amount of data from the PSRAM device in DMA mode.
arostm 0:4af3ca173992 191 * @param uwStartAddress: Read start address
arostm 0:4af3ca173992 192 * @param pData: Pointer to data to be read
arostm 0:4af3ca173992 193 * @param uwDataSize: Size of read data from the memory
arostm 0:4af3ca173992 194 * @retval PSRAM status
arostm 0:4af3ca173992 195 */
arostm 0:4af3ca173992 196 uint8_t BSP_PSRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
arostm 0:4af3ca173992 197 {
arostm 0:4af3ca173992 198 if(HAL_SRAM_Read_DMA(&psramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
arostm 0:4af3ca173992 199 {
arostm 0:4af3ca173992 200 return PSRAM_ERROR;
arostm 0:4af3ca173992 201 }
arostm 0:4af3ca173992 202 else
arostm 0:4af3ca173992 203 {
arostm 0:4af3ca173992 204 return PSRAM_OK;
arostm 0:4af3ca173992 205 }
arostm 0:4af3ca173992 206 }
arostm 0:4af3ca173992 207
arostm 0:4af3ca173992 208 /**
arostm 0:4af3ca173992 209 * @brief Writes an amount of data from the PSRAM device in polling mode.
arostm 0:4af3ca173992 210 * @param uwStartAddress: Write start address
arostm 0:4af3ca173992 211 * @param pData: Pointer to data to be written
arostm 0:4af3ca173992 212 * @param uwDataSize: Size of written data from the memory
arostm 0:4af3ca173992 213 * @retval PSRAM status
arostm 0:4af3ca173992 214 */
arostm 0:4af3ca173992 215 uint8_t BSP_PSRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
arostm 0:4af3ca173992 216 {
arostm 0:4af3ca173992 217 if(HAL_SRAM_Write_16b(&psramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
arostm 0:4af3ca173992 218 {
arostm 0:4af3ca173992 219 return PSRAM_ERROR;
arostm 0:4af3ca173992 220 }
arostm 0:4af3ca173992 221 else
arostm 0:4af3ca173992 222 {
arostm 0:4af3ca173992 223 return PSRAM_OK;
arostm 0:4af3ca173992 224 }
arostm 0:4af3ca173992 225 }
arostm 0:4af3ca173992 226
arostm 0:4af3ca173992 227 /**
arostm 0:4af3ca173992 228 * @brief Writes an amount of data from the PSRAM device in DMA mode.
arostm 0:4af3ca173992 229 * @param uwStartAddress: Write start address
arostm 0:4af3ca173992 230 * @param pData: Pointer to data to be written
arostm 0:4af3ca173992 231 * @param uwDataSize: Size of written data from the memory
arostm 0:4af3ca173992 232 * @retval PSRAM status
arostm 0:4af3ca173992 233 */
arostm 0:4af3ca173992 234 uint8_t BSP_PSRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
arostm 0:4af3ca173992 235 {
arostm 0:4af3ca173992 236 if(HAL_SRAM_Write_DMA(&psramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
arostm 0:4af3ca173992 237 {
arostm 0:4af3ca173992 238 return PSRAM_ERROR;
arostm 0:4af3ca173992 239 }
arostm 0:4af3ca173992 240 else
arostm 0:4af3ca173992 241 {
arostm 0:4af3ca173992 242 return PSRAM_OK;
arostm 0:4af3ca173992 243 }
arostm 0:4af3ca173992 244 }
arostm 0:4af3ca173992 245
arostm 0:4af3ca173992 246 /**
arostm 0:4af3ca173992 247 * @brief Initializes PSRAM MSP.
arostm 0:4af3ca173992 248 * @param hsram: PSRAM handle
arostm 0:4af3ca173992 249 * @param Params : pointer on additional configuration parameters, can be NULL.
arostm 0:4af3ca173992 250 */
arostm 0:4af3ca173992 251 __weak void BSP_PSRAM_MspInit(SRAM_HandleTypeDef *hsram, void *Params)
arostm 0:4af3ca173992 252 {
arostm 0:4af3ca173992 253 static DMA_HandleTypeDef dma_handle;
arostm 0:4af3ca173992 254 GPIO_InitTypeDef gpio_init_structure;
arostm 0:4af3ca173992 255
arostm 0:4af3ca173992 256 /* Prevent unused argument(s) compilation warning */
arostm 0:4af3ca173992 257 UNUSED(Params);
arostm 0:4af3ca173992 258
arostm 0:4af3ca173992 259 /* Enable FSMC clock */
arostm 0:4af3ca173992 260 __HAL_RCC_FSMC_CLK_ENABLE();
arostm 0:4af3ca173992 261
arostm 0:4af3ca173992 262 /* Enable chosen DMAx clock */
arostm 0:4af3ca173992 263 PSRAM_DMAx_CLK_ENABLE();
arostm 0:4af3ca173992 264
arostm 0:4af3ca173992 265 /* Enable GPIOs clock */
arostm 0:4af3ca173992 266 __HAL_RCC_GPIOD_CLK_ENABLE();
arostm 0:4af3ca173992 267 __HAL_RCC_GPIOE_CLK_ENABLE();
arostm 0:4af3ca173992 268 __HAL_RCC_GPIOF_CLK_ENABLE();
arostm 0:4af3ca173992 269 __HAL_RCC_GPIOG_CLK_ENABLE();
arostm 0:4af3ca173992 270
arostm 0:4af3ca173992 271 /* Common GPIO configuration */
arostm 0:4af3ca173992 272 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
arostm 0:4af3ca173992 273 gpio_init_structure.Pull = GPIO_PULLUP;
arostm 0:4af3ca173992 274 gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
arostm 0:4af3ca173992 275 gpio_init_structure.Alternate = GPIO_AF12_FSMC;
arostm 0:4af3ca173992 276
arostm 0:4af3ca173992 277 /* GPIOD configuration */
arostm 0:4af3ca173992 278 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7 |\
arostm 0:4af3ca173992 279 GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
arostm 0:4af3ca173992 280 GPIO_PIN_14 | GPIO_PIN_15;
arostm 0:4af3ca173992 281 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
arostm 0:4af3ca173992 282
arostm 0:4af3ca173992 283 /* GPIOE configuration */
arostm 0:4af3ca173992 284 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |\
arostm 0:4af3ca173992 285 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
arostm 0:4af3ca173992 286 GPIO_PIN_15;
arostm 0:4af3ca173992 287 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
arostm 0:4af3ca173992 288
arostm 0:4af3ca173992 289 /* GPIOF configuration */
arostm 0:4af3ca173992 290 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
arostm 0:4af3ca173992 291 GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
arostm 0:4af3ca173992 292 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
arostm 0:4af3ca173992 293
arostm 0:4af3ca173992 294 /* GPIOG configuration */
arostm 0:4af3ca173992 295 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
arostm 0:4af3ca173992 296 GPIO_PIN_5;
arostm 0:4af3ca173992 297 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
arostm 0:4af3ca173992 298
arostm 0:4af3ca173992 299 /* Configure common DMA parameters */
arostm 0:4af3ca173992 300 dma_handle.Init.Channel = PSRAM_DMAx_CHANNEL;
arostm 0:4af3ca173992 301 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
arostm 0:4af3ca173992 302 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
arostm 0:4af3ca173992 303 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
arostm 0:4af3ca173992 304 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
arostm 0:4af3ca173992 305 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
arostm 0:4af3ca173992 306 dma_handle.Init.Mode = DMA_NORMAL;
arostm 0:4af3ca173992 307 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
arostm 0:4af3ca173992 308 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
arostm 0:4af3ca173992 309 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
arostm 0:4af3ca173992 310 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
arostm 0:4af3ca173992 311 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
arostm 0:4af3ca173992 312
arostm 0:4af3ca173992 313 dma_handle.Instance = PSRAM_DMAx_STREAM;
arostm 0:4af3ca173992 314
arostm 0:4af3ca173992 315 /* Associate the DMA handle */
arostm 0:4af3ca173992 316 __HAL_LINKDMA(hsram, hdma, dma_handle);
arostm 0:4af3ca173992 317
arostm 0:4af3ca173992 318 /* Deinitialize the Stream for new transfer */
arostm 0:4af3ca173992 319 HAL_DMA_DeInit(&dma_handle);
arostm 0:4af3ca173992 320
arostm 0:4af3ca173992 321 /* Configure the DMA Stream */
arostm 0:4af3ca173992 322 HAL_DMA_Init(&dma_handle);
arostm 0:4af3ca173992 323
arostm 0:4af3ca173992 324 /* NVIC configuration for DMA transfer complete interrupt */
arostm 0:4af3ca173992 325 HAL_NVIC_SetPriority(PSRAM_DMAx_IRQn, 0x0F, 0);
arostm 0:4af3ca173992 326 HAL_NVIC_EnableIRQ(PSRAM_DMAx_IRQn);
arostm 0:4af3ca173992 327 }
arostm 0:4af3ca173992 328
arostm 0:4af3ca173992 329 /**
arostm 0:4af3ca173992 330 * @brief DeInitializes SRAM MSP.
arostm 0:4af3ca173992 331 * @param hsram: SRAM handle
arostm 0:4af3ca173992 332 * @param Params : pointer on additional configuration parameters, can be NULL.
arostm 0:4af3ca173992 333 * @retval None
arostm 0:4af3ca173992 334 */
arostm 0:4af3ca173992 335 __weak void BSP_PSRAM_MspDeInit(SRAM_HandleTypeDef *hsram, void *Params)
arostm 0:4af3ca173992 336 {
arostm 0:4af3ca173992 337 /* Prevent unused argument(s) compilation warning */
arostm 0:4af3ca173992 338 UNUSED(Params);
arostm 0:4af3ca173992 339
arostm 0:4af3ca173992 340 /* Disable NVIC configuration for DMA interrupt */
arostm 0:4af3ca173992 341 HAL_NVIC_DisableIRQ(PSRAM_DMAx_IRQn);
arostm 0:4af3ca173992 342
arostm 0:4af3ca173992 343 if(hsram->Instance != NULL)
arostm 0:4af3ca173992 344 {
arostm 0:4af3ca173992 345 /* Deinitialize the stream for new transfer */
arostm 0:4af3ca173992 346 HAL_DMA_DeInit(hsram->hdma);
arostm 0:4af3ca173992 347 }
arostm 0:4af3ca173992 348
arostm 0:4af3ca173992 349 /* GPIO pins clock, FSMC clock and DMA clock can be shut down in the applications
arostm 0:4af3ca173992 350 by surcharging this __weak function */
arostm 0:4af3ca173992 351 }
arostm 0:4af3ca173992 352 /**
arostm 0:4af3ca173992 353 * @}
arostm 0:4af3ca173992 354 */
arostm 0:4af3ca173992 355
arostm 0:4af3ca173992 356 /**
arostm 0:4af3ca173992 357 * @}
arostm 0:4af3ca173992 358 */
arostm 0:4af3ca173992 359
arostm 0:4af3ca173992 360 /**
arostm 0:4af3ca173992 361 * @}
arostm 0:4af3ca173992 362 */
arostm 0:4af3ca173992 363
arostm 0:4af3ca173992 364 /**
arostm 0:4af3ca173992 365 * @}
arostm 0:4af3ca173992 366 */
arostm 0:4af3ca173992 367
arostm 0:4af3ca173992 368 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/