Fork of Smoothie to port to mbed non-LPC targets.
Fork of Smoothie by
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_pwm.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_pwm.h 2011-03-31 |
Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_pwm.h |
Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for PWM firmware library on LPC17xx |
Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 2.1 |
Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 31. Mar. 2011 |
Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2011, NXP Semiconductor |
Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup PWM PWM (Pulse Width Modulator) |
Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_PWM_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_PWM_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
Michael J. Spencer |
2:1df0b61d3b5a | 46 | |
Michael J. Spencer |
2:1df0b61d3b5a | 47 | /* Private Macros ------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 48 | /** @defgroup PWM_Private_Macros PWM Private Macros |
Michael J. Spencer |
2:1df0b61d3b5a | 49 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 50 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 51 | |
Michael J. Spencer |
2:1df0b61d3b5a | 52 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 53 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 54 | * IR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 55 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 56 | /** Interrupt flag for PWM match channel for 6 channel */ |
Michael J. Spencer |
2:1df0b61d3b5a | 57 | #define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4)))) |
Michael J. Spencer |
2:1df0b61d3b5a | 58 | /** Interrupt flag for capture input */ |
Michael J. Spencer |
2:1df0b61d3b5a | 59 | #define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4))) |
Michael J. Spencer |
2:1df0b61d3b5a | 60 | /** IR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 61 | #define PWM_IR_BITMASK ((uint32_t)(0x0000073F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 62 | |
Michael J. Spencer |
2:1df0b61d3b5a | 63 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 64 | * TCR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 65 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 66 | /** TCR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 67 | #define PWM_TCR_BITMASK ((uint32_t)(0x0000000B)) |
Michael J. Spencer |
2:1df0b61d3b5a | 68 | #define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) /*!< PWM Counter Enable */ |
Michael J. Spencer |
2:1df0b61d3b5a | 69 | #define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) /*!< PWM Counter Reset */ |
Michael J. Spencer |
2:1df0b61d3b5a | 70 | #define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) /*!< PWM Enable */ |
Michael J. Spencer |
2:1df0b61d3b5a | 71 | |
Michael J. Spencer |
2:1df0b61d3b5a | 72 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 73 | * CTCR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 74 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 75 | /** CTCR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 76 | #define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 77 | /** PWM Counter-Timer Mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03)) |
Michael J. Spencer |
2:1df0b61d3b5a | 79 | /** PWM Capture input select */ |
Michael J. Spencer |
2:1df0b61d3b5a | 80 | #define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 81 | |
Michael J. Spencer |
2:1df0b61d3b5a | 82 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 83 | * MCR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 84 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 85 | /** MCR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 86 | #define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF)) |
Michael J. Spencer |
2:1df0b61d3b5a | 87 | /** generate a PWM interrupt when a MATCHn occurs */ |
Michael J. Spencer |
2:1df0b61d3b5a | 88 | #define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)))) |
Michael J. Spencer |
2:1df0b61d3b5a | 89 | /** reset the PWM when a MATCHn occurs */ |
Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1))) |
Michael J. Spencer |
2:1df0b61d3b5a | 91 | /** stop the PWM when a MATCHn occurs */ |
Michael J. Spencer |
2:1df0b61d3b5a | 92 | #define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2))) |
Michael J. Spencer |
2:1df0b61d3b5a | 93 | |
Michael J. Spencer |
2:1df0b61d3b5a | 94 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 95 | * CCR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 96 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 97 | /** CCR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 98 | #define PWM_CCR_BITMASK ((uint32_t)(0x0000003F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 99 | /** PCAPn is rising edge sensitive */ |
Michael J. Spencer |
2:1df0b61d3b5a | 100 | #define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)))) |
Michael J. Spencer |
2:1df0b61d3b5a | 101 | /** PCAPn is falling edge sensitive */ |
Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1))) |
Michael J. Spencer |
2:1df0b61d3b5a | 103 | /** PWM interrupt is generated on a PCAP event */ |
Michael J. Spencer |
2:1df0b61d3b5a | 104 | #define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2))) |
Michael J. Spencer |
2:1df0b61d3b5a | 105 | |
Michael J. Spencer |
2:1df0b61d3b5a | 106 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 107 | * PCR register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 108 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 109 | /** PCR register mask */ |
Michael J. Spencer |
2:1df0b61d3b5a | 110 | #define PWM_PCR_BITMASK (uint32_t)0x00007E7C |
Michael J. Spencer |
2:1df0b61d3b5a | 111 | /** PWM output n is a single edge controlled output */ |
Michael J. Spencer |
2:1df0b61d3b5a | 112 | #define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n))) |
Michael J. Spencer |
2:1df0b61d3b5a | 113 | /** enable PWM output n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 114 | #define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8)))) |
Michael J. Spencer |
2:1df0b61d3b5a | 115 | |
Michael J. Spencer |
2:1df0b61d3b5a | 116 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 117 | * LER register definitions |
Michael J. Spencer |
2:1df0b61d3b5a | 118 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 119 | /** LER register mask*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 120 | #define PWM_LER_BITMASK ((uint32_t)(0x0000007F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 121 | /** PWM MATCHn register update control */ |
Michael J. Spencer |
2:1df0b61d3b5a | 122 | #define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 123 | |
Michael J. Spencer |
2:1df0b61d3b5a | 124 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 125 | /** Macro to determine if it is valid PWM peripheral or not */ |
Michael J. Spencer |
2:1df0b61d3b5a | 126 | #define PARAM_PWMx(n) (((uint32_t *)n)==((uint32_t *)LPC_PWM1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 127 | |
Michael J. Spencer |
2:1df0b61d3b5a | 128 | /** Macro check PWM1 match channel value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 129 | #define PARAM_PWM1_MATCH_CHANNEL(n) ((n>=0) && (n<=6)) |
Michael J. Spencer |
2:1df0b61d3b5a | 130 | |
Michael J. Spencer |
2:1df0b61d3b5a | 131 | /** Macro check PWM1 channel value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 132 | #define PARAM_PWM1_CHANNEL(n) ((n>=1) && (n<=6)) |
Michael J. Spencer |
2:1df0b61d3b5a | 133 | |
Michael J. Spencer |
2:1df0b61d3b5a | 134 | /** Macro check PWM1 edge channel mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 135 | #define PARAM_PWM1_EDGE_MODE_CHANNEL(n) ((n>=2) && (n<=6)) |
Michael J. Spencer |
2:1df0b61d3b5a | 136 | |
Michael J. Spencer |
2:1df0b61d3b5a | 137 | /** Macro check PWM1 capture channel mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 138 | #define PARAM_PWM1_CAPTURE_CHANNEL(n) ((n==0) || (n==1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 139 | |
Michael J. Spencer |
2:1df0b61d3b5a | 140 | /** Macro check PWM1 interrupt status type */ |
Michael J. Spencer |
2:1df0b61d3b5a | 141 | #define PARAM_PWM_INTSTAT(n) ((n==PWM_INTSTAT_MR0) || (n==PWM_INTSTAT_MR1) || (n==PWM_INTSTAT_MR2) \ |
Michael J. Spencer |
2:1df0b61d3b5a | 142 | || (n==PWM_INTSTAT_MR3) || (n==PWM_INTSTAT_MR4) || (n==PWM_INTSTAT_MR5) \ |
Michael J. Spencer |
2:1df0b61d3b5a | 143 | || (n==PWM_INTSTAT_MR6) || (n==PWM_INTSTAT_CAP0) || (n==PWM_INTSTAT_CAP1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 144 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 145 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 146 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 147 | |
Michael J. Spencer |
2:1df0b61d3b5a | 148 | |
Michael J. Spencer |
2:1df0b61d3b5a | 149 | /* Public Types --------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 150 | /** @defgroup PWM_Public_Types PWM Public Types |
Michael J. Spencer |
2:1df0b61d3b5a | 151 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 152 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 153 | |
Michael J. Spencer |
2:1df0b61d3b5a | 154 | /** @brief Configuration structure in PWM TIMER mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 155 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 156 | |
Michael J. Spencer |
2:1df0b61d3b5a | 157 | uint8_t PrescaleOption; /**< Prescale option, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 158 | - PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value |
Michael J. Spencer |
2:1df0b61d3b5a | 159 | - PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value |
Michael J. Spencer |
2:1df0b61d3b5a | 160 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 161 | uint8_t Reserved[3]; |
Michael J. Spencer |
2:1df0b61d3b5a | 162 | uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched |
Michael J. Spencer |
2:1df0b61d3b5a | 163 | with PrescaleOption |
Michael J. Spencer |
2:1df0b61d3b5a | 164 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 165 | } PWM_TIMERCFG_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 166 | |
Michael J. Spencer |
2:1df0b61d3b5a | 167 | /** @brief Configuration structure in PWM COUNTER mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 168 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 169 | |
Michael J. Spencer |
2:1df0b61d3b5a | 170 | uint8_t CounterOption; /**< Counter Option, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 171 | - PWM_COUNTER_RISING: Rising Edge |
Michael J. Spencer |
2:1df0b61d3b5a | 172 | - PWM_COUNTER_FALLING: Falling Edge |
Michael J. Spencer |
2:1df0b61d3b5a | 173 | - PWM_COUNTER_ANY: Both rising and falling mode |
Michael J. Spencer |
2:1df0b61d3b5a | 174 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 175 | uint8_t CountInputSelect; /**< Counter input select, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 176 | - PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin |
Michael J. Spencer |
2:1df0b61d3b5a | 177 | - PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin |
Michael J. Spencer |
2:1df0b61d3b5a | 178 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 179 | uint8_t Reserved[2]; |
Michael J. Spencer |
2:1df0b61d3b5a | 180 | } PWM_COUNTERCFG_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 181 | |
Michael J. Spencer |
2:1df0b61d3b5a | 182 | /** @brief PWM Match channel configuration structure */ |
Michael J. Spencer |
2:1df0b61d3b5a | 183 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 184 | uint8_t MatchChannel; /**< Match channel, should be in range |
Michael J. Spencer |
2:1df0b61d3b5a | 185 | from 0..6 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 186 | uint8_t IntOnMatch; /**< Interrupt On match, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 187 | - ENABLE: Enable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 188 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 189 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 190 | uint8_t StopOnMatch; /**< Stop On match, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 191 | - ENABLE: Enable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 192 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 193 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 194 | uint8_t ResetOnMatch; /**< Reset On match, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 195 | - ENABLE: Enable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 196 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 197 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 198 | } PWM_MATCHCFG_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 199 | |
Michael J. Spencer |
2:1df0b61d3b5a | 200 | |
Michael J. Spencer |
2:1df0b61d3b5a | 201 | /** @brief PWM Capture Input configuration structure */ |
Michael J. Spencer |
2:1df0b61d3b5a | 202 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 203 | uint8_t CaptureChannel; /**< Capture channel, should be in range |
Michael J. Spencer |
2:1df0b61d3b5a | 204 | from 0..1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 205 | uint8_t RisingEdge; /**< caption rising edge, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 206 | - ENABLE: Enable rising edge. |
Michael J. Spencer |
2:1df0b61d3b5a | 207 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 208 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 209 | uint8_t FallingEdge; /**< caption falling edge, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 210 | - ENABLE: Enable falling edge. |
Michael J. Spencer |
2:1df0b61d3b5a | 211 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 212 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 213 | uint8_t IntOnCaption; /**< Interrupt On caption, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 214 | - ENABLE: Enable interrupt function. |
Michael J. Spencer |
2:1df0b61d3b5a | 215 | - DISABLE: Disable this function. |
Michael J. Spencer |
2:1df0b61d3b5a | 216 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 217 | } PWM_CAPTURECFG_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 218 | |
Michael J. Spencer |
2:1df0b61d3b5a | 219 | /* Timer/Counter in PWM configuration type definition -----------------------------------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 220 | |
Michael J. Spencer |
2:1df0b61d3b5a | 221 | /** @brief PMW TC mode select option */ |
Michael J. Spencer |
2:1df0b61d3b5a | 222 | typedef enum { |
Michael J. Spencer |
2:1df0b61d3b5a | 223 | PWM_MODE_TIMER = 0, /*!< PWM using Timer mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 224 | PWM_MODE_COUNTER /*!< PWM using Counter mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 225 | } PWM_TC_MODE_OPT; |
Michael J. Spencer |
2:1df0b61d3b5a | 226 | |
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2:1df0b61d3b5a | 227 | #define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER)) |
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2:1df0b61d3b5a | 228 | |
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2:1df0b61d3b5a | 229 | |
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2:1df0b61d3b5a | 230 | /** @brief PWM Timer/Counter prescale option */ |
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2:1df0b61d3b5a | 231 | typedef enum |
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2:1df0b61d3b5a | 232 | { |
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2:1df0b61d3b5a | 233 | PWM_TIMER_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */ |
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2:1df0b61d3b5a | 234 | PWM_TIMER_PRESCALE_USVAL /*!< Prescale in microsecond value */ |
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2:1df0b61d3b5a | 235 | } PWM_TIMER_PRESCALE_OPT; |
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2:1df0b61d3b5a | 236 | |
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2:1df0b61d3b5a | 237 | #define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL)) |
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2:1df0b61d3b5a | 238 | |
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2:1df0b61d3b5a | 239 | |
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2:1df0b61d3b5a | 240 | /** @brief PWM Input Select in counter mode */ |
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2:1df0b61d3b5a | 241 | typedef enum { |
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2:1df0b61d3b5a | 242 | PWM_COUNTER_PCAP1_0 = 0, /*!< PWM Counter input selected is PCAP1.0 pin */ |
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2:1df0b61d3b5a | 243 | PWM_COUNTER_PCAP1_1 /*!< PWM counter input selected is CAP1.1 pin */ |
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2:1df0b61d3b5a | 244 | } PWM_COUNTER_INPUTSEL_OPT; |
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2:1df0b61d3b5a | 245 | |
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2:1df0b61d3b5a | 246 | #define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1)) |
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2:1df0b61d3b5a | 247 | |
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2:1df0b61d3b5a | 248 | /** @brief PWM Input Edge Option in counter mode */ |
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2:1df0b61d3b5a | 249 | typedef enum { |
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2:1df0b61d3b5a | 250 | PWM_COUNTER_RISING = 1, /*!< Rising edge mode */ |
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2:1df0b61d3b5a | 251 | PWM_COUNTER_FALLING = 2, /*!< Falling edge mode */ |
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2:1df0b61d3b5a | 252 | PWM_COUNTER_ANY = 3 /*!< Both rising and falling mode */ |
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2:1df0b61d3b5a | 253 | } PWM_COUNTER_EDGE_OPT; |
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2:1df0b61d3b5a | 254 | |
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2:1df0b61d3b5a | 255 | #define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \ |
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2:1df0b61d3b5a | 256 | || (n==PWM_COUNTER_ANY)) |
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2:1df0b61d3b5a | 257 | |
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2:1df0b61d3b5a | 258 | |
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2:1df0b61d3b5a | 259 | /* PWM configuration type definition ----------------------------------------------------- */ |
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2:1df0b61d3b5a | 260 | /** @brief PWM operating mode options */ |
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2:1df0b61d3b5a | 261 | typedef enum { |
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2:1df0b61d3b5a | 262 | PWM_CHANNEL_SINGLE_EDGE, /*!< PWM Channel Single edge mode */ |
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2:1df0b61d3b5a | 263 | PWM_CHANNEL_DUAL_EDGE /*!< PWM Channel Dual edge mode */ |
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2:1df0b61d3b5a | 264 | } PWM_CHANNEL_EDGE_OPT; |
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2:1df0b61d3b5a | 265 | |
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2:1df0b61d3b5a | 266 | #define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE)) |
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2:1df0b61d3b5a | 267 | |
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2:1df0b61d3b5a | 268 | |
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2:1df0b61d3b5a | 269 | /** @brief PWM update type */ |
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2:1df0b61d3b5a | 270 | typedef enum { |
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2:1df0b61d3b5a | 271 | PWM_MATCH_UPDATE_NOW = 0, /**< PWM Match Channel Update Now */ |
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2:1df0b61d3b5a | 272 | PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next |
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2:1df0b61d3b5a | 273 | PWM Counter resetting */ |
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2:1df0b61d3b5a | 274 | } PWM_MATCH_UPDATE_OPT; |
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2:1df0b61d3b5a | 275 | |
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2:1df0b61d3b5a | 276 | #define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST)) |
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2:1df0b61d3b5a | 277 | |
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2:1df0b61d3b5a | 278 | |
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2:1df0b61d3b5a | 279 | /** @brief PWM interrupt status type definition ----------------------------------------------------- */ |
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2:1df0b61d3b5a | 280 | /** @brief PWM Interrupt status type */ |
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2:1df0b61d3b5a | 281 | typedef enum |
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2:1df0b61d3b5a | 282 | { |
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2:1df0b61d3b5a | 283 | PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /**< Interrupt flag for PWM match channel 0 */ |
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2:1df0b61d3b5a | 284 | PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /**< Interrupt flag for PWM match channel 1 */ |
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2:1df0b61d3b5a | 285 | PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /**< Interrupt flag for PWM match channel 2 */ |
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2:1df0b61d3b5a | 286 | PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /**< Interrupt flag for PWM match channel 3 */ |
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2:1df0b61d3b5a | 287 | PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /**< Interrupt flag for capture input 0 */ |
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2:1df0b61d3b5a | 288 | PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /**< Interrupt flag for capture input 1 */ |
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2:1df0b61d3b5a | 289 | PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /**< Interrupt flag for PWM match channel 4 */ |
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2:1df0b61d3b5a | 290 | PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /**< Interrupt flag for PWM match channel 5 */ |
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2:1df0b61d3b5a | 291 | PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6) /**< Interrupt flag for PWM match channel 6 */ |
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2:1df0b61d3b5a | 292 | }PWM_INTSTAT_TYPE; |
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2:1df0b61d3b5a | 293 | |
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2:1df0b61d3b5a | 294 | /** @brief Match update structure */ |
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2:1df0b61d3b5a | 295 | typedef struct |
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2:1df0b61d3b5a | 296 | { |
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2:1df0b61d3b5a | 297 | uint32_t Matchvalue; |
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2:1df0b61d3b5a | 298 | FlagStatus Status; |
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2:1df0b61d3b5a | 299 | }PWM_Match_T; |
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2:1df0b61d3b5a | 300 | |
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2:1df0b61d3b5a | 301 | /** |
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2:1df0b61d3b5a | 302 | * @} |
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2:1df0b61d3b5a | 303 | */ |
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2:1df0b61d3b5a | 304 | |
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2:1df0b61d3b5a | 305 | |
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2:1df0b61d3b5a | 306 | /* Public Functions ----------------------------------------------------------- */ |
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2:1df0b61d3b5a | 307 | /** @defgroup PWM_Public_Functions PWM Public Functions |
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2:1df0b61d3b5a | 308 | * @{ |
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2:1df0b61d3b5a | 309 | */ |
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2:1df0b61d3b5a | 310 | |
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2:1df0b61d3b5a | 311 | void PWM_PinConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWM_Channel, uint8_t PinselOption); |
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2:1df0b61d3b5a | 312 | IntStatus PWM_GetIntStatus(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag); |
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2:1df0b61d3b5a | 313 | void PWM_ClearIntPending(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag); |
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2:1df0b61d3b5a | 314 | void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct); |
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2:1df0b61d3b5a | 315 | void PWM_Init(LPC_PWM_TypeDef *PWMx, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct); |
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2:1df0b61d3b5a | 316 | void PWM_DeInit (LPC_PWM_TypeDef *PWMx); |
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2:1df0b61d3b5a | 317 | void PWM_Cmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState); |
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2:1df0b61d3b5a | 318 | void PWM_CounterCmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState); |
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2:1df0b61d3b5a | 319 | void PWM_ResetCounter(LPC_PWM_TypeDef *PWMx); |
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2:1df0b61d3b5a | 320 | void PWM_ConfigMatch(LPC_PWM_TypeDef *PWMx, PWM_MATCHCFG_Type *PWM_MatchConfigStruct); |
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2:1df0b61d3b5a | 321 | void PWM_ConfigCapture(LPC_PWM_TypeDef *PWMx, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct); |
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2:1df0b61d3b5a | 322 | uint32_t PWM_GetCaptureValue(LPC_PWM_TypeDef *PWMx, uint8_t CaptureChannel); |
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2:1df0b61d3b5a | 323 | void PWM_MatchUpdate(LPC_PWM_TypeDef *PWMx, uint8_t MatchChannel, \ |
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2:1df0b61d3b5a | 324 | uint32_t MatchValue, uint8_t UpdateType); |
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2:1df0b61d3b5a | 325 | void PWM_ChannelConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, uint8_t ModeOption); |
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2:1df0b61d3b5a | 326 | void PWM_ChannelCmd(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, FunctionalState NewState); |
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2:1df0b61d3b5a | 327 | |
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2:1df0b61d3b5a | 328 | /** |
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2:1df0b61d3b5a | 329 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 330 | */ |
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2:1df0b61d3b5a | 331 | |
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2:1df0b61d3b5a | 332 | #ifdef __cplusplus |
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2:1df0b61d3b5a | 333 | } |
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2:1df0b61d3b5a | 334 | #endif |
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2:1df0b61d3b5a | 335 | |
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2:1df0b61d3b5a | 336 | #endif /* LPC17XX_PWM_H_ */ |
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2:1df0b61d3b5a | 337 | |
Michael J. Spencer |
2:1df0b61d3b5a | 338 | /** |
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2:1df0b61d3b5a | 339 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 340 | */ |
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2:1df0b61d3b5a | 341 | |
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2:1df0b61d3b5a | 342 | /* --------------------------------- End Of File ------------------------------ */ |