Fork of Smoothie to port to mbed non-LPC targets.
Fork of Smoothie by
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_mcpwm.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_mcpwm.h 2010-05-21 |
Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_mcpwm.h |
Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for Motor Control PWM firmware library on LPC17xx |
Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 2.0 |
Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 21. May. 2010 |
Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup MCPWM MCPWM (Motor Control PWM) |
Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_MCPWM_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_MCPWM_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
Michael J. Spencer |
2:1df0b61d3b5a | 46 | /* Public Macros -------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 47 | /** @defgroup MCPWM_Public_Macros MCPWM Public Macros |
Michael J. Spencer |
2:1df0b61d3b5a | 48 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 49 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 50 | |
Michael J. Spencer |
2:1df0b61d3b5a | 51 | |
Michael J. Spencer |
2:1df0b61d3b5a | 52 | /** Edge aligned mode for channel in MCPWM */ |
Michael J. Spencer |
2:1df0b61d3b5a | 53 | #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 54 | /** Center aligned mode for channel in MCPWM */ |
Michael J. Spencer |
2:1df0b61d3b5a | 55 | #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 56 | |
Michael J. Spencer |
2:1df0b61d3b5a | 57 | /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ |
Michael J. Spencer |
2:1df0b61d3b5a | 58 | #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 59 | /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ |
Michael J. Spencer |
2:1df0b61d3b5a | 60 | #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 61 | |
Michael J. Spencer |
2:1df0b61d3b5a | 62 | /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of |
Michael J. Spencer |
2:1df0b61d3b5a | 63 | * the six output pins under the control of the bits in this register */ |
Michael J. Spencer |
2:1df0b61d3b5a | 64 | #define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 65 | #define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 67 | #define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 68 | #define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 69 | #define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 70 | |
Michael J. Spencer |
2:1df0b61d3b5a | 71 | /* Interrupt type in MCPWM */ |
Michael J. Spencer |
2:1df0b61d3b5a | 72 | /** Limit interrupt for channel (0) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 73 | #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) |
Michael J. Spencer |
2:1df0b61d3b5a | 74 | /** Match interrupt for channel (0) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 75 | #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) |
Michael J. Spencer |
2:1df0b61d3b5a | 76 | /** Capture interrupt for channel (0) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 77 | #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) |
Michael J. Spencer |
2:1df0b61d3b5a | 78 | |
Michael J. Spencer |
2:1df0b61d3b5a | 79 | /** Limit interrupt for channel (1) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 80 | #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) |
Michael J. Spencer |
2:1df0b61d3b5a | 81 | /** Match interrupt for channel (1) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 82 | #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) |
Michael J. Spencer |
2:1df0b61d3b5a | 83 | /** Capture interrupt for channel (1) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 84 | #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) |
Michael J. Spencer |
2:1df0b61d3b5a | 85 | |
Michael J. Spencer |
2:1df0b61d3b5a | 86 | /** Limit interrupt for channel (2) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 87 | #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) |
Michael J. Spencer |
2:1df0b61d3b5a | 88 | /** Match interrupt for channel (2) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 89 | #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) |
Michael J. Spencer |
2:1df0b61d3b5a | 90 | /** Capture interrupt for channel (2) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 91 | #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) |
Michael J. Spencer |
2:1df0b61d3b5a | 92 | |
Michael J. Spencer |
2:1df0b61d3b5a | 93 | /** Fast abort interrupt */ |
Michael J. Spencer |
2:1df0b61d3b5a | 94 | #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT |
Michael J. Spencer |
2:1df0b61d3b5a | 95 | |
Michael J. Spencer |
2:1df0b61d3b5a | 96 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 97 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 98 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 99 | |
Michael J. Spencer |
2:1df0b61d3b5a | 100 | /* Private Macros ------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 101 | /** @defgroup MCPWM_Private_Macros MCPWM Private Macros |
Michael J. Spencer |
2:1df0b61d3b5a | 102 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 103 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 104 | |
Michael J. Spencer |
2:1df0b61d3b5a | 105 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 106 | * Macro defines for MCPWM Control register |
Michael J. Spencer |
2:1df0b61d3b5a | 107 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 108 | /* MCPWM Control register, these macro definitions below can be applied for these |
Michael J. Spencer |
2:1df0b61d3b5a | 109 | * register type: |
Michael J. Spencer |
2:1df0b61d3b5a | 110 | * - MCPWM Control read address |
Michael J. Spencer |
2:1df0b61d3b5a | 111 | * - MCPWM Control set address |
Michael J. Spencer |
2:1df0b61d3b5a | 112 | * - MCPWM Control clear address |
Michael J. Spencer |
2:1df0b61d3b5a | 113 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 114 | #define MCPWM_CON_RUN(n) ((n<=2) ? ((uint32_t)(1UL<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 115 | #define MCPWM_CON_CENTER(n) ((n<=2) ? ((uint32_t)(1UL<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 116 | #define MCPWM_CON_POLAR(n) ((n<=2) ? ((uint32_t)(1UL<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */ |
Michael J. Spencer |
2:1df0b61d3b5a | 117 | #define MCPWM_CON_DTE(n) ((n<=2) ? ((uint32_t)(1UL<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 118 | #define MCPWM_CON_DISUP(n) ((n<=2) ? ((uint32_t)(1UL<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 119 | #define MCPWM_CON_INVBDC ((uint32_t)(1UL<<29)) /**< Control the polarity for all 3 channels */ |
Michael J. Spencer |
2:1df0b61d3b5a | 120 | #define MCPWM_CON_ACMODE ((uint32_t)(1UL<<30)) /**< 3-phase AC mode select */ |
Michael J. Spencer |
2:1df0b61d3b5a | 121 | #define MCPWM_CON_DCMODE ((uint32_t)(1UL<<31)) /**< 3-phase DC mode select */ |
Michael J. Spencer |
2:1df0b61d3b5a | 122 | |
Michael J. Spencer |
2:1df0b61d3b5a | 123 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 124 | * Macro defines for MCPWM Capture Control register |
Michael J. Spencer |
2:1df0b61d3b5a | 125 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 126 | /* Capture Control register, these macro definitions below can be applied for these |
Michael J. Spencer |
2:1df0b61d3b5a | 127 | * register type: |
Michael J. Spencer |
2:1df0b61d3b5a | 128 | * - MCPWM Capture Control read address |
Michael J. Spencer |
2:1df0b61d3b5a | 129 | * - MCPWM Capture Control set address |
Michael J. Spencer |
2:1df0b61d3b5a | 130 | * - MCPWM Capture control clear address |
Michael J. Spencer |
2:1df0b61d3b5a | 131 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 132 | /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 133 | #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 134 | /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 135 | #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 136 | /** TC(n) is reset by channel (n) capture event */ |
Michael J. Spencer |
2:1df0b61d3b5a | 137 | #define MCPWM_CAPCON_RT(n) ((n<=2) ? ((uint32_t)(1<<(18+(n)))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 138 | /** Hardware noise filter: channel (n) capture events are delayed */ |
Michael J. Spencer |
2:1df0b61d3b5a | 139 | #define MCPWM_CAPCON_HNFCAP(n) ((n<=2) ? ((uint32_t)(1<<(21+(n)))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 140 | |
Michael J. Spencer |
2:1df0b61d3b5a | 141 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 142 | * Macro defines for MCPWM Interrupt register |
Michael J. Spencer |
2:1df0b61d3b5a | 143 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 144 | /* Interrupt registers, these macro definitions below can be applied for these |
Michael J. Spencer |
2:1df0b61d3b5a | 145 | * register type: |
Michael J. Spencer |
2:1df0b61d3b5a | 146 | * - MCPWM Interrupt Enable read address |
Michael J. Spencer |
2:1df0b61d3b5a | 147 | * - MCPWM Interrupt Enable set address |
Michael J. Spencer |
2:1df0b61d3b5a | 148 | * - MCPWM Interrupt Enable clear address |
Michael J. Spencer |
2:1df0b61d3b5a | 149 | * - MCPWM Interrupt Flags read address |
Michael J. Spencer |
2:1df0b61d3b5a | 150 | * - MCPWM Interrupt Flags set address |
Michael J. Spencer |
2:1df0b61d3b5a | 151 | * - MCPWM Interrupt Flags clear address |
Michael J. Spencer |
2:1df0b61d3b5a | 152 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 153 | /** Limit interrupt for channel (n) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 154 | #define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 155 | /** Match interrupt for channel (n) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 157 | /** Capture interrupt for channel (n) */ |
Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 159 | /** Fast abort interrupt */ |
Michael J. Spencer |
2:1df0b61d3b5a | 160 | #define MCPWM_INT_ABORT ((uint32_t)(1<<15)) |
Michael J. Spencer |
2:1df0b61d3b5a | 161 | |
Michael J. Spencer |
2:1df0b61d3b5a | 162 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 163 | * Macro defines for MCPWM Count Control register |
Michael J. Spencer |
2:1df0b61d3b5a | 164 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 165 | /* MCPWM Count Control register, these macro definitions below can be applied for these |
Michael J. Spencer |
2:1df0b61d3b5a | 166 | * register type: |
Michael J. Spencer |
2:1df0b61d3b5a | 167 | * - MCPWM Count Control read address |
Michael J. Spencer |
2:1df0b61d3b5a | 168 | * - MCPWM Count Control set address |
Michael J. Spencer |
2:1df0b61d3b5a | 169 | * - MCPWM Count Control clear address |
Michael J. Spencer |
2:1df0b61d3b5a | 170 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 171 | /** Counter(tc) advances on a rising edge on MCI(mci) pin */ |
Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 173 | /** Counter(cnt) advances on a falling edge on MCI(mci) pin */ |
Michael J. Spencer |
2:1df0b61d3b5a | 174 | #define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 175 | /** Channel (n) is in counter mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 176 | #define MCPWM_CNTCON_CNTR(n) ((n<=2) ? ((uint32_t)(1<<(29+n))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 177 | |
Michael J. Spencer |
2:1df0b61d3b5a | 178 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 179 | * Macro defines for MCPWM Dead-time register |
Michael J. Spencer |
2:1df0b61d3b5a | 180 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 181 | /** Dead time value x for channel n */ |
Michael J. Spencer |
2:1df0b61d3b5a | 182 | #define MCPWM_DT(n,x) ((n<=2) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 183 | |
Michael J. Spencer |
2:1df0b61d3b5a | 184 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 185 | * Macro defines for MCPWM Communication Pattern register |
Michael J. Spencer |
2:1df0b61d3b5a | 186 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 187 | #define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 188 | #define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 189 | #define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 190 | #define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 191 | #define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 192 | #define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 193 | |
Michael J. Spencer |
2:1df0b61d3b5a | 194 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 195 | * Macro defines for MCPWM Capture clear address register |
Michael J. Spencer |
2:1df0b61d3b5a | 196 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 197 | /** Clear the MCCAP (n) register */ |
Michael J. Spencer |
2:1df0b61d3b5a | 198 | #define MCPWM_CAPCLR_CAP(n) ((n<=2) ? ((uint32_t)(1<<n)) : (0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 199 | |
Michael J. Spencer |
2:1df0b61d3b5a | 200 | |
Michael J. Spencer |
2:1df0b61d3b5a | 201 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 202 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 203 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 204 | |
Michael J. Spencer |
2:1df0b61d3b5a | 205 | |
Michael J. Spencer |
2:1df0b61d3b5a | 206 | /* Public Types --------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 207 | /** @defgroup MCPWM_Public_Types MCPWM Public Types |
Michael J. Spencer |
2:1df0b61d3b5a | 208 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 209 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 210 | |
Michael J. Spencer |
2:1df0b61d3b5a | 211 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 212 | * @brief Motor Control PWM Channel Configuration structure type definition |
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2:1df0b61d3b5a | 213 | */ |
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2:1df0b61d3b5a | 214 | typedef struct { |
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2:1df0b61d3b5a | 215 | uint32_t channelType; /**< Edge/center aligned mode for this channel, |
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2:1df0b61d3b5a | 216 | should be: |
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2:1df0b61d3b5a | 217 | - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode |
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2:1df0b61d3b5a | 218 | - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode |
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2:1df0b61d3b5a | 219 | */ |
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2:1df0b61d3b5a | 220 | uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be: |
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2:1df0b61d3b5a | 221 | - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH |
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2:1df0b61d3b5a | 222 | - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW |
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2:1df0b61d3b5a | 223 | */ |
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2:1df0b61d3b5a | 224 | uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be: |
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2:1df0b61d3b5a | 225 | - ENABLE. |
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2:1df0b61d3b5a | 226 | - DISABLE. |
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2:1df0b61d3b5a | 227 | */ |
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2:1df0b61d3b5a | 228 | uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */ |
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2:1df0b61d3b5a | 229 | uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers, |
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2:1df0b61d3b5a | 230 | should be: |
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2:1df0b61d3b5a | 231 | - ENABLE. |
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2:1df0b61d3b5a | 232 | - DISABLE. |
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2:1df0b61d3b5a | 233 | */ |
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2:1df0b61d3b5a | 234 | uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */ |
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2:1df0b61d3b5a | 235 | uint32_t channelPeriodValue; /**< MCPWM Period value */ |
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2:1df0b61d3b5a | 236 | uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */ |
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2:1df0b61d3b5a | 237 | } MCPWM_CHANNEL_CFG_Type; |
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2:1df0b61d3b5a | 238 | |
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2:1df0b61d3b5a | 239 | /** |
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2:1df0b61d3b5a | 240 | * @brief MCPWM Capture Configuration type definition |
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2:1df0b61d3b5a | 241 | */ |
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2:1df0b61d3b5a | 242 | typedef struct { |
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2:1df0b61d3b5a | 243 | uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */ |
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2:1df0b61d3b5a | 244 | uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
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2:1df0b61d3b5a | 245 | - ENABLE. |
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2:1df0b61d3b5a | 246 | - DISABLE. |
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2:1df0b61d3b5a | 247 | */ |
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2:1df0b61d3b5a | 248 | uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
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2:1df0b61d3b5a | 249 | - ENABLE. |
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2:1df0b61d3b5a | 250 | - DISABLE. |
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2:1df0b61d3b5a | 251 | */ |
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2:1df0b61d3b5a | 252 | uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be: |
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2:1df0b61d3b5a | 253 | - ENABLE. |
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2:1df0b61d3b5a | 254 | - DISABLE. |
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2:1df0b61d3b5a | 255 | */ |
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2:1df0b61d3b5a | 256 | uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be: |
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2:1df0b61d3b5a | 257 | - ENABLE. |
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2:1df0b61d3b5a | 258 | - DISABLE. |
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2:1df0b61d3b5a | 259 | */ |
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2:1df0b61d3b5a | 260 | } MCPWM_CAPTURE_CFG_Type; |
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2:1df0b61d3b5a | 261 | |
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2:1df0b61d3b5a | 262 | |
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2:1df0b61d3b5a | 263 | /** |
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2:1df0b61d3b5a | 264 | * @brief MCPWM Count Control Configuration type definition |
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2:1df0b61d3b5a | 265 | */ |
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2:1df0b61d3b5a | 266 | typedef struct { |
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2:1df0b61d3b5a | 267 | uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */ |
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2:1df0b61d3b5a | 268 | uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
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2:1df0b61d3b5a | 269 | - ENABLE. |
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2:1df0b61d3b5a | 270 | - DISABLE. |
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2:1df0b61d3b5a | 271 | */ |
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2:1df0b61d3b5a | 272 | uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
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2:1df0b61d3b5a | 273 | - ENABLE. |
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2:1df0b61d3b5a | 274 | - DISABLE. |
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2:1df0b61d3b5a | 275 | */ |
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2:1df0b61d3b5a | 276 | } MCPWM_COUNT_CFG_Type; |
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2:1df0b61d3b5a | 277 | |
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2:1df0b61d3b5a | 278 | /** |
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2:1df0b61d3b5a | 279 | * @} |
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2:1df0b61d3b5a | 280 | */ |
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2:1df0b61d3b5a | 281 | |
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2:1df0b61d3b5a | 282 | |
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2:1df0b61d3b5a | 283 | /* Public Functions ----------------------------------------------------------- */ |
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2:1df0b61d3b5a | 284 | /** @defgroup MCPWM_Public_Functions MCPWM Public Functions |
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2:1df0b61d3b5a | 285 | * @{ |
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2:1df0b61d3b5a | 286 | */ |
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2:1df0b61d3b5a | 287 | |
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2:1df0b61d3b5a | 288 | void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx); |
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2:1df0b61d3b5a | 289 | void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
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2:1df0b61d3b5a | 290 | MCPWM_CHANNEL_CFG_Type * channelSetup); |
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2:1df0b61d3b5a | 291 | void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
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2:1df0b61d3b5a | 292 | MCPWM_CHANNEL_CFG_Type *channelSetup); |
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2:1df0b61d3b5a | 293 | void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
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2:1df0b61d3b5a | 294 | MCPWM_CAPTURE_CFG_Type *captureConfig); |
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2:1df0b61d3b5a | 295 | void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
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2:1df0b61d3b5a | 296 | uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
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2:1df0b61d3b5a | 297 | void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
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2:1df0b61d3b5a | 298 | uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig); |
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2:1df0b61d3b5a | 299 | void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
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2:1df0b61d3b5a | 300 | void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
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2:1df0b61d3b5a | 301 | void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode); |
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2:1df0b61d3b5a | 302 | void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode, |
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2:1df0b61d3b5a | 303 | uint32_t outputInvered, uint32_t outputPattern); |
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2:1df0b61d3b5a | 304 | void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState); |
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2:1df0b61d3b5a | 305 | void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
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2:1df0b61d3b5a | 306 | void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
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2:1df0b61d3b5a | 307 | FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
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2:1df0b61d3b5a | 308 | |
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2:1df0b61d3b5a | 309 | /** |
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2:1df0b61d3b5a | 310 | * @} |
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2:1df0b61d3b5a | 311 | */ |
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2:1df0b61d3b5a | 312 | |
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2:1df0b61d3b5a | 313 | #ifdef __cplusplus |
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2:1df0b61d3b5a | 314 | } |
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2:1df0b61d3b5a | 315 | #endif |
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2:1df0b61d3b5a | 316 | |
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2:1df0b61d3b5a | 317 | #endif /* LPC17XX_MCPWM_H_ */ |
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2:1df0b61d3b5a | 318 | |
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2:1df0b61d3b5a | 319 | /** |
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2:1df0b61d3b5a | 320 | * @} |
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2:1df0b61d3b5a | 321 | */ |
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2:1df0b61d3b5a | 322 | |
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2:1df0b61d3b5a | 323 | /* --------------------------------- End Of File ------------------------------ */ |