Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_spi.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_spi.h 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_spi.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for SPI firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup SPI SPI (Serial Peripheral Interface)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_SPI_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_SPI_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46 /* Public Macros -------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 47 /** @defgroup SPI_Public_Macros SPI Public Macros
Michael J. Spencer 2:1df0b61d3b5a 48 * @{
Michael J. Spencer 2:1df0b61d3b5a 49 */
Michael J. Spencer 2:1df0b61d3b5a 50
Michael J. Spencer 2:1df0b61d3b5a 51 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 52 * SPI configuration parameter defines
Michael J. Spencer 2:1df0b61d3b5a 53 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 54 /** Clock phase control bit */
Michael J. Spencer 2:1df0b61d3b5a 55 #define SPI_CPHA_FIRST ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 56 #define SPI_CPHA_SECOND ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 57
Michael J. Spencer 2:1df0b61d3b5a 58 /** Clock polarity control bit */
Michael J. Spencer 2:1df0b61d3b5a 59 #define SPI_CPOL_HI ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 60 #define SPI_CPOL_LO ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 61
Michael J. Spencer 2:1df0b61d3b5a 62 /** SPI master mode enable */
Michael J. Spencer 2:1df0b61d3b5a 63 #define SPI_SLAVE_MODE ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 64 #define SPI_MASTER_MODE ((uint32_t)(1<<5))
Michael J. Spencer 2:1df0b61d3b5a 65
Michael J. Spencer 2:1df0b61d3b5a 66 /** LSB enable bit */
Michael J. Spencer 2:1df0b61d3b5a 67 #define SPI_DATA_MSB_FIRST ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 68 #define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
Michael J. Spencer 2:1df0b61d3b5a 69
Michael J. Spencer 2:1df0b61d3b5a 70 /** SPI data bit number defines */
Michael J. Spencer 2:1df0b61d3b5a 71 #define SPI_DATABIT_16 SPI_SPCR_BITS(0) /*!< Databit number = 16 */
Michael J. Spencer 2:1df0b61d3b5a 72 #define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /*!< Databit number = 8 */
Michael J. Spencer 2:1df0b61d3b5a 73 #define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /*!< Databit number = 9 */
Michael J. Spencer 2:1df0b61d3b5a 74 #define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /*!< Databit number = 10 */
Michael J. Spencer 2:1df0b61d3b5a 75 #define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /*!< Databit number = 11 */
Michael J. Spencer 2:1df0b61d3b5a 76 #define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /*!< Databit number = 12 */
Michael J. Spencer 2:1df0b61d3b5a 77 #define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /*!< Databit number = 13 */
Michael J. Spencer 2:1df0b61d3b5a 78 #define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /*!< Databit number = 14 */
Michael J. Spencer 2:1df0b61d3b5a 79 #define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /*!< Databit number = 15 */
Michael J. Spencer 2:1df0b61d3b5a 80
Michael J. Spencer 2:1df0b61d3b5a 81 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 82 * SPI Status Flag defines
Michael J. Spencer 2:1df0b61d3b5a 83 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 84 /** Slave abort */
Michael J. Spencer 2:1df0b61d3b5a 85 #define SPI_STAT_ABRT SPI_SPSR_ABRT
Michael J. Spencer 2:1df0b61d3b5a 86 /** Mode fault */
Michael J. Spencer 2:1df0b61d3b5a 87 #define SPI_STAT_MODF SPI_SPSR_MODF
Michael J. Spencer 2:1df0b61d3b5a 88 /** Read overrun */
Michael J. Spencer 2:1df0b61d3b5a 89 #define SPI_STAT_ROVR SPI_SPSR_ROVR
Michael J. Spencer 2:1df0b61d3b5a 90 /** Write collision */
Michael J. Spencer 2:1df0b61d3b5a 91 #define SPI_STAT_WCOL SPI_SPSR_WCOL
Michael J. Spencer 2:1df0b61d3b5a 92 /** SPI transfer complete flag */
Michael J. Spencer 2:1df0b61d3b5a 93 #define SPI_STAT_SPIF SPI_SPSR_SPIF
Michael J. Spencer 2:1df0b61d3b5a 94
Michael J. Spencer 2:1df0b61d3b5a 95 /* SPI Status Implementation definitions */
Michael J. Spencer 2:1df0b61d3b5a 96 #define SPI_STAT_DONE (1UL<<8) /**< Done */
Michael J. Spencer 2:1df0b61d3b5a 97 #define SPI_STAT_ERROR (1UL<<9) /**< Error */
Michael J. Spencer 2:1df0b61d3b5a 98
Michael J. Spencer 2:1df0b61d3b5a 99 /**
Michael J. Spencer 2:1df0b61d3b5a 100 * @}
Michael J. Spencer 2:1df0b61d3b5a 101 */
Michael J. Spencer 2:1df0b61d3b5a 102
Michael J. Spencer 2:1df0b61d3b5a 103
Michael J. Spencer 2:1df0b61d3b5a 104 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 105 /** @defgroup SPI_Private_Macros SPI Private Macros
Michael J. Spencer 2:1df0b61d3b5a 106 * @{
Michael J. Spencer 2:1df0b61d3b5a 107 */
Michael J. Spencer 2:1df0b61d3b5a 108
Michael J. Spencer 2:1df0b61d3b5a 109 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 110 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 111 * Macro defines for SPI Control Register
Michael J. Spencer 2:1df0b61d3b5a 112 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 113 /** Bit enable, the SPI controller sends and receives the number
Michael J. Spencer 2:1df0b61d3b5a 114 * of bits selected by bits 11:8 */
Michael J. Spencer 2:1df0b61d3b5a 115 #define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 116 /** Clock phase control bit */
Michael J. Spencer 2:1df0b61d3b5a 117 #define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 118 /** Clock polarity control bit */
Michael J. Spencer 2:1df0b61d3b5a 119 #define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 120 /** SPI master mode enable */
Michael J. Spencer 2:1df0b61d3b5a 121 #define SPI_SPCR_MSTR ((uint32_t)(1<<5))
Michael J. Spencer 2:1df0b61d3b5a 122 /** LSB enable bit */
Michael J. Spencer 2:1df0b61d3b5a 123 #define SPI_SPCR_LSBF ((uint32_t)(1<<6))
Michael J. Spencer 2:1df0b61d3b5a 124 /** SPI interrupt enable bit */
Michael J. Spencer 2:1df0b61d3b5a 125 #define SPI_SPCR_SPIE ((uint32_t)(1<<7))
Michael J. Spencer 2:1df0b61d3b5a 126 /** When bit 2 of this register is 1, this field controls the
Michael J. Spencer 2:1df0b61d3b5a 127 number of bits per transfer */
Michael J. Spencer 2:1df0b61d3b5a 128 #define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
Michael J. Spencer 2:1df0b61d3b5a 129 /** SPI Control bit mask */
Michael J. Spencer 2:1df0b61d3b5a 130 #define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
Michael J. Spencer 2:1df0b61d3b5a 131
Michael J. Spencer 2:1df0b61d3b5a 132 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 133 * Macro defines for SPI Status Register
Michael J. Spencer 2:1df0b61d3b5a 134 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 135 /** Slave abort */
Michael J. Spencer 2:1df0b61d3b5a 136 #define SPI_SPSR_ABRT ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 137 /** Mode fault */
Michael J. Spencer 2:1df0b61d3b5a 138 #define SPI_SPSR_MODF ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 139 /** Read overrun */
Michael J. Spencer 2:1df0b61d3b5a 140 #define SPI_SPSR_ROVR ((uint32_t)(1<<5))
Michael J. Spencer 2:1df0b61d3b5a 141 /** Write collision */
Michael J. Spencer 2:1df0b61d3b5a 142 #define SPI_SPSR_WCOL ((uint32_t)(1<<6))
Michael J. Spencer 2:1df0b61d3b5a 143 /** SPI transfer complete flag */
Michael J. Spencer 2:1df0b61d3b5a 144 #define SPI_SPSR_SPIF ((uint32_t)(1<<7))
Michael J. Spencer 2:1df0b61d3b5a 145 /** SPI Status bit mask */
Michael J. Spencer 2:1df0b61d3b5a 146 #define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
Michael J. Spencer 2:1df0b61d3b5a 147
Michael J. Spencer 2:1df0b61d3b5a 148 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 149 * Macro defines for SPI Data Register
Michael J. Spencer 2:1df0b61d3b5a 150 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 151 /** SPI Data low bit-mask */
Michael J. Spencer 2:1df0b61d3b5a 152 #define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
Michael J. Spencer 2:1df0b61d3b5a 153 /** SPI Data high bit-mask */
Michael J. Spencer 2:1df0b61d3b5a 154 #define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
Michael J. Spencer 2:1df0b61d3b5a 155 /** SPI Data bit-mask */
Michael J. Spencer 2:1df0b61d3b5a 156 #define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 157
Michael J. Spencer 2:1df0b61d3b5a 158 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 159 * Macro defines for SPI Clock Counter Register
Michael J. Spencer 2:1df0b61d3b5a 160 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 161 /** SPI clock counter setting */
Michael J. Spencer 2:1df0b61d3b5a 162 #define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 163 /** SPI clock counter bit-mask */
Michael J. Spencer 2:1df0b61d3b5a 164 #define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
Michael J. Spencer 2:1df0b61d3b5a 165
Michael J. Spencer 2:1df0b61d3b5a 166 /***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 167 * Macro defines for SPI Test Control Register
Michael J. Spencer 2:1df0b61d3b5a 168 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 169 /** SPI Test bit */
Michael J. Spencer 2:1df0b61d3b5a 170 #define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
Michael J. Spencer 2:1df0b61d3b5a 171 /** SPI Test register bit mask */
Michael J. Spencer 2:1df0b61d3b5a 172 #define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
Michael J. Spencer 2:1df0b61d3b5a 173
Michael J. Spencer 2:1df0b61d3b5a 174 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 175 * Macro defines for SPI Test Status Register
Michael J. Spencer 2:1df0b61d3b5a 176 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 177 /** Slave abort */
Michael J. Spencer 2:1df0b61d3b5a 178 #define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 179 /** Mode fault */
Michael J. Spencer 2:1df0b61d3b5a 180 #define SPI_SPTSR_MODF ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 181 /** Read overrun */
Michael J. Spencer 2:1df0b61d3b5a 182 #define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
Michael J. Spencer 2:1df0b61d3b5a 183 /** Write collision */
Michael J. Spencer 2:1df0b61d3b5a 184 #define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
Michael J. Spencer 2:1df0b61d3b5a 185 /** SPI transfer complete flag */
Michael J. Spencer 2:1df0b61d3b5a 186 #define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
Michael J. Spencer 2:1df0b61d3b5a 187 /** SPI Status bit mask */
Michael J. Spencer 2:1df0b61d3b5a 188 #define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
Michael J. Spencer 2:1df0b61d3b5a 189
Michael J. Spencer 2:1df0b61d3b5a 190 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 191 * Macro defines for SPI Interrupt Register
Michael J. Spencer 2:1df0b61d3b5a 192 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 193 /** SPI interrupt flag */
Michael J. Spencer 2:1df0b61d3b5a 194 #define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 195 /** SPI interrupt register bit mask */
Michael J. Spencer 2:1df0b61d3b5a 196 #define SPI_SPINT_BITMASK ((uint32_t)(0x01))
Michael J. Spencer 2:1df0b61d3b5a 197
Michael J. Spencer 2:1df0b61d3b5a 198
Michael J. Spencer 2:1df0b61d3b5a 199 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 200 /** Macro to determine if it is valid SPI port number */
Michael J. Spencer 2:1df0b61d3b5a 201 #define PARAM_SPIx(n) (((uint32_t *)n)==((uint32_t *)LPC_SPI))
Michael J. Spencer 2:1df0b61d3b5a 202
Michael J. Spencer 2:1df0b61d3b5a 203 /** Macro check Clock phase control mode */
Michael J. Spencer 2:1df0b61d3b5a 204 #define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) || (n==SPI_CPHA_SECOND))
Michael J. Spencer 2:1df0b61d3b5a 205
Michael J. Spencer 2:1df0b61d3b5a 206 /** Macro check Clock polarity control mode */
Michael J. Spencer 2:1df0b61d3b5a 207 #define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) || (n==SPI_CPOL_LO))
Michael J. Spencer 2:1df0b61d3b5a 208
Michael J. Spencer 2:1df0b61d3b5a 209 /** Macro check master/slave mode */
Michael J. Spencer 2:1df0b61d3b5a 210 #define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) || (n==SPI_MASTER_MODE))
Michael J. Spencer 2:1df0b61d3b5a 211
Michael J. Spencer 2:1df0b61d3b5a 212 /** Macro check LSB/MSB mode */
Michael J. Spencer 2:1df0b61d3b5a 213 #define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) || (n==SPI_DATA_LSB_FIRST))
Michael J. Spencer 2:1df0b61d3b5a 214
Michael J. Spencer 2:1df0b61d3b5a 215 /** Macro check databit value */
Michael J. Spencer 2:1df0b61d3b5a 216 #define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) || (n==SPI_DATABIT_8) \
Michael J. Spencer 2:1df0b61d3b5a 217 || (n==SPI_DATABIT_9) || (n==SPI_DATABIT_10) \
Michael J. Spencer 2:1df0b61d3b5a 218 || (n==SPI_DATABIT_11) || (n==SPI_DATABIT_12) \
Michael J. Spencer 2:1df0b61d3b5a 219 || (n==SPI_DATABIT_13) || (n==SPI_DATABIT_14) \
Michael J. Spencer 2:1df0b61d3b5a 220 || (n==SPI_DATABIT_15))
Michael J. Spencer 2:1df0b61d3b5a 221
Michael J. Spencer 2:1df0b61d3b5a 222 /** Macro check status flag */
Michael J. Spencer 2:1df0b61d3b5a 223 #define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) || (n==SPI_STAT_MODF) \
Michael J. Spencer 2:1df0b61d3b5a 224 || (n==SPI_STAT_ROVR) || (n==SPI_STAT_WCOL) \
Michael J. Spencer 2:1df0b61d3b5a 225 || (n==SPI_STAT_SPIF))
Michael J. Spencer 2:1df0b61d3b5a 226
Michael J. Spencer 2:1df0b61d3b5a 227 /**
Michael J. Spencer 2:1df0b61d3b5a 228 * @}
Michael J. Spencer 2:1df0b61d3b5a 229 */
Michael J. Spencer 2:1df0b61d3b5a 230
Michael J. Spencer 2:1df0b61d3b5a 231
Michael J. Spencer 2:1df0b61d3b5a 232 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 233 /** @defgroup SPI_Public_Types SPI Public Types
Michael J. Spencer 2:1df0b61d3b5a 234 * @{
Michael J. Spencer 2:1df0b61d3b5a 235 */
Michael J. Spencer 2:1df0b61d3b5a 236
Michael J. Spencer 2:1df0b61d3b5a 237 /** @brief SPI configuration structure */
Michael J. Spencer 2:1df0b61d3b5a 238 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 239 uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
Michael J. Spencer 2:1df0b61d3b5a 240 where x is in range from 8 - 16 */
Michael J. Spencer 2:1df0b61d3b5a 241 uint32_t CPHA; /** Clock phase, should be:
Michael J. Spencer 2:1df0b61d3b5a 242 - SPI_CPHA_FIRST: first clock edge
Michael J. Spencer 2:1df0b61d3b5a 243 - SPI_CPHA_SECOND: second clock edge */
Michael J. Spencer 2:1df0b61d3b5a 244 uint32_t CPOL; /** Clock polarity, should be:
Michael J. Spencer 2:1df0b61d3b5a 245 - SPI_CPOL_HI: high level
Michael J. Spencer 2:1df0b61d3b5a 246 - SPI_CPOL_LO: low level */
Michael J. Spencer 2:1df0b61d3b5a 247 uint32_t Mode; /** SPI mode, should be:
Michael J. Spencer 2:1df0b61d3b5a 248 - SPI_MASTER_MODE: Master mode
Michael J. Spencer 2:1df0b61d3b5a 249 - SPI_SLAVE_MODE: Slave mode */
Michael J. Spencer 2:1df0b61d3b5a 250 uint32_t DataOrder; /** Data order, should be:
Michael J. Spencer 2:1df0b61d3b5a 251 - SPI_DATA_MSB_FIRST: MSB first
Michael J. Spencer 2:1df0b61d3b5a 252 - SPI_DATA_LSB_FIRST: LSB first */
Michael J. Spencer 2:1df0b61d3b5a 253 uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
Michael J. Spencer 2:1df0b61d3b5a 254 (SPI peripheral clock)/8 */
Michael J. Spencer 2:1df0b61d3b5a 255 } SPI_CFG_Type;
Michael J. Spencer 2:1df0b61d3b5a 256
Michael J. Spencer 2:1df0b61d3b5a 257
Michael J. Spencer 2:1df0b61d3b5a 258 /**
Michael J. Spencer 2:1df0b61d3b5a 259 * @brief SPI Transfer Type definitions
Michael J. Spencer 2:1df0b61d3b5a 260 */
Michael J. Spencer 2:1df0b61d3b5a 261 typedef enum {
Michael J. Spencer 2:1df0b61d3b5a 262 SPI_TRANSFER_POLLING = 0, /**< Polling transfer */
Michael J. Spencer 2:1df0b61d3b5a 263 SPI_TRANSFER_INTERRUPT /**< Interrupt transfer */
Michael J. Spencer 2:1df0b61d3b5a 264 } SPI_TRANSFER_Type;
Michael J. Spencer 2:1df0b61d3b5a 265
Michael J. Spencer 2:1df0b61d3b5a 266 /**
Michael J. Spencer 2:1df0b61d3b5a 267 * @brief SPI Data configuration structure definitions
Michael J. Spencer 2:1df0b61d3b5a 268 */
Michael J. Spencer 2:1df0b61d3b5a 269 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 270 void *tx_data; /**< Pointer to transmit data */
Michael J. Spencer 2:1df0b61d3b5a 271 void *rx_data; /**< Pointer to transmit data */
Michael J. Spencer 2:1df0b61d3b5a 272 uint32_t length; /**< Length of transfer data */
Michael J. Spencer 2:1df0b61d3b5a 273 uint32_t counter; /**< Data counter index */
Michael J. Spencer 2:1df0b61d3b5a 274 uint32_t status; /**< Current status of SPI activity */
Michael J. Spencer 2:1df0b61d3b5a 275 } SPI_DATA_SETUP_Type;
Michael J. Spencer 2:1df0b61d3b5a 276
Michael J. Spencer 2:1df0b61d3b5a 277 /**
Michael J. Spencer 2:1df0b61d3b5a 278 * @}
Michael J. Spencer 2:1df0b61d3b5a 279 */
Michael J. Spencer 2:1df0b61d3b5a 280
Michael J. Spencer 2:1df0b61d3b5a 281
Michael J. Spencer 2:1df0b61d3b5a 282 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 283 /** @defgroup SPI_Public_Functions SPI Public Functions
Michael J. Spencer 2:1df0b61d3b5a 284 * @{
Michael J. Spencer 2:1df0b61d3b5a 285 */
Michael J. Spencer 2:1df0b61d3b5a 286
Michael J. Spencer 2:1df0b61d3b5a 287 /* SPI Init/DeInit functions ---------*/
Michael J. Spencer 2:1df0b61d3b5a 288 void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct);
Michael J. Spencer 2:1df0b61d3b5a 289 void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 290 void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
Michael J. Spencer 2:1df0b61d3b5a 291 void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
Michael J. Spencer 2:1df0b61d3b5a 292
Michael J. Spencer 2:1df0b61d3b5a 293 /* SPI transfer functions ------------*/
Michael J. Spencer 2:1df0b61d3b5a 294 void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
Michael J. Spencer 2:1df0b61d3b5a 295 uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 296 int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, SPI_TRANSFER_Type xfType);
Michael J. Spencer 2:1df0b61d3b5a 297
Michael J. Spencer 2:1df0b61d3b5a 298 /* SPI Interrupt functions ---------*/
Michael J. Spencer 2:1df0b61d3b5a 299 void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 300 IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 301 void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 302
Michael J. Spencer 2:1df0b61d3b5a 303 /* SPI get information functions-----*/
Michael J. Spencer 2:1df0b61d3b5a 304 uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 305 uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
Michael J. Spencer 2:1df0b61d3b5a 306 FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
Michael J. Spencer 2:1df0b61d3b5a 307
Michael J. Spencer 2:1df0b61d3b5a 308 /**
Michael J. Spencer 2:1df0b61d3b5a 309 * @}
Michael J. Spencer 2:1df0b61d3b5a 310 */
Michael J. Spencer 2:1df0b61d3b5a 311
Michael J. Spencer 2:1df0b61d3b5a 312 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 313 }
Michael J. Spencer 2:1df0b61d3b5a 314 #endif
Michael J. Spencer 2:1df0b61d3b5a 315
Michael J. Spencer 2:1df0b61d3b5a 316 #endif /* LPC17XX_SPI_H_ */
Michael J. Spencer 2:1df0b61d3b5a 317
Michael J. Spencer 2:1df0b61d3b5a 318 /**
Michael J. Spencer 2:1df0b61d3b5a 319 * @}
Michael J. Spencer 2:1df0b61d3b5a 320 */
Michael J. Spencer 2:1df0b61d3b5a 321
Michael J. Spencer 2:1df0b61d3b5a 322 /* --------------------------------- End Of File ------------------------------ */