Martin Olejar / Mbed 2 deprecated FRDM_MFRC522

MFRC522 example project for FRDM

Dependencies:   MFRC522 mbed

MFRC522.h@0:1d9c7c0b5015, 2013-12-14 (annotated)

Committer:
AtomX
Date:
Sat Dec 14 21:41:08 2013 +0000
Revision:
0:1d9c7c0b5015
Created MFRC522 project

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AtomX 0:1d9c7c0b5015 1 /**
AtomX 0:1d9c7c0b5015 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
AtomX 0:1d9c7c0b5015 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
AtomX 0:1d9c7c0b5015 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
AtomX 0:1d9c7c0b5015 5 * Rewritten by S�ren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
AtomX 0:1d9c7c0b5015 6 * Ported by Martin Olejar to mbed, Dec, 2013
AtomX 0:1d9c7c0b5015 7 *
AtomX 0:1d9c7c0b5015 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
AtomX 0:1d9c7c0b5015 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
AtomX 0:1d9c7c0b5015 10 *
AtomX 0:1d9c7c0b5015 11 * There are three hardware components involved:
AtomX 0:1d9c7c0b5015 12 * 1) The micro controller: An Arduino
AtomX 0:1d9c7c0b5015 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
AtomX 0:1d9c7c0b5015 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
AtomX 0:1d9c7c0b5015 15 *
AtomX 0:1d9c7c0b5015 16 * The microcontroller and card reader uses SPI for communication.
AtomX 0:1d9c7c0b5015 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
AtomX 0:1d9c7c0b5015 18 *
AtomX 0:1d9c7c0b5015 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
AtomX 0:1d9c7c0b5015 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
AtomX 0:1d9c7c0b5015 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
AtomX 0:1d9c7c0b5015 22 * Details are found in chapter 6, Type A � Initialization and anticollision.
AtomX 0:1d9c7c0b5015 23 *
AtomX 0:1d9c7c0b5015 24 * If only the PICC UID is wanted, the above documents has all the needed information.
AtomX 0:1d9c7c0b5015 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
AtomX 0:1d9c7c0b5015 26 * The MIFARE Classic chips and protocol is described in the datasheets:
AtomX 0:1d9c7c0b5015 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
AtomX 0:1d9c7c0b5015 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
AtomX 0:1d9c7c0b5015 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
AtomX 0:1d9c7c0b5015 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
AtomX 0:1d9c7c0b5015 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
AtomX 0:1d9c7c0b5015 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
AtomX 0:1d9c7c0b5015 33 *
AtomX 0:1d9c7c0b5015 34 * MIFARE Classic 1K (MF1S503x):
AtomX 0:1d9c7c0b5015 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
AtomX 0:1d9c7c0b5015 36 * The blocks are numbered 0-63.
AtomX 0:1d9c7c0b5015 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
AtomX 0:1d9c7c0b5015 38 * Bytes 0-5: Key A
AtomX 0:1d9c7c0b5015 39 * Bytes 6-8: Access Bits
AtomX 0:1d9c7c0b5015 40 * Bytes 9: User data
AtomX 0:1d9c7c0b5015 41 * Bytes 10-15: Key B (or user data)
AtomX 0:1d9c7c0b5015 42 * Block 0 is read only manufacturer data.
AtomX 0:1d9c7c0b5015 43 * To access a block, an authentication using a key from the block's sector must be performed first.
AtomX 0:1d9c7c0b5015 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
AtomX 0:1d9c7c0b5015 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX 0:1d9c7c0b5015 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
AtomX 0:1d9c7c0b5015 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
AtomX 0:1d9c7c0b5015 48 * MIFARE Classic 4K (MF1S703x):
AtomX 0:1d9c7c0b5015 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
AtomX 0:1d9c7c0b5015 50 * The blocks are numbered 0-255.
AtomX 0:1d9c7c0b5015 51 * The last block in each sector is the Sector Trailer like above.
AtomX 0:1d9c7c0b5015 52 * MIFARE Classic Mini (MF1 IC S20):
AtomX 0:1d9c7c0b5015 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
AtomX 0:1d9c7c0b5015 54 * The blocks are numbered 0-19.
AtomX 0:1d9c7c0b5015 55 * The last block in each sector is the Sector Trailer like above.
AtomX 0:1d9c7c0b5015 56 *
AtomX 0:1d9c7c0b5015 57 * MIFARE Ultralight (MF0ICU1):
AtomX 0:1d9c7c0b5015 58 * Has 16 pages of 4 bytes = 64 bytes.
AtomX 0:1d9c7c0b5015 59 * Pages 0 + 1 is used for the 7-byte UID.
AtomX 0:1d9c7c0b5015 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX 0:1d9c7c0b5015 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX 0:1d9c7c0b5015 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
AtomX 0:1d9c7c0b5015 63 * MIFARE Ultralight C (MF0ICU2):
AtomX 0:1d9c7c0b5015 64 * Has 48 pages of 4 bytes = 64 bytes.
AtomX 0:1d9c7c0b5015 65 * Pages 0 + 1 is used for the 7-byte UID.
AtomX 0:1d9c7c0b5015 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
AtomX 0:1d9c7c0b5015 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
AtomX 0:1d9c7c0b5015 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
AtomX 0:1d9c7c0b5015 69 * Page 40 Lock bytes
AtomX 0:1d9c7c0b5015 70 * Page 41 16 bit one way counter
AtomX 0:1d9c7c0b5015 71 * Pages 42-43 Authentication configuration
AtomX 0:1d9c7c0b5015 72 * Pages 44-47 Authentication key
AtomX 0:1d9c7c0b5015 73 */
AtomX 0:1d9c7c0b5015 74 #ifndef MFRC522_h
AtomX 0:1d9c7c0b5015 75 #define MFRC522_h
AtomX 0:1d9c7c0b5015 76
AtomX 0:1d9c7c0b5015 77 #include <string>
AtomX 0:1d9c7c0b5015 78 #include "mbed.h"
AtomX 0:1d9c7c0b5015 79
AtomX 0:1d9c7c0b5015 80 class MFRC522 {
AtomX 0:1d9c7c0b5015 81 public:
AtomX 0:1d9c7c0b5015 82
AtomX 0:1d9c7c0b5015 83 // MFRC522 registers. Described in chapter 9 of the datasheet.
AtomX 0:1d9c7c0b5015 84 // When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
AtomX 0:1d9c7c0b5015 85 enum PCD_Register {
AtomX 0:1d9c7c0b5015 86 // Page 0: Command and status
AtomX 0:1d9c7c0b5015 87 // 0x00 // reserved for future use
AtomX 0:1d9c7c0b5015 88 CommandReg = 0x01 << 1, // starts and stops command execution
AtomX 0:1d9c7c0b5015 89 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
AtomX 0:1d9c7c0b5015 90 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
AtomX 0:1d9c7c0b5015 91 ComIrqReg = 0x04 << 1, // interrupt request bits
AtomX 0:1d9c7c0b5015 92 DivIrqReg = 0x05 << 1, // interrupt request bits
AtomX 0:1d9c7c0b5015 93 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
AtomX 0:1d9c7c0b5015 94 Status1Reg = 0x07 << 1, // communication status bits
AtomX 0:1d9c7c0b5015 95 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
AtomX 0:1d9c7c0b5015 96 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
AtomX 0:1d9c7c0b5015 97 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
AtomX 0:1d9c7c0b5015 98 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
AtomX 0:1d9c7c0b5015 99 ControlReg = 0x0C << 1, // miscellaneous control registers
AtomX 0:1d9c7c0b5015 100 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
AtomX 0:1d9c7c0b5015 101 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
AtomX 0:1d9c7c0b5015 102 // 0x0F // reserved for future use
AtomX 0:1d9c7c0b5015 103
AtomX 0:1d9c7c0b5015 104 // Page 1:Command
AtomX 0:1d9c7c0b5015 105 // 0x10 // reserved for future use
AtomX 0:1d9c7c0b5015 106 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
AtomX 0:1d9c7c0b5015 107 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
AtomX 0:1d9c7c0b5015 108 RxModeReg = 0x13 << 1, // defines reception data rate and framing
AtomX 0:1d9c7c0b5015 109 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
AtomX 0:1d9c7c0b5015 110 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
AtomX 0:1d9c7c0b5015 111 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
AtomX 0:1d9c7c0b5015 112 RxSelReg = 0x17 << 1, // selects internal receiver settings
AtomX 0:1d9c7c0b5015 113 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
AtomX 0:1d9c7c0b5015 114 DemodReg = 0x19 << 1, // defines demodulator settings
AtomX 0:1d9c7c0b5015 115 // 0x1A // reserved for future use
AtomX 0:1d9c7c0b5015 116 // 0x1B // reserved for future use
AtomX 0:1d9c7c0b5015 117 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
AtomX 0:1d9c7c0b5015 118 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
AtomX 0:1d9c7c0b5015 119 // 0x1E // reserved for future use
AtomX 0:1d9c7c0b5015 120 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
AtomX 0:1d9c7c0b5015 121
AtomX 0:1d9c7c0b5015 122 // Page 2: Configuration
AtomX 0:1d9c7c0b5015 123 // 0x20 // reserved for future use
AtomX 0:1d9c7c0b5015 124 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
AtomX 0:1d9c7c0b5015 125 CRCResultRegL = 0x22 << 1,
AtomX 0:1d9c7c0b5015 126 // 0x23 // reserved for future use
AtomX 0:1d9c7c0b5015 127 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
AtomX 0:1d9c7c0b5015 128 // 0x25 // reserved for future use
AtomX 0:1d9c7c0b5015 129 RFCfgReg = 0x26 << 1, // configures the receiver gain
AtomX 0:1d9c7c0b5015 130 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
AtomX 0:1d9c7c0b5015 131 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
AtomX 0:1d9c7c0b5015 132 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
AtomX 0:1d9c7c0b5015 133 TModeReg = 0x2A << 1, // defines settings for the internal timer
AtomX 0:1d9c7c0b5015 134 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
AtomX 0:1d9c7c0b5015 135 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
AtomX 0:1d9c7c0b5015 136 TReloadRegL = 0x2D << 1,
AtomX 0:1d9c7c0b5015 137 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
AtomX 0:1d9c7c0b5015 138 TCntValueRegL = 0x2F << 1,
AtomX 0:1d9c7c0b5015 139
AtomX 0:1d9c7c0b5015 140 // Page 3:Test Registers
AtomX 0:1d9c7c0b5015 141 // 0x30 // reserved for future use
AtomX 0:1d9c7c0b5015 142 TestSel1Reg = 0x31 << 1, // general test signal configuration
AtomX 0:1d9c7c0b5015 143 TestSel2Reg = 0x32 << 1, // general test signal configuration
AtomX 0:1d9c7c0b5015 144 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
AtomX 0:1d9c7c0b5015 145 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
AtomX 0:1d9c7c0b5015 146 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
AtomX 0:1d9c7c0b5015 147 AutoTestReg = 0x36 << 1, // controls the digital self test
AtomX 0:1d9c7c0b5015 148 VersionReg = 0x37 << 1, // shows the software version
AtomX 0:1d9c7c0b5015 149 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
AtomX 0:1d9c7c0b5015 150 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
AtomX 0:1d9c7c0b5015 151 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
AtomX 0:1d9c7c0b5015 152 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
AtomX 0:1d9c7c0b5015 153 // 0x3C // reserved for production tests
AtomX 0:1d9c7c0b5015 154 // 0x3D // reserved for production tests
AtomX 0:1d9c7c0b5015 155 // 0x3E // reserved for production tests
AtomX 0:1d9c7c0b5015 156 // 0x3F // reserved for production tests
AtomX 0:1d9c7c0b5015 157 };
AtomX 0:1d9c7c0b5015 158
AtomX 0:1d9c7c0b5015 159 // MFRC522 commands Described in chapter 10 of the datasheet.
AtomX 0:1d9c7c0b5015 160 enum PCD_Command {
AtomX 0:1d9c7c0b5015 161 PCD_Idle = 0x00, // no action, cancels current command execution
AtomX 0:1d9c7c0b5015 162 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
AtomX 0:1d9c7c0b5015 163 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
AtomX 0:1d9c7c0b5015 164 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
AtomX 0:1d9c7c0b5015 165 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
AtomX 0:1d9c7c0b5015 166 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
AtomX 0:1d9c7c0b5015 167 PCD_Receive = 0x08, // activates the receiver circuits
AtomX 0:1d9c7c0b5015 168 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
AtomX 0:1d9c7c0b5015 169 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
AtomX 0:1d9c7c0b5015 170 PCD_SoftReset = 0x0F // resets the MFRC522
AtomX 0:1d9c7c0b5015 171 };
AtomX 0:1d9c7c0b5015 172
AtomX 0:1d9c7c0b5015 173 // Commands sent to the PICC.
AtomX 0:1d9c7c0b5015 174 enum PICC_Command {
AtomX 0:1d9c7c0b5015 175 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
AtomX 0:1d9c7c0b5015 176 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX 0:1d9c7c0b5015 177 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX 0:1d9c7c0b5015 178 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
AtomX 0:1d9c7c0b5015 179 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
AtomX 0:1d9c7c0b5015 180 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
AtomX 0:1d9c7c0b5015 181 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
AtomX 0:1d9c7c0b5015 182 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
AtomX 0:1d9c7c0b5015 183 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
AtomX 0:1d9c7c0b5015 184 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
AtomX 0:1d9c7c0b5015 185 // The read/write commands can also be used for MIFARE Ultralight.
AtomX 0:1d9c7c0b5015 186 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
AtomX 0:1d9c7c0b5015 187 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
AtomX 0:1d9c7c0b5015 188 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
AtomX 0:1d9c7c0b5015 189 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
AtomX 0:1d9c7c0b5015 190 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
AtomX 0:1d9c7c0b5015 191 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
AtomX 0:1d9c7c0b5015 192 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
AtomX 0:1d9c7c0b5015 193 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
AtomX 0:1d9c7c0b5015 194 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
AtomX 0:1d9c7c0b5015 195 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
AtomX 0:1d9c7c0b5015 196 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
AtomX 0:1d9c7c0b5015 197 };
AtomX 0:1d9c7c0b5015 198
AtomX 0:1d9c7c0b5015 199 // MIFARE constants that does not fit anywhere else
AtomX 0:1d9c7c0b5015 200 enum MIFARE_Misc {
AtomX 0:1d9c7c0b5015 201 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
AtomX 0:1d9c7c0b5015 202 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
AtomX 0:1d9c7c0b5015 203 };
AtomX 0:1d9c7c0b5015 204
AtomX 0:1d9c7c0b5015 205 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
AtomX 0:1d9c7c0b5015 206 enum PICC_Type {
AtomX 0:1d9c7c0b5015 207 PICC_TYPE_UNKNOWN = 0,
AtomX 0:1d9c7c0b5015 208 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
AtomX 0:1d9c7c0b5015 209 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
AtomX 0:1d9c7c0b5015 210 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
AtomX 0:1d9c7c0b5015 211 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
AtomX 0:1d9c7c0b5015 212 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
AtomX 0:1d9c7c0b5015 213 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
AtomX 0:1d9c7c0b5015 214 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
AtomX 0:1d9c7c0b5015 215 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
AtomX 0:1d9c7c0b5015 216 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
AtomX 0:1d9c7c0b5015 217 };
AtomX 0:1d9c7c0b5015 218
AtomX 0:1d9c7c0b5015 219 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
AtomX 0:1d9c7c0b5015 220 enum StatusCode {
AtomX 0:1d9c7c0b5015 221 STATUS_OK = 1, // Success
AtomX 0:1d9c7c0b5015 222 STATUS_ERROR = 2, // Error in communication
AtomX 0:1d9c7c0b5015 223 STATUS_COLLISION = 3, // Collision detected
AtomX 0:1d9c7c0b5015 224 STATUS_TIMEOUT = 4, // Timeout in communication.
AtomX 0:1d9c7c0b5015 225 STATUS_NO_ROOM = 5, // A buffer is not big enough.
AtomX 0:1d9c7c0b5015 226 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
AtomX 0:1d9c7c0b5015 227 STATUS_INVALID = 7, // Invalid argument.
AtomX 0:1d9c7c0b5015 228 STATUS_CRC_WRONG = 8, // The CRC_A does not match
AtomX 0:1d9c7c0b5015 229 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
AtomX 0:1d9c7c0b5015 230 };
AtomX 0:1d9c7c0b5015 231
AtomX 0:1d9c7c0b5015 232 // A struct used for passing the UID of a PICC.
AtomX 0:1d9c7c0b5015 233 typedef struct {
AtomX 0:1d9c7c0b5015 234 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
AtomX 0:1d9c7c0b5015 235 uint8_t uidByte[10];
AtomX 0:1d9c7c0b5015 236 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
AtomX 0:1d9c7c0b5015 237 } Uid;
AtomX 0:1d9c7c0b5015 238
AtomX 0:1d9c7c0b5015 239 // A struct used for passing a MIFARE Crypto1 key
AtomX 0:1d9c7c0b5015 240 typedef struct {
AtomX 0:1d9c7c0b5015 241 uint8_t keyByte[MF_KEY_SIZE];
AtomX 0:1d9c7c0b5015 242 } MIFARE_Key;
AtomX 0:1d9c7c0b5015 243
AtomX 0:1d9c7c0b5015 244 // Member variables
AtomX 0:1d9c7c0b5015 245 Uid uid; // Used by PICC_ReadCardSerial().
AtomX 0:1d9c7c0b5015 246
AtomX 0:1d9c7c0b5015 247 // Size of the MFRC522 FIFO
AtomX 0:1d9c7c0b5015 248 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
AtomX 0:1d9c7c0b5015 249
AtomX 0:1d9c7c0b5015 250 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 251 // Functions for setting up the driver
AtomX 0:1d9c7c0b5015 252 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 253 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
AtomX 0:1d9c7c0b5015 254
AtomX 0:1d9c7c0b5015 255 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 256 // Functions for manipulating the MFRC522
AtomX 0:1d9c7c0b5015 257 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 258 void PCD_Init();
AtomX 0:1d9c7c0b5015 259 void PCD_Reset();
AtomX 0:1d9c7c0b5015 260 void PCD_AntennaOn();
AtomX 0:1d9c7c0b5015 261
AtomX 0:1d9c7c0b5015 262 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 263 // Basic interface functions for communicating with the MFRC522
AtomX 0:1d9c7c0b5015 264 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 265 void PCD_WriteRegister(uint8_t reg, uint8_t value);
AtomX 0:1d9c7c0b5015 266 void PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values);
AtomX 0:1d9c7c0b5015 267 uint8_t PCD_ReadRegister(uint8_t reg);
AtomX 0:1d9c7c0b5015 268 void PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
AtomX 0:1d9c7c0b5015 269 void PCD_SetRegisterBitMask(uint8_t reg, uint8_t mask);
AtomX 0:1d9c7c0b5015 270 void PCD_ClearRegisterBitMask(uint8_t reg, uint8_t mask);
AtomX 0:1d9c7c0b5015 271 uint8_t PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result);
AtomX 0:1d9c7c0b5015 272
AtomX 0:1d9c7c0b5015 273 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 274 // Functions for communicating with PICCs
AtomX 0:1d9c7c0b5015 275 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 276 uint8_t PCD_TransceiveData(uint8_t *sendData, uint8_t sendLen, uint8_t *backData, uint8_t *backLen, uint8_t *validBits = NULL, uint8_t rxAlign = 0, bool checkCRC = false);
AtomX 0:1d9c7c0b5015 277 uint8_t PCD_CommunicateWithPICC(uint8_t command, uint8_t waitIRq, uint8_t *sendData, uint8_t sendLen, uint8_t *backData = NULL, uint8_t *backLen = NULL, uint8_t *validBits = NULL, uint8_t rxAlign = 0, bool checkCRC = false);
AtomX 0:1d9c7c0b5015 278
AtomX 0:1d9c7c0b5015 279 uint8_t PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 0:1d9c7c0b5015 280 uint8_t PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 0:1d9c7c0b5015 281 uint8_t PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
AtomX 0:1d9c7c0b5015 282 uint8_t PICC_Select(Uid *uid, uint8_t validBits = 0);
AtomX 0:1d9c7c0b5015 283 uint8_t PICC_HaltA();
AtomX 0:1d9c7c0b5015 284
AtomX 0:1d9c7c0b5015 285 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 286 // Functions for communicating with MIFARE PICCs
AtomX 0:1d9c7c0b5015 287 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 288 uint8_t PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
AtomX 0:1d9c7c0b5015 289 void PCD_StopCrypto1();
AtomX 0:1d9c7c0b5015 290 uint8_t MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
AtomX 0:1d9c7c0b5015 291 uint8_t MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
AtomX 0:1d9c7c0b5015 292 uint8_t MIFARE_Decrement(uint8_t blockAddr, uint32_t delta);
AtomX 0:1d9c7c0b5015 293 uint8_t MIFARE_Increment(uint8_t blockAddr, uint32_t delta);
AtomX 0:1d9c7c0b5015 294 uint8_t MIFARE_Restore(uint8_t blockAddr);
AtomX 0:1d9c7c0b5015 295 uint8_t MIFARE_Transfer(uint8_t blockAddr);
AtomX 0:1d9c7c0b5015 296 uint8_t MIFARE_Ultralight_Write(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
AtomX 0:1d9c7c0b5015 297
AtomX 0:1d9c7c0b5015 298 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 299 // Support functions
AtomX 0:1d9c7c0b5015 300 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 301 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
AtomX 0:1d9c7c0b5015 302 uint8_t PICC_GetType(uint8_t sak);
AtomX 0:1d9c7c0b5015 303 std::string PICC_GetTypeName(uint8_t type);
AtomX 0:1d9c7c0b5015 304 std::string GetStatusCodeName(uint8_t code);
AtomX 0:1d9c7c0b5015 305 void MIFARE_SetAccessBits(uint8_t *accessBitBuffer, uint8_t g0, uint8_t g1, uint8_t g2, uint8_t g3);
AtomX 0:1d9c7c0b5015 306
AtomX 0:1d9c7c0b5015 307 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 308 // Convenience functions - does not add extra functionality
AtomX 0:1d9c7c0b5015 309 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 310 bool PICC_IsNewCardPresent();
AtomX 0:1d9c7c0b5015 311 bool PICC_ReadCardSerial();
AtomX 0:1d9c7c0b5015 312
AtomX 0:1d9c7c0b5015 313 private:
AtomX 0:1d9c7c0b5015 314 SPI m_SPI;
AtomX 0:1d9c7c0b5015 315 DigitalOut m_CS;
AtomX 0:1d9c7c0b5015 316 DigitalOut m_RESET;
AtomX 0:1d9c7c0b5015 317
AtomX 0:1d9c7c0b5015 318 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
AtomX 0:1d9c7c0b5015 319 };
AtomX 0:1d9c7c0b5015 320
AtomX 0:1d9c7c0b5015 321 #endif