_hw_usb_endptn Union Reference

HW_USB_ENDPTn - Endpoint Control register (RW) More...

#include <MK64F12_usb.h>

Detailed Description

HW_USB_ENDPTn - Endpoint Control register (RW)

Reset value: 0x00U

Contains the endpoint control bits for each of the 16 endpoints available within the USB module for a decoded address. The format for these registers is shown in the following figure. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required for all USB functions. Therefore, after a USBRST interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and EPTXEN define if an endpoint is enabled and define the direction of the endpoint. The endpoint enable/direction control is defined in the following table. Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP) transfers.

Definition at line 2814 of file MK64F12_usb.h.