MK64F12_usb.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_USB_REGISTERS_H__
00088 #define __HW_USB_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 USB
00095  *
00096  * Universal Serial Bus, OTG Capable Controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_USB_PERID - Peripheral ID register
00100  * - HW_USB_IDCOMP - Peripheral ID Complement register
00101  * - HW_USB_REV - Peripheral Revision register
00102  * - HW_USB_ADDINFO - Peripheral Additional Info register
00103  * - HW_USB_OTGISTAT - OTG Interrupt Status register
00104  * - HW_USB_OTGICR - OTG Interrupt Control register
00105  * - HW_USB_OTGSTAT - OTG Status register
00106  * - HW_USB_OTGCTL - OTG Control register
00107  * - HW_USB_ISTAT - Interrupt Status register
00108  * - HW_USB_INTEN - Interrupt Enable register
00109  * - HW_USB_ERRSTAT - Error Interrupt Status register
00110  * - HW_USB_ERREN - Error Interrupt Enable register
00111  * - HW_USB_STAT - Status register
00112  * - HW_USB_CTL - Control register
00113  * - HW_USB_ADDR - Address register
00114  * - HW_USB_BDTPAGE1 - BDT Page register 1
00115  * - HW_USB_FRMNUML - Frame Number register Low
00116  * - HW_USB_FRMNUMH - Frame Number register High
00117  * - HW_USB_TOKEN - Token register
00118  * - HW_USB_SOFTHLD - SOF Threshold register
00119  * - HW_USB_BDTPAGE2 - BDT Page Register 2
00120  * - HW_USB_BDTPAGE3 - BDT Page Register 3
00121  * - HW_USB_ENDPTn - Endpoint Control register
00122  * - HW_USB_USBCTRL - USB Control register
00123  * - HW_USB_OBSERVE - USB OTG Observe register
00124  * - HW_USB_CONTROL - USB OTG Control register
00125  * - HW_USB_USBTRC0 - USB Transceiver Control register 0
00126  * - HW_USB_USBFRMADJUST - Frame Adjust Register
00127  * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
00128  * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
00129  * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
00130  *
00131  * - hw_usb_t - Struct containing all module registers.
00132  */
00133 
00134 #define HW_USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
00135 
00136 /*******************************************************************************
00137  * HW_USB_PERID - Peripheral ID register
00138  ******************************************************************************/
00139 
00140 /*!
00141  * @brief HW_USB_PERID - Peripheral ID register (RO)
00142  *
00143  * Reset value: 0x04U
00144  *
00145  * Reads back the value of 0x04. This value is defined for the USB peripheral.
00146  */
00147 typedef union _hw_usb_perid
00148 {
00149     uint8_t U;
00150     struct _hw_usb_perid_bitfields
00151     {
00152         uint8_t ID : 6;                /*!< [5:0] Peripheral Identification */
00153         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
00154     } B;
00155 } hw_usb_perid_t;
00156 
00157 /*!
00158  * @name Constants and macros for entire USB_PERID register
00159  */
00160 /*@{*/
00161 #define HW_USB_PERID_ADDR(x)     ((x) + 0x0U)
00162 
00163 #define HW_USB_PERID(x)          (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR(x))
00164 #define HW_USB_PERID_RD(x)       (ADDRESS_READ(hw_usb_perid_t, HW_USB_PERID_ADDR(x)))
00165 /*@}*/
00166 
00167 /*
00168  * Constants & macros for individual USB_PERID bitfields
00169  */
00170 
00171 /*!
00172  * @name Register USB_PERID, field ID[5:0] (RO)
00173  *
00174  * This field always reads 0x4h.
00175  */
00176 /*@{*/
00177 #define BP_USB_PERID_ID      (0U)          /*!< Bit position for USB_PERID_ID. */
00178 #define BM_USB_PERID_ID      (0x3FU)       /*!< Bit mask for USB_PERID_ID. */
00179 #define BS_USB_PERID_ID      (6U)          /*!< Bit field size in bits for USB_PERID_ID. */
00180 
00181 /*! @brief Read current value of the USB_PERID_ID field. */
00182 #define BR_USB_PERID_ID(x)   (UNION_READ(hw_usb_perid_t, HW_USB_PERID_ADDR(x), U, B.ID))
00183 /*@}*/
00184 
00185 /*******************************************************************************
00186  * HW_USB_IDCOMP - Peripheral ID Complement register
00187  ******************************************************************************/
00188 
00189 /*!
00190  * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO)
00191  *
00192  * Reset value: 0xFBU
00193  *
00194  * Reads back the complement of the Peripheral ID register. For the USB
00195  * peripheral, the value is 0xFB.
00196  */
00197 typedef union _hw_usb_idcomp
00198 {
00199     uint8_t U;
00200     struct _hw_usb_idcomp_bitfields
00201     {
00202         uint8_t NID : 6;               /*!< [5:0]  */
00203         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
00204     } B;
00205 } hw_usb_idcomp_t;
00206 
00207 /*!
00208  * @name Constants and macros for entire USB_IDCOMP register
00209  */
00210 /*@{*/
00211 #define HW_USB_IDCOMP_ADDR(x)    ((x) + 0x4U)
00212 
00213 #define HW_USB_IDCOMP(x)         (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR(x))
00214 #define HW_USB_IDCOMP_RD(x)      (ADDRESS_READ(hw_usb_idcomp_t, HW_USB_IDCOMP_ADDR(x)))
00215 /*@}*/
00216 
00217 /*
00218  * Constants & macros for individual USB_IDCOMP bitfields
00219  */
00220 
00221 /*!
00222  * @name Register USB_IDCOMP, field NID[5:0] (RO)
00223  *
00224  * Ones' complement of PERID[ID]. bits.
00225  */
00226 /*@{*/
00227 #define BP_USB_IDCOMP_NID    (0U)          /*!< Bit position for USB_IDCOMP_NID. */
00228 #define BM_USB_IDCOMP_NID    (0x3FU)       /*!< Bit mask for USB_IDCOMP_NID. */
00229 #define BS_USB_IDCOMP_NID    (6U)          /*!< Bit field size in bits for USB_IDCOMP_NID. */
00230 
00231 /*! @brief Read current value of the USB_IDCOMP_NID field. */
00232 #define BR_USB_IDCOMP_NID(x) (UNION_READ(hw_usb_idcomp_t, HW_USB_IDCOMP_ADDR(x), U, B.NID))
00233 /*@}*/
00234 
00235 /*******************************************************************************
00236  * HW_USB_REV - Peripheral Revision register
00237  ******************************************************************************/
00238 
00239 /*!
00240  * @brief HW_USB_REV - Peripheral Revision register (RO)
00241  *
00242  * Reset value: 0x33U
00243  *
00244  * Contains the revision number of the USB module.
00245  */
00246 typedef union _hw_usb_rev
00247 {
00248     uint8_t U;
00249     struct _hw_usb_rev_bitfields
00250     {
00251         uint8_t REV : 8;               /*!< [7:0] Revision */
00252     } B;
00253 } hw_usb_rev_t;
00254 
00255 /*!
00256  * @name Constants and macros for entire USB_REV register
00257  */
00258 /*@{*/
00259 #define HW_USB_REV_ADDR(x)       ((x) + 0x8U)
00260 
00261 #define HW_USB_REV(x)            (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR(x))
00262 #define HW_USB_REV_RD(x)         (ADDRESS_READ(hw_usb_rev_t, HW_USB_REV_ADDR(x)))
00263 /*@}*/
00264 
00265 /*
00266  * Constants & macros for individual USB_REV bitfields
00267  */
00268 
00269 /*!
00270  * @name Register USB_REV, field REV[7:0] (RO)
00271  *
00272  * Indicates the revision number of the USB Core.
00273  */
00274 /*@{*/
00275 #define BP_USB_REV_REV       (0U)          /*!< Bit position for USB_REV_REV. */
00276 #define BM_USB_REV_REV       (0xFFU)       /*!< Bit mask for USB_REV_REV. */
00277 #define BS_USB_REV_REV       (8U)          /*!< Bit field size in bits for USB_REV_REV. */
00278 
00279 /*! @brief Read current value of the USB_REV_REV field. */
00280 #define BR_USB_REV_REV(x)    (HW_USB_REV(x).U)
00281 /*@}*/
00282 
00283 /*******************************************************************************
00284  * HW_USB_ADDINFO - Peripheral Additional Info register
00285  ******************************************************************************/
00286 
00287 /*!
00288  * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO)
00289  *
00290  * Reset value: 0x01U
00291  *
00292  * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
00293  * the Host Enable bit.
00294  */
00295 typedef union _hw_usb_addinfo
00296 {
00297     uint8_t U;
00298     struct _hw_usb_addinfo_bitfields
00299     {
00300         uint8_t IEHOST : 1;            /*!< [0]  */
00301         uint8_t RESERVED0 : 2;         /*!< [2:1]  */
00302         uint8_t IRQNUM : 5;            /*!< [7:3] Assigned Interrupt Request Number */
00303     } B;
00304 } hw_usb_addinfo_t;
00305 
00306 /*!
00307  * @name Constants and macros for entire USB_ADDINFO register
00308  */
00309 /*@{*/
00310 #define HW_USB_ADDINFO_ADDR(x)   ((x) + 0xCU)
00311 
00312 #define HW_USB_ADDINFO(x)        (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR(x))
00313 #define HW_USB_ADDINFO_RD(x)     (ADDRESS_READ(hw_usb_addinfo_t, HW_USB_ADDINFO_ADDR(x)))
00314 /*@}*/
00315 
00316 /*
00317  * Constants & macros for individual USB_ADDINFO bitfields
00318  */
00319 
00320 /*!
00321  * @name Register USB_ADDINFO, field IEHOST[0] (RO)
00322  *
00323  * This bit is set if host mode is enabled.
00324  */
00325 /*@{*/
00326 #define BP_USB_ADDINFO_IEHOST (0U)         /*!< Bit position for USB_ADDINFO_IEHOST. */
00327 #define BM_USB_ADDINFO_IEHOST (0x01U)      /*!< Bit mask for USB_ADDINFO_IEHOST. */
00328 #define BS_USB_ADDINFO_IEHOST (1U)         /*!< Bit field size in bits for USB_ADDINFO_IEHOST. */
00329 
00330 /*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
00331 #define BR_USB_ADDINFO_IEHOST(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ADDINFO_ADDR(x), BP_USB_ADDINFO_IEHOST)))
00332 /*@}*/
00333 
00334 /*!
00335  * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
00336  */
00337 /*@{*/
00338 #define BP_USB_ADDINFO_IRQNUM (3U)         /*!< Bit position for USB_ADDINFO_IRQNUM. */
00339 #define BM_USB_ADDINFO_IRQNUM (0xF8U)      /*!< Bit mask for USB_ADDINFO_IRQNUM. */
00340 #define BS_USB_ADDINFO_IRQNUM (5U)         /*!< Bit field size in bits for USB_ADDINFO_IRQNUM. */
00341 
00342 /*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
00343 #define BR_USB_ADDINFO_IRQNUM(x) (UNION_READ(hw_usb_addinfo_t, HW_USB_ADDINFO_ADDR(x), U, B.IRQNUM))
00344 /*@}*/
00345 
00346 /*******************************************************************************
00347  * HW_USB_OTGISTAT - OTG Interrupt Status register
00348  ******************************************************************************/
00349 
00350 /*!
00351  * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW)
00352  *
00353  * Reset value: 0x00U
00354  *
00355  * Records changes of the ID sense and VBUS signals. Software can read this
00356  * register to determine the event that triggers an interrupt. Only bits that have
00357  * changed since the last software read are set. Writing a one to a bit clears the
00358  * associated interrupt.
00359  */
00360 typedef union _hw_usb_otgistat
00361 {
00362     uint8_t U;
00363     struct _hw_usb_otgistat_bitfields
00364     {
00365         uint8_t AVBUSCHG : 1;          /*!< [0]  */
00366         uint8_t RESERVED0 : 1;         /*!< [1]  */
00367         uint8_t B_SESS_CHG : 1;        /*!< [2]  */
00368         uint8_t SESSVLDCHG : 1;        /*!< [3]  */
00369         uint8_t RESERVED1 : 1;         /*!< [4]  */
00370         uint8_t LINE_STATE_CHG : 1;    /*!< [5]  */
00371         uint8_t ONEMSEC : 1;           /*!< [6]  */
00372         uint8_t IDCHG : 1;             /*!< [7]  */
00373     } B;
00374 } hw_usb_otgistat_t;
00375 
00376 /*!
00377  * @name Constants and macros for entire USB_OTGISTAT register
00378  */
00379 /*@{*/
00380 #define HW_USB_OTGISTAT_ADDR(x)  ((x) + 0x10U)
00381 
00382 #define HW_USB_OTGISTAT(x)       (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR(x))
00383 #define HW_USB_OTGISTAT_RD(x)    (ADDRESS_READ(hw_usb_otgistat_t, HW_USB_OTGISTAT_ADDR(x)))
00384 #define HW_USB_OTGISTAT_WR(x, v) (ADDRESS_WRITE(hw_usb_otgistat_t, HW_USB_OTGISTAT_ADDR(x), v))
00385 #define HW_USB_OTGISTAT_SET(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) |  (v)))
00386 #define HW_USB_OTGISTAT_CLR(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) & ~(v)))
00387 #define HW_USB_OTGISTAT_TOG(x, v) (HW_USB_OTGISTAT_WR(x, HW_USB_OTGISTAT_RD(x) ^  (v)))
00388 /*@}*/
00389 
00390 /*
00391  * Constants & macros for individual USB_OTGISTAT bitfields
00392  */
00393 
00394 /*!
00395  * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
00396  *
00397  * This bit is set when a change in VBUS is detected on an A device.
00398  */
00399 /*@{*/
00400 #define BP_USB_OTGISTAT_AVBUSCHG (0U)      /*!< Bit position for USB_OTGISTAT_AVBUSCHG. */
00401 #define BM_USB_OTGISTAT_AVBUSCHG (0x01U)   /*!< Bit mask for USB_OTGISTAT_AVBUSCHG. */
00402 #define BS_USB_OTGISTAT_AVBUSCHG (1U)      /*!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG. */
00403 
00404 /*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
00405 #define BR_USB_OTGISTAT_AVBUSCHG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG)))
00406 
00407 /*! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG. */
00408 #define BF_USB_OTGISTAT_AVBUSCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_AVBUSCHG) & BM_USB_OTGISTAT_AVBUSCHG)
00409 
00410 /*! @brief Set the AVBUSCHG field to a new value. */
00411 #define BW_USB_OTGISTAT_AVBUSCHG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_AVBUSCHG), v))
00412 /*@}*/
00413 
00414 /*!
00415  * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
00416  *
00417  * This bit is set when a change in VBUS is detected on a B device.
00418  */
00419 /*@{*/
00420 #define BP_USB_OTGISTAT_B_SESS_CHG (2U)    /*!< Bit position for USB_OTGISTAT_B_SESS_CHG. */
00421 #define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) /*!< Bit mask for USB_OTGISTAT_B_SESS_CHG. */
00422 #define BS_USB_OTGISTAT_B_SESS_CHG (1U)    /*!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG. */
00423 
00424 /*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
00425 #define BR_USB_OTGISTAT_B_SESS_CHG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG)))
00426 
00427 /*! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG. */
00428 #define BF_USB_OTGISTAT_B_SESS_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_B_SESS_CHG) & BM_USB_OTGISTAT_B_SESS_CHG)
00429 
00430 /*! @brief Set the B_SESS_CHG field to a new value. */
00431 #define BW_USB_OTGISTAT_B_SESS_CHG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_B_SESS_CHG), v))
00432 /*@}*/
00433 
00434 /*!
00435  * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
00436  *
00437  * This bit is set when a change in VBUS is detected indicating a session valid
00438  * or a session no longer valid.
00439  */
00440 /*@{*/
00441 #define BP_USB_OTGISTAT_SESSVLDCHG (3U)    /*!< Bit position for USB_OTGISTAT_SESSVLDCHG. */
00442 #define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) /*!< Bit mask for USB_OTGISTAT_SESSVLDCHG. */
00443 #define BS_USB_OTGISTAT_SESSVLDCHG (1U)    /*!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG. */
00444 
00445 /*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
00446 #define BR_USB_OTGISTAT_SESSVLDCHG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG)))
00447 
00448 /*! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG. */
00449 #define BF_USB_OTGISTAT_SESSVLDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_SESSVLDCHG) & BM_USB_OTGISTAT_SESSVLDCHG)
00450 
00451 /*! @brief Set the SESSVLDCHG field to a new value. */
00452 #define BW_USB_OTGISTAT_SESSVLDCHG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_SESSVLDCHG), v))
00453 /*@}*/
00454 
00455 /*!
00456  * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
00457  *
00458  * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
00459  * are stable without change for 1 millisecond, and the value of the line state
00460  * is different from the last time when the line state was stable. It is set on
00461  * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
00462  * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
00463  * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
00464  * signaling.
00465  */
00466 /*@{*/
00467 #define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) /*!< Bit position for USB_OTGISTAT_LINE_STATE_CHG. */
00468 #define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) /*!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG. */
00469 #define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) /*!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG. */
00470 
00471 /*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
00472 #define BR_USB_OTGISTAT_LINE_STATE_CHG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG)))
00473 
00474 /*! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG. */
00475 #define BF_USB_OTGISTAT_LINE_STATE_CHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_LINE_STATE_CHG) & BM_USB_OTGISTAT_LINE_STATE_CHG)
00476 
00477 /*! @brief Set the LINE_STATE_CHG field to a new value. */
00478 #define BW_USB_OTGISTAT_LINE_STATE_CHG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_LINE_STATE_CHG), v))
00479 /*@}*/
00480 
00481 /*!
00482  * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
00483  *
00484  * This bit is set when the 1 millisecond timer expires. This bit stays asserted
00485  * until cleared by software. The interrupt must be serviced every millisecond
00486  * to avoid losing 1msec counts.
00487  */
00488 /*@{*/
00489 #define BP_USB_OTGISTAT_ONEMSEC (6U)       /*!< Bit position for USB_OTGISTAT_ONEMSEC. */
00490 #define BM_USB_OTGISTAT_ONEMSEC (0x40U)    /*!< Bit mask for USB_OTGISTAT_ONEMSEC. */
00491 #define BS_USB_OTGISTAT_ONEMSEC (1U)       /*!< Bit field size in bits for USB_OTGISTAT_ONEMSEC. */
00492 
00493 /*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
00494 #define BR_USB_OTGISTAT_ONEMSEC(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC)))
00495 
00496 /*! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC. */
00497 #define BF_USB_OTGISTAT_ONEMSEC(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_ONEMSEC) & BM_USB_OTGISTAT_ONEMSEC)
00498 
00499 /*! @brief Set the ONEMSEC field to a new value. */
00500 #define BW_USB_OTGISTAT_ONEMSEC(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_ONEMSEC), v))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
00505  *
00506  * This bit is set when a change in the ID Signal from the USB connector is
00507  * sensed.
00508  */
00509 /*@{*/
00510 #define BP_USB_OTGISTAT_IDCHG (7U)         /*!< Bit position for USB_OTGISTAT_IDCHG. */
00511 #define BM_USB_OTGISTAT_IDCHG (0x80U)      /*!< Bit mask for USB_OTGISTAT_IDCHG. */
00512 #define BS_USB_OTGISTAT_IDCHG (1U)         /*!< Bit field size in bits for USB_OTGISTAT_IDCHG. */
00513 
00514 /*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
00515 #define BR_USB_OTGISTAT_IDCHG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG)))
00516 
00517 /*! @brief Format value for bitfield USB_OTGISTAT_IDCHG. */
00518 #define BF_USB_OTGISTAT_IDCHG(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGISTAT_IDCHG) & BM_USB_OTGISTAT_IDCHG)
00519 
00520 /*! @brief Set the IDCHG field to a new value. */
00521 #define BW_USB_OTGISTAT_IDCHG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGISTAT_ADDR(x), BP_USB_OTGISTAT_IDCHG), v))
00522 /*@}*/
00523 
00524 /*******************************************************************************
00525  * HW_USB_OTGICR - OTG Interrupt Control register
00526  ******************************************************************************/
00527 
00528 /*!
00529  * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW)
00530  *
00531  * Reset value: 0x00U
00532  *
00533  * Enables the corresponding interrupt status bits defined in the OTG Interrupt
00534  * Status Register.
00535  */
00536 typedef union _hw_usb_otgicr
00537 {
00538     uint8_t U;
00539     struct _hw_usb_otgicr_bitfields
00540     {
00541         uint8_t AVBUSEN : 1;           /*!< [0] A VBUS Valid Interrupt Enable */
00542         uint8_t RESERVED0 : 1;         /*!< [1]  */
00543         uint8_t BSESSEN : 1;           /*!< [2] B Session END Interrupt Enable */
00544         uint8_t SESSVLDEN : 1;         /*!< [3] Session Valid Interrupt Enable */
00545         uint8_t RESERVED1 : 1;         /*!< [4]  */
00546         uint8_t LINESTATEEN : 1;       /*!< [5] Line State Change Interrupt Enable
00547                                         * */
00548         uint8_t ONEMSECEN : 1;         /*!< [6] One Millisecond Interrupt Enable */
00549         uint8_t IDEN : 1;              /*!< [7] ID Interrupt Enable */
00550     } B;
00551 } hw_usb_otgicr_t;
00552 
00553 /*!
00554  * @name Constants and macros for entire USB_OTGICR register
00555  */
00556 /*@{*/
00557 #define HW_USB_OTGICR_ADDR(x)    ((x) + 0x14U)
00558 
00559 #define HW_USB_OTGICR(x)         (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR(x))
00560 #define HW_USB_OTGICR_RD(x)      (ADDRESS_READ(hw_usb_otgicr_t, HW_USB_OTGICR_ADDR(x)))
00561 #define HW_USB_OTGICR_WR(x, v)   (ADDRESS_WRITE(hw_usb_otgicr_t, HW_USB_OTGICR_ADDR(x), v))
00562 #define HW_USB_OTGICR_SET(x, v)  (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) |  (v)))
00563 #define HW_USB_OTGICR_CLR(x, v)  (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) & ~(v)))
00564 #define HW_USB_OTGICR_TOG(x, v)  (HW_USB_OTGICR_WR(x, HW_USB_OTGICR_RD(x) ^  (v)))
00565 /*@}*/
00566 
00567 /*
00568  * Constants & macros for individual USB_OTGICR bitfields
00569  */
00570 
00571 /*!
00572  * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
00573  *
00574  * Values:
00575  * - 0 - Disables the AVBUSCHG interrupt.
00576  * - 1 - Enables the AVBUSCHG interrupt.
00577  */
00578 /*@{*/
00579 #define BP_USB_OTGICR_AVBUSEN (0U)         /*!< Bit position for USB_OTGICR_AVBUSEN. */
00580 #define BM_USB_OTGICR_AVBUSEN (0x01U)      /*!< Bit mask for USB_OTGICR_AVBUSEN. */
00581 #define BS_USB_OTGICR_AVBUSEN (1U)         /*!< Bit field size in bits for USB_OTGICR_AVBUSEN. */
00582 
00583 /*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
00584 #define BR_USB_OTGICR_AVBUSEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN)))
00585 
00586 /*! @brief Format value for bitfield USB_OTGICR_AVBUSEN. */
00587 #define BF_USB_OTGICR_AVBUSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_AVBUSEN) & BM_USB_OTGICR_AVBUSEN)
00588 
00589 /*! @brief Set the AVBUSEN field to a new value. */
00590 #define BW_USB_OTGICR_AVBUSEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_AVBUSEN), v))
00591 /*@}*/
00592 
00593 /*!
00594  * @name Register USB_OTGICR, field BSESSEN[2] (RW)
00595  *
00596  * Values:
00597  * - 0 - Disables the B_SESS_CHG interrupt.
00598  * - 1 - Enables the B_SESS_CHG interrupt.
00599  */
00600 /*@{*/
00601 #define BP_USB_OTGICR_BSESSEN (2U)         /*!< Bit position for USB_OTGICR_BSESSEN. */
00602 #define BM_USB_OTGICR_BSESSEN (0x04U)      /*!< Bit mask for USB_OTGICR_BSESSEN. */
00603 #define BS_USB_OTGICR_BSESSEN (1U)         /*!< Bit field size in bits for USB_OTGICR_BSESSEN. */
00604 
00605 /*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
00606 #define BR_USB_OTGICR_BSESSEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN)))
00607 
00608 /*! @brief Format value for bitfield USB_OTGICR_BSESSEN. */
00609 #define BF_USB_OTGICR_BSESSEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_BSESSEN) & BM_USB_OTGICR_BSESSEN)
00610 
00611 /*! @brief Set the BSESSEN field to a new value. */
00612 #define BW_USB_OTGICR_BSESSEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_BSESSEN), v))
00613 /*@}*/
00614 
00615 /*!
00616  * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
00617  *
00618  * Values:
00619  * - 0 - Disables the SESSVLDCHG interrupt.
00620  * - 1 - Enables the SESSVLDCHG interrupt.
00621  */
00622 /*@{*/
00623 #define BP_USB_OTGICR_SESSVLDEN (3U)       /*!< Bit position for USB_OTGICR_SESSVLDEN. */
00624 #define BM_USB_OTGICR_SESSVLDEN (0x08U)    /*!< Bit mask for USB_OTGICR_SESSVLDEN. */
00625 #define BS_USB_OTGICR_SESSVLDEN (1U)       /*!< Bit field size in bits for USB_OTGICR_SESSVLDEN. */
00626 
00627 /*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
00628 #define BR_USB_OTGICR_SESSVLDEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN)))
00629 
00630 /*! @brief Format value for bitfield USB_OTGICR_SESSVLDEN. */
00631 #define BF_USB_OTGICR_SESSVLDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_SESSVLDEN) & BM_USB_OTGICR_SESSVLDEN)
00632 
00633 /*! @brief Set the SESSVLDEN field to a new value. */
00634 #define BW_USB_OTGICR_SESSVLDEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_SESSVLDEN), v))
00635 /*@}*/
00636 
00637 /*!
00638  * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
00639  *
00640  * Values:
00641  * - 0 - Disables the LINE_STAT_CHG interrupt.
00642  * - 1 - Enables the LINE_STAT_CHG interrupt.
00643  */
00644 /*@{*/
00645 #define BP_USB_OTGICR_LINESTATEEN (5U)     /*!< Bit position for USB_OTGICR_LINESTATEEN. */
00646 #define BM_USB_OTGICR_LINESTATEEN (0x20U)  /*!< Bit mask for USB_OTGICR_LINESTATEEN. */
00647 #define BS_USB_OTGICR_LINESTATEEN (1U)     /*!< Bit field size in bits for USB_OTGICR_LINESTATEEN. */
00648 
00649 /*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
00650 #define BR_USB_OTGICR_LINESTATEEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN)))
00651 
00652 /*! @brief Format value for bitfield USB_OTGICR_LINESTATEEN. */
00653 #define BF_USB_OTGICR_LINESTATEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_LINESTATEEN) & BM_USB_OTGICR_LINESTATEEN)
00654 
00655 /*! @brief Set the LINESTATEEN field to a new value. */
00656 #define BW_USB_OTGICR_LINESTATEEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_LINESTATEEN), v))
00657 /*@}*/
00658 
00659 /*!
00660  * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
00661  *
00662  * Values:
00663  * - 0 - Diables the 1ms timer interrupt.
00664  * - 1 - Enables the 1ms timer interrupt.
00665  */
00666 /*@{*/
00667 #define BP_USB_OTGICR_ONEMSECEN (6U)       /*!< Bit position for USB_OTGICR_ONEMSECEN. */
00668 #define BM_USB_OTGICR_ONEMSECEN (0x40U)    /*!< Bit mask for USB_OTGICR_ONEMSECEN. */
00669 #define BS_USB_OTGICR_ONEMSECEN (1U)       /*!< Bit field size in bits for USB_OTGICR_ONEMSECEN. */
00670 
00671 /*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
00672 #define BR_USB_OTGICR_ONEMSECEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN)))
00673 
00674 /*! @brief Format value for bitfield USB_OTGICR_ONEMSECEN. */
00675 #define BF_USB_OTGICR_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_ONEMSECEN) & BM_USB_OTGICR_ONEMSECEN)
00676 
00677 /*! @brief Set the ONEMSECEN field to a new value. */
00678 #define BW_USB_OTGICR_ONEMSECEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_ONEMSECEN), v))
00679 /*@}*/
00680 
00681 /*!
00682  * @name Register USB_OTGICR, field IDEN[7] (RW)
00683  *
00684  * Values:
00685  * - 0 - The ID interrupt is disabled
00686  * - 1 - The ID interrupt is enabled
00687  */
00688 /*@{*/
00689 #define BP_USB_OTGICR_IDEN   (7U)          /*!< Bit position for USB_OTGICR_IDEN. */
00690 #define BM_USB_OTGICR_IDEN   (0x80U)       /*!< Bit mask for USB_OTGICR_IDEN. */
00691 #define BS_USB_OTGICR_IDEN   (1U)          /*!< Bit field size in bits for USB_OTGICR_IDEN. */
00692 
00693 /*! @brief Read current value of the USB_OTGICR_IDEN field. */
00694 #define BR_USB_OTGICR_IDEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN)))
00695 
00696 /*! @brief Format value for bitfield USB_OTGICR_IDEN. */
00697 #define BF_USB_OTGICR_IDEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGICR_IDEN) & BM_USB_OTGICR_IDEN)
00698 
00699 /*! @brief Set the IDEN field to a new value. */
00700 #define BW_USB_OTGICR_IDEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGICR_ADDR(x), BP_USB_OTGICR_IDEN), v))
00701 /*@}*/
00702 
00703 /*******************************************************************************
00704  * HW_USB_OTGSTAT - OTG Status register
00705  ******************************************************************************/
00706 
00707 /*!
00708  * @brief HW_USB_OTGSTAT - OTG Status register (RW)
00709  *
00710  * Reset value: 0x00U
00711  *
00712  * Displays the actual value from the external comparator outputs of the ID pin
00713  * and VBUS.
00714  */
00715 typedef union _hw_usb_otgstat
00716 {
00717     uint8_t U;
00718     struct _hw_usb_otgstat_bitfields
00719     {
00720         uint8_t AVBUSVLD : 1;          /*!< [0] A VBUS Valid */
00721         uint8_t RESERVED0 : 1;         /*!< [1]  */
00722         uint8_t BSESSEND : 1;          /*!< [2] B Session End */
00723         uint8_t SESS_VLD : 1;          /*!< [3] Session Valid */
00724         uint8_t RESERVED1 : 1;         /*!< [4]  */
00725         uint8_t LINESTATESTABLE : 1;   /*!< [5]  */
00726         uint8_t ONEMSECEN : 1;         /*!< [6]  */
00727         uint8_t ID : 1;                /*!< [7]  */
00728     } B;
00729 } hw_usb_otgstat_t;
00730 
00731 /*!
00732  * @name Constants and macros for entire USB_OTGSTAT register
00733  */
00734 /*@{*/
00735 #define HW_USB_OTGSTAT_ADDR(x)   ((x) + 0x18U)
00736 
00737 #define HW_USB_OTGSTAT(x)        (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR(x))
00738 #define HW_USB_OTGSTAT_RD(x)     (ADDRESS_READ(hw_usb_otgstat_t, HW_USB_OTGSTAT_ADDR(x)))
00739 #define HW_USB_OTGSTAT_WR(x, v)  (ADDRESS_WRITE(hw_usb_otgstat_t, HW_USB_OTGSTAT_ADDR(x), v))
00740 #define HW_USB_OTGSTAT_SET(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) |  (v)))
00741 #define HW_USB_OTGSTAT_CLR(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) & ~(v)))
00742 #define HW_USB_OTGSTAT_TOG(x, v) (HW_USB_OTGSTAT_WR(x, HW_USB_OTGSTAT_RD(x) ^  (v)))
00743 /*@}*/
00744 
00745 /*
00746  * Constants & macros for individual USB_OTGSTAT bitfields
00747  */
00748 
00749 /*!
00750  * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
00751  *
00752  * Values:
00753  * - 0 - The VBUS voltage is below the A VBUS Valid threshold.
00754  * - 1 - The VBUS voltage is above the A VBUS Valid threshold.
00755  */
00756 /*@{*/
00757 #define BP_USB_OTGSTAT_AVBUSVLD (0U)       /*!< Bit position for USB_OTGSTAT_AVBUSVLD. */
00758 #define BM_USB_OTGSTAT_AVBUSVLD (0x01U)    /*!< Bit mask for USB_OTGSTAT_AVBUSVLD. */
00759 #define BS_USB_OTGSTAT_AVBUSVLD (1U)       /*!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD. */
00760 
00761 /*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
00762 #define BR_USB_OTGSTAT_AVBUSVLD(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD)))
00763 
00764 /*! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD. */
00765 #define BF_USB_OTGSTAT_AVBUSVLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_AVBUSVLD) & BM_USB_OTGSTAT_AVBUSVLD)
00766 
00767 /*! @brief Set the AVBUSVLD field to a new value. */
00768 #define BW_USB_OTGSTAT_AVBUSVLD(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_AVBUSVLD), v))
00769 /*@}*/
00770 
00771 /*!
00772  * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
00773  *
00774  * Values:
00775  * - 0 - The VBUS voltage is above the B session end threshold.
00776  * - 1 - The VBUS voltage is below the B session end threshold.
00777  */
00778 /*@{*/
00779 #define BP_USB_OTGSTAT_BSESSEND (2U)       /*!< Bit position for USB_OTGSTAT_BSESSEND. */
00780 #define BM_USB_OTGSTAT_BSESSEND (0x04U)    /*!< Bit mask for USB_OTGSTAT_BSESSEND. */
00781 #define BS_USB_OTGSTAT_BSESSEND (1U)       /*!< Bit field size in bits for USB_OTGSTAT_BSESSEND. */
00782 
00783 /*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
00784 #define BR_USB_OTGSTAT_BSESSEND(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND)))
00785 
00786 /*! @brief Format value for bitfield USB_OTGSTAT_BSESSEND. */
00787 #define BF_USB_OTGSTAT_BSESSEND(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_BSESSEND) & BM_USB_OTGSTAT_BSESSEND)
00788 
00789 /*! @brief Set the BSESSEND field to a new value. */
00790 #define BW_USB_OTGSTAT_BSESSEND(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_BSESSEND), v))
00791 /*@}*/
00792 
00793 /*!
00794  * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
00795  *
00796  * Values:
00797  * - 0 - The VBUS voltage is below the B session valid threshold
00798  * - 1 - The VBUS voltage is above the B session valid threshold.
00799  */
00800 /*@{*/
00801 #define BP_USB_OTGSTAT_SESS_VLD (3U)       /*!< Bit position for USB_OTGSTAT_SESS_VLD. */
00802 #define BM_USB_OTGSTAT_SESS_VLD (0x08U)    /*!< Bit mask for USB_OTGSTAT_SESS_VLD. */
00803 #define BS_USB_OTGSTAT_SESS_VLD (1U)       /*!< Bit field size in bits for USB_OTGSTAT_SESS_VLD. */
00804 
00805 /*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
00806 #define BR_USB_OTGSTAT_SESS_VLD(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD)))
00807 
00808 /*! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD. */
00809 #define BF_USB_OTGSTAT_SESS_VLD(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_SESS_VLD) & BM_USB_OTGSTAT_SESS_VLD)
00810 
00811 /*! @brief Set the SESS_VLD field to a new value. */
00812 #define BW_USB_OTGSTAT_SESS_VLD(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_SESS_VLD), v))
00813 /*@}*/
00814 
00815 /*!
00816  * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
00817  *
00818  * Indicates that the internal signals that control the LINE_STATE_CHG field of
00819  * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
00820  * field and then read this field. If this field reads as 1, then the value of
00821  * LINE_STATE_CHG can be considered stable.
00822  *
00823  * Values:
00824  * - 0 - The LINE_STAT_CHG bit is not yet stable.
00825  * - 1 - The LINE_STAT_CHG bit has been debounced and is stable.
00826  */
00827 /*@{*/
00828 #define BP_USB_OTGSTAT_LINESTATESTABLE (5U) /*!< Bit position for USB_OTGSTAT_LINESTATESTABLE. */
00829 #define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) /*!< Bit mask for USB_OTGSTAT_LINESTATESTABLE. */
00830 #define BS_USB_OTGSTAT_LINESTATESTABLE (1U) /*!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE. */
00831 
00832 /*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
00833 #define BR_USB_OTGSTAT_LINESTATESTABLE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE)))
00834 
00835 /*! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE. */
00836 #define BF_USB_OTGSTAT_LINESTATESTABLE(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_LINESTATESTABLE) & BM_USB_OTGSTAT_LINESTATESTABLE)
00837 
00838 /*! @brief Set the LINESTATESTABLE field to a new value. */
00839 #define BW_USB_OTGSTAT_LINESTATESTABLE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_LINESTATESTABLE), v))
00840 /*@}*/
00841 
00842 /*!
00843  * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
00844  *
00845  * This bit is reserved for the 1ms count, but it is not useful to software.
00846  */
00847 /*@{*/
00848 #define BP_USB_OTGSTAT_ONEMSECEN (6U)      /*!< Bit position for USB_OTGSTAT_ONEMSECEN. */
00849 #define BM_USB_OTGSTAT_ONEMSECEN (0x40U)   /*!< Bit mask for USB_OTGSTAT_ONEMSECEN. */
00850 #define BS_USB_OTGSTAT_ONEMSECEN (1U)      /*!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN. */
00851 
00852 /*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
00853 #define BR_USB_OTGSTAT_ONEMSECEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN)))
00854 
00855 /*! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN. */
00856 #define BF_USB_OTGSTAT_ONEMSECEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ONEMSECEN) & BM_USB_OTGSTAT_ONEMSECEN)
00857 
00858 /*! @brief Set the ONEMSECEN field to a new value. */
00859 #define BW_USB_OTGSTAT_ONEMSECEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ONEMSECEN), v))
00860 /*@}*/
00861 
00862 /*!
00863  * @name Register USB_OTGSTAT, field ID[7] (RW)
00864  *
00865  * Indicates the current state of the ID pin on the USB connector
00866  *
00867  * Values:
00868  * - 0 - Indicates a Type A cable is plugged into the USB connector.
00869  * - 1 - Indicates no cable is attached or a Type B cable is plugged into the
00870  *     USB connector.
00871  */
00872 /*@{*/
00873 #define BP_USB_OTGSTAT_ID    (7U)          /*!< Bit position for USB_OTGSTAT_ID. */
00874 #define BM_USB_OTGSTAT_ID    (0x80U)       /*!< Bit mask for USB_OTGSTAT_ID. */
00875 #define BS_USB_OTGSTAT_ID    (1U)          /*!< Bit field size in bits for USB_OTGSTAT_ID. */
00876 
00877 /*! @brief Read current value of the USB_OTGSTAT_ID field. */
00878 #define BR_USB_OTGSTAT_ID(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID)))
00879 
00880 /*! @brief Format value for bitfield USB_OTGSTAT_ID. */
00881 #define BF_USB_OTGSTAT_ID(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGSTAT_ID) & BM_USB_OTGSTAT_ID)
00882 
00883 /*! @brief Set the ID field to a new value. */
00884 #define BW_USB_OTGSTAT_ID(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGSTAT_ADDR(x), BP_USB_OTGSTAT_ID), v))
00885 /*@}*/
00886 
00887 /*******************************************************************************
00888  * HW_USB_OTGCTL - OTG Control register
00889  ******************************************************************************/
00890 
00891 /*!
00892  * @brief HW_USB_OTGCTL - OTG Control register (RW)
00893  *
00894  * Reset value: 0x00U
00895  *
00896  * Controls the operation of VBUS and Data Line termination resistors.
00897  */
00898 typedef union _hw_usb_otgctl
00899 {
00900     uint8_t U;
00901     struct _hw_usb_otgctl_bitfields
00902     {
00903         uint8_t RESERVED0 : 2;         /*!< [1:0]  */
00904         uint8_t OTGEN : 1;             /*!< [2] On-The-Go pullup/pulldown resistor enable
00905                                         * */
00906         uint8_t RESERVED1 : 1;         /*!< [3]  */
00907         uint8_t DMLOW : 1;             /*!< [4] D- Data Line pull-down resistor enable */
00908         uint8_t DPLOW : 1;             /*!< [5] D+ Data Line pull-down resistor enable */
00909         uint8_t RESERVED2 : 1;         /*!< [6]  */
00910         uint8_t DPHIGH : 1;            /*!< [7] D+ Data Line pullup resistor enable */
00911     } B;
00912 } hw_usb_otgctl_t;
00913 
00914 /*!
00915  * @name Constants and macros for entire USB_OTGCTL register
00916  */
00917 /*@{*/
00918 #define HW_USB_OTGCTL_ADDR(x)    ((x) + 0x1CU)
00919 
00920 #define HW_USB_OTGCTL(x)         (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR(x))
00921 #define HW_USB_OTGCTL_RD(x)      (ADDRESS_READ(hw_usb_otgctl_t, HW_USB_OTGCTL_ADDR(x)))
00922 #define HW_USB_OTGCTL_WR(x, v)   (ADDRESS_WRITE(hw_usb_otgctl_t, HW_USB_OTGCTL_ADDR(x), v))
00923 #define HW_USB_OTGCTL_SET(x, v)  (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) |  (v)))
00924 #define HW_USB_OTGCTL_CLR(x, v)  (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) & ~(v)))
00925 #define HW_USB_OTGCTL_TOG(x, v)  (HW_USB_OTGCTL_WR(x, HW_USB_OTGCTL_RD(x) ^  (v)))
00926 /*@}*/
00927 
00928 /*
00929  * Constants & macros for individual USB_OTGCTL bitfields
00930  */
00931 
00932 /*!
00933  * @name Register USB_OTGCTL, field OTGEN[2] (RW)
00934  *
00935  * Values:
00936  * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
00937  *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
00938  *     and D- Data Line pull-down resistors are engaged.
00939  * - 1 - The pull-up and pull-down controls in this register are used.
00940  */
00941 /*@{*/
00942 #define BP_USB_OTGCTL_OTGEN  (2U)          /*!< Bit position for USB_OTGCTL_OTGEN. */
00943 #define BM_USB_OTGCTL_OTGEN  (0x04U)       /*!< Bit mask for USB_OTGCTL_OTGEN. */
00944 #define BS_USB_OTGCTL_OTGEN  (1U)          /*!< Bit field size in bits for USB_OTGCTL_OTGEN. */
00945 
00946 /*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
00947 #define BR_USB_OTGCTL_OTGEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN)))
00948 
00949 /*! @brief Format value for bitfield USB_OTGCTL_OTGEN. */
00950 #define BF_USB_OTGCTL_OTGEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_OTGEN) & BM_USB_OTGCTL_OTGEN)
00951 
00952 /*! @brief Set the OTGEN field to a new value. */
00953 #define BW_USB_OTGCTL_OTGEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_OTGEN), v))
00954 /*@}*/
00955 
00956 /*!
00957  * @name Register USB_OTGCTL, field DMLOW[4] (RW)
00958  *
00959  * Values:
00960  * - 0 - D- pulldown resistor is not enabled.
00961  * - 1 - D- pulldown resistor is enabled.
00962  */
00963 /*@{*/
00964 #define BP_USB_OTGCTL_DMLOW  (4U)          /*!< Bit position for USB_OTGCTL_DMLOW. */
00965 #define BM_USB_OTGCTL_DMLOW  (0x10U)       /*!< Bit mask for USB_OTGCTL_DMLOW. */
00966 #define BS_USB_OTGCTL_DMLOW  (1U)          /*!< Bit field size in bits for USB_OTGCTL_DMLOW. */
00967 
00968 /*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
00969 #define BR_USB_OTGCTL_DMLOW(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW)))
00970 
00971 /*! @brief Format value for bitfield USB_OTGCTL_DMLOW. */
00972 #define BF_USB_OTGCTL_DMLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DMLOW) & BM_USB_OTGCTL_DMLOW)
00973 
00974 /*! @brief Set the DMLOW field to a new value. */
00975 #define BW_USB_OTGCTL_DMLOW(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DMLOW), v))
00976 /*@}*/
00977 
00978 /*!
00979  * @name Register USB_OTGCTL, field DPLOW[5] (RW)
00980  *
00981  * This bit should always be enabled together with bit 4 (DMLOW)
00982  *
00983  * Values:
00984  * - 0 - D+ pulldown resistor is not enabled.
00985  * - 1 - D+ pulldown resistor is enabled.
00986  */
00987 /*@{*/
00988 #define BP_USB_OTGCTL_DPLOW  (5U)          /*!< Bit position for USB_OTGCTL_DPLOW. */
00989 #define BM_USB_OTGCTL_DPLOW  (0x20U)       /*!< Bit mask for USB_OTGCTL_DPLOW. */
00990 #define BS_USB_OTGCTL_DPLOW  (1U)          /*!< Bit field size in bits for USB_OTGCTL_DPLOW. */
00991 
00992 /*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
00993 #define BR_USB_OTGCTL_DPLOW(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW)))
00994 
00995 /*! @brief Format value for bitfield USB_OTGCTL_DPLOW. */
00996 #define BF_USB_OTGCTL_DPLOW(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPLOW) & BM_USB_OTGCTL_DPLOW)
00997 
00998 /*! @brief Set the DPLOW field to a new value. */
00999 #define BW_USB_OTGCTL_DPLOW(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPLOW), v))
01000 /*@}*/
01001 
01002 /*!
01003  * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
01004  *
01005  * Values:
01006  * - 0 - D+ pullup resistor is not enabled
01007  * - 1 - D+ pullup resistor is enabled
01008  */
01009 /*@{*/
01010 #define BP_USB_OTGCTL_DPHIGH (7U)          /*!< Bit position for USB_OTGCTL_DPHIGH. */
01011 #define BM_USB_OTGCTL_DPHIGH (0x80U)       /*!< Bit mask for USB_OTGCTL_DPHIGH. */
01012 #define BS_USB_OTGCTL_DPHIGH (1U)          /*!< Bit field size in bits for USB_OTGCTL_DPHIGH. */
01013 
01014 /*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
01015 #define BR_USB_OTGCTL_DPHIGH(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH)))
01016 
01017 /*! @brief Format value for bitfield USB_OTGCTL_DPHIGH. */
01018 #define BF_USB_OTGCTL_DPHIGH(v) ((uint8_t)((uint8_t)(v) << BP_USB_OTGCTL_DPHIGH) & BM_USB_OTGCTL_DPHIGH)
01019 
01020 /*! @brief Set the DPHIGH field to a new value. */
01021 #define BW_USB_OTGCTL_DPHIGH(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_OTGCTL_ADDR(x), BP_USB_OTGCTL_DPHIGH), v))
01022 /*@}*/
01023 
01024 /*******************************************************************************
01025  * HW_USB_ISTAT - Interrupt Status register
01026  ******************************************************************************/
01027 
01028 /*!
01029  * @brief HW_USB_ISTAT - Interrupt Status register (W1C)
01030  *
01031  * Reset value: 0x00U
01032  *
01033  * Contains fields for each of the interrupt sources within the USB Module. Each
01034  * of these fields are qualified with their respective interrupt enable bits.
01035  * All fields of this register are logically OR'd together along with the OTG
01036  * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
01037  * processor's interrupt controller. After an interrupt bit has been set it may only
01038  * be cleared by writing a one to the respective interrupt bit. This register
01039  * contains the value of 0x00 after a reset.
01040  */
01041 typedef union _hw_usb_istat
01042 {
01043     uint8_t U;
01044     struct _hw_usb_istat_bitfields
01045     {
01046         uint8_t USBRST : 1;            /*!< [0]  */
01047         uint8_t ERROR : 1;             /*!< [1]  */
01048         uint8_t SOFTOK : 1;            /*!< [2]  */
01049         uint8_t TOKDNE : 1;            /*!< [3]  */
01050         uint8_t SLEEP : 1;             /*!< [4]  */
01051         uint8_t RESUME : 1;            /*!< [5]  */
01052         uint8_t ATTACH : 1;            /*!< [6] Attach Interrupt */
01053         uint8_t STALL : 1;             /*!< [7] Stall Interrupt */
01054     } B;
01055 } hw_usb_istat_t;
01056 
01057 /*!
01058  * @name Constants and macros for entire USB_ISTAT register
01059  */
01060 /*@{*/
01061 #define HW_USB_ISTAT_ADDR(x)     ((x) + 0x80U)
01062 
01063 #define HW_USB_ISTAT(x)          (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR(x))
01064 #define HW_USB_ISTAT_RD(x)       (ADDRESS_READ(hw_usb_istat_t, HW_USB_ISTAT_ADDR(x)))
01065 #define HW_USB_ISTAT_WR(x, v)    (ADDRESS_WRITE(hw_usb_istat_t, HW_USB_ISTAT_ADDR(x), v))
01066 #define HW_USB_ISTAT_SET(x, v)   (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) |  (v)))
01067 #define HW_USB_ISTAT_CLR(x, v)   (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) & ~(v)))
01068 #define HW_USB_ISTAT_TOG(x, v)   (HW_USB_ISTAT_WR(x, HW_USB_ISTAT_RD(x) ^  (v)))
01069 /*@}*/
01070 
01071 /*
01072  * Constants & macros for individual USB_ISTAT bitfields
01073  */
01074 
01075 /*!
01076  * @name Register USB_ISTAT, field USBRST[0] (W1C)
01077  *
01078  * This bit is set when the USB Module has decoded a valid USB reset. This
01079  * informs the processor that it should write 0x00 into the address register and
01080  * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
01081  * microseconds. It is not asserted again until the USB reset condition has been
01082  * removed and then reasserted.
01083  */
01084 /*@{*/
01085 #define BP_USB_ISTAT_USBRST  (0U)          /*!< Bit position for USB_ISTAT_USBRST. */
01086 #define BM_USB_ISTAT_USBRST  (0x01U)       /*!< Bit mask for USB_ISTAT_USBRST. */
01087 #define BS_USB_ISTAT_USBRST  (1U)          /*!< Bit field size in bits for USB_ISTAT_USBRST. */
01088 
01089 /*! @brief Read current value of the USB_ISTAT_USBRST field. */
01090 #define BR_USB_ISTAT_USBRST(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST)))
01091 
01092 /*! @brief Format value for bitfield USB_ISTAT_USBRST. */
01093 #define BF_USB_ISTAT_USBRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_USBRST) & BM_USB_ISTAT_USBRST)
01094 
01095 /*! @brief Set the USBRST field to a new value. */
01096 #define BW_USB_ISTAT_USBRST(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_USBRST), v))
01097 /*@}*/
01098 
01099 /*!
01100  * @name Register USB_ISTAT, field ERROR[1] (W1C)
01101  *
01102  * This bit is set when any of the error conditions within Error Interrupt
01103  * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
01104  * to determine the source of the error.
01105  */
01106 /*@{*/
01107 #define BP_USB_ISTAT_ERROR   (1U)          /*!< Bit position for USB_ISTAT_ERROR. */
01108 #define BM_USB_ISTAT_ERROR   (0x02U)       /*!< Bit mask for USB_ISTAT_ERROR. */
01109 #define BS_USB_ISTAT_ERROR   (1U)          /*!< Bit field size in bits for USB_ISTAT_ERROR. */
01110 
01111 /*! @brief Read current value of the USB_ISTAT_ERROR field. */
01112 #define BR_USB_ISTAT_ERROR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR)))
01113 
01114 /*! @brief Format value for bitfield USB_ISTAT_ERROR. */
01115 #define BF_USB_ISTAT_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ERROR) & BM_USB_ISTAT_ERROR)
01116 
01117 /*! @brief Set the ERROR field to a new value. */
01118 #define BW_USB_ISTAT_ERROR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ERROR), v))
01119 /*@}*/
01120 
01121 /*!
01122  * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
01123  *
01124  * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
01125  * Host mode this field is set when the SOF threshold is reached, so that
01126  * software can prepare for the next SOF.
01127  */
01128 /*@{*/
01129 #define BP_USB_ISTAT_SOFTOK  (2U)          /*!< Bit position for USB_ISTAT_SOFTOK. */
01130 #define BM_USB_ISTAT_SOFTOK  (0x04U)       /*!< Bit mask for USB_ISTAT_SOFTOK. */
01131 #define BS_USB_ISTAT_SOFTOK  (1U)          /*!< Bit field size in bits for USB_ISTAT_SOFTOK. */
01132 
01133 /*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
01134 #define BR_USB_ISTAT_SOFTOK(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK)))
01135 
01136 /*! @brief Format value for bitfield USB_ISTAT_SOFTOK. */
01137 #define BF_USB_ISTAT_SOFTOK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SOFTOK) & BM_USB_ISTAT_SOFTOK)
01138 
01139 /*! @brief Set the SOFTOK field to a new value. */
01140 #define BW_USB_ISTAT_SOFTOK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SOFTOK), v))
01141 /*@}*/
01142 
01143 /*!
01144  * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
01145  *
01146  * This bit is set when the current token being processed has completed. The
01147  * processor must immediately read the STATUS (STAT) register to determine the
01148  * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
01149  * STAT to be cleared or the STAT holding register to be loaded into the STAT
01150  * register.
01151  */
01152 /*@{*/
01153 #define BP_USB_ISTAT_TOKDNE  (3U)          /*!< Bit position for USB_ISTAT_TOKDNE. */
01154 #define BM_USB_ISTAT_TOKDNE  (0x08U)       /*!< Bit mask for USB_ISTAT_TOKDNE. */
01155 #define BS_USB_ISTAT_TOKDNE  (1U)          /*!< Bit field size in bits for USB_ISTAT_TOKDNE. */
01156 
01157 /*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
01158 #define BR_USB_ISTAT_TOKDNE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE)))
01159 
01160 /*! @brief Format value for bitfield USB_ISTAT_TOKDNE. */
01161 #define BF_USB_ISTAT_TOKDNE(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_TOKDNE) & BM_USB_ISTAT_TOKDNE)
01162 
01163 /*! @brief Set the TOKDNE field to a new value. */
01164 #define BW_USB_ISTAT_TOKDNE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_TOKDNE), v))
01165 /*@}*/
01166 
01167 /*!
01168  * @name Register USB_ISTAT, field SLEEP[4] (W1C)
01169  *
01170  * This bit is set when the USB Module detects a constant idle on the USB bus
01171  * for 3 ms. The sleep timer is reset by activity on the USB bus.
01172  */
01173 /*@{*/
01174 #define BP_USB_ISTAT_SLEEP   (4U)          /*!< Bit position for USB_ISTAT_SLEEP. */
01175 #define BM_USB_ISTAT_SLEEP   (0x10U)       /*!< Bit mask for USB_ISTAT_SLEEP. */
01176 #define BS_USB_ISTAT_SLEEP   (1U)          /*!< Bit field size in bits for USB_ISTAT_SLEEP. */
01177 
01178 /*! @brief Read current value of the USB_ISTAT_SLEEP field. */
01179 #define BR_USB_ISTAT_SLEEP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP)))
01180 
01181 /*! @brief Format value for bitfield USB_ISTAT_SLEEP. */
01182 #define BF_USB_ISTAT_SLEEP(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_SLEEP) & BM_USB_ISTAT_SLEEP)
01183 
01184 /*! @brief Set the SLEEP field to a new value. */
01185 #define BW_USB_ISTAT_SLEEP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_SLEEP), v))
01186 /*@}*/
01187 
01188 /*!
01189  * @name Register USB_ISTAT, field RESUME[5] (W1C)
01190  *
01191  * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
01192  * When not in suspend mode this interrupt must be disabled.
01193  */
01194 /*@{*/
01195 #define BP_USB_ISTAT_RESUME  (5U)          /*!< Bit position for USB_ISTAT_RESUME. */
01196 #define BM_USB_ISTAT_RESUME  (0x20U)       /*!< Bit mask for USB_ISTAT_RESUME. */
01197 #define BS_USB_ISTAT_RESUME  (1U)          /*!< Bit field size in bits for USB_ISTAT_RESUME. */
01198 
01199 /*! @brief Read current value of the USB_ISTAT_RESUME field. */
01200 #define BR_USB_ISTAT_RESUME(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME)))
01201 
01202 /*! @brief Format value for bitfield USB_ISTAT_RESUME. */
01203 #define BF_USB_ISTAT_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_RESUME) & BM_USB_ISTAT_RESUME)
01204 
01205 /*! @brief Set the RESUME field to a new value. */
01206 #define BW_USB_ISTAT_RESUME(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_RESUME), v))
01207 /*@}*/
01208 
01209 /*!
01210  * @name Register USB_ISTAT, field ATTACH[6] (W1C)
01211  *
01212  * This bit is set when the USB Module detects an attach of a USB device. This
01213  * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
01214  * peripheral is now present and must be configured; it is asserted if there have
01215  * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
01216  */
01217 /*@{*/
01218 #define BP_USB_ISTAT_ATTACH  (6U)          /*!< Bit position for USB_ISTAT_ATTACH. */
01219 #define BM_USB_ISTAT_ATTACH  (0x40U)       /*!< Bit mask for USB_ISTAT_ATTACH. */
01220 #define BS_USB_ISTAT_ATTACH  (1U)          /*!< Bit field size in bits for USB_ISTAT_ATTACH. */
01221 
01222 /*! @brief Read current value of the USB_ISTAT_ATTACH field. */
01223 #define BR_USB_ISTAT_ATTACH(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH)))
01224 
01225 /*! @brief Format value for bitfield USB_ISTAT_ATTACH. */
01226 #define BF_USB_ISTAT_ATTACH(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_ATTACH) & BM_USB_ISTAT_ATTACH)
01227 
01228 /*! @brief Set the ATTACH field to a new value. */
01229 #define BW_USB_ISTAT_ATTACH(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_ATTACH), v))
01230 /*@}*/
01231 
01232 /*!
01233  * @name Register USB_ISTAT, field STALL[7] (W1C)
01234  *
01235  * In Target mode this bit is asserted when a STALL handshake is sent by the
01236  * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
01237  * during the handshake phase of a USB transaction.This interrupt can be used to
01238  * determine whether the last USB transaction was completed successfully or
01239  * stalled.
01240  */
01241 /*@{*/
01242 #define BP_USB_ISTAT_STALL   (7U)          /*!< Bit position for USB_ISTAT_STALL. */
01243 #define BM_USB_ISTAT_STALL   (0x80U)       /*!< Bit mask for USB_ISTAT_STALL. */
01244 #define BS_USB_ISTAT_STALL   (1U)          /*!< Bit field size in bits for USB_ISTAT_STALL. */
01245 
01246 /*! @brief Read current value of the USB_ISTAT_STALL field. */
01247 #define BR_USB_ISTAT_STALL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL)))
01248 
01249 /*! @brief Format value for bitfield USB_ISTAT_STALL. */
01250 #define BF_USB_ISTAT_STALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ISTAT_STALL) & BM_USB_ISTAT_STALL)
01251 
01252 /*! @brief Set the STALL field to a new value. */
01253 #define BW_USB_ISTAT_STALL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ISTAT_ADDR(x), BP_USB_ISTAT_STALL), v))
01254 /*@}*/
01255 
01256 /*******************************************************************************
01257  * HW_USB_INTEN - Interrupt Enable register
01258  ******************************************************************************/
01259 
01260 /*!
01261  * @brief HW_USB_INTEN - Interrupt Enable register (RW)
01262  *
01263  * Reset value: 0x00U
01264  *
01265  * Contains enable fields for each of the interrupt sources within the USB
01266  * Module. Setting any of these bits enables the respective interrupt source in the
01267  * ISTAT register. This register contains the value of 0x00 after a reset.
01268  */
01269 typedef union _hw_usb_inten
01270 {
01271     uint8_t U;
01272     struct _hw_usb_inten_bitfields
01273     {
01274         uint8_t USBRSTEN : 1;          /*!< [0] USBRST Interrupt Enable */
01275         uint8_t ERROREN : 1;           /*!< [1] ERROR Interrupt Enable */
01276         uint8_t SOFTOKEN : 1;          /*!< [2] SOFTOK Interrupt Enable */
01277         uint8_t TOKDNEEN : 1;          /*!< [3] TOKDNE Interrupt Enable */
01278         uint8_t SLEEPEN : 1;           /*!< [4] SLEEP Interrupt Enable */
01279         uint8_t RESUMEEN : 1;          /*!< [5] RESUME Interrupt Enable */
01280         uint8_t ATTACHEN : 1;          /*!< [6] ATTACH Interrupt Enable */
01281         uint8_t STALLEN : 1;           /*!< [7] STALL Interrupt Enable */
01282     } B;
01283 } hw_usb_inten_t;
01284 
01285 /*!
01286  * @name Constants and macros for entire USB_INTEN register
01287  */
01288 /*@{*/
01289 #define HW_USB_INTEN_ADDR(x)     ((x) + 0x84U)
01290 
01291 #define HW_USB_INTEN(x)          (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR(x))
01292 #define HW_USB_INTEN_RD(x)       (ADDRESS_READ(hw_usb_inten_t, HW_USB_INTEN_ADDR(x)))
01293 #define HW_USB_INTEN_WR(x, v)    (ADDRESS_WRITE(hw_usb_inten_t, HW_USB_INTEN_ADDR(x), v))
01294 #define HW_USB_INTEN_SET(x, v)   (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) |  (v)))
01295 #define HW_USB_INTEN_CLR(x, v)   (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) & ~(v)))
01296 #define HW_USB_INTEN_TOG(x, v)   (HW_USB_INTEN_WR(x, HW_USB_INTEN_RD(x) ^  (v)))
01297 /*@}*/
01298 
01299 /*
01300  * Constants & macros for individual USB_INTEN bitfields
01301  */
01302 
01303 /*!
01304  * @name Register USB_INTEN, field USBRSTEN[0] (RW)
01305  *
01306  * Values:
01307  * - 0 - Disables the USBRST interrupt.
01308  * - 1 - Enables the USBRST interrupt.
01309  */
01310 /*@{*/
01311 #define BP_USB_INTEN_USBRSTEN (0U)         /*!< Bit position for USB_INTEN_USBRSTEN. */
01312 #define BM_USB_INTEN_USBRSTEN (0x01U)      /*!< Bit mask for USB_INTEN_USBRSTEN. */
01313 #define BS_USB_INTEN_USBRSTEN (1U)         /*!< Bit field size in bits for USB_INTEN_USBRSTEN. */
01314 
01315 /*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
01316 #define BR_USB_INTEN_USBRSTEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN)))
01317 
01318 /*! @brief Format value for bitfield USB_INTEN_USBRSTEN. */
01319 #define BF_USB_INTEN_USBRSTEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_USBRSTEN) & BM_USB_INTEN_USBRSTEN)
01320 
01321 /*! @brief Set the USBRSTEN field to a new value. */
01322 #define BW_USB_INTEN_USBRSTEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_USBRSTEN), v))
01323 /*@}*/
01324 
01325 /*!
01326  * @name Register USB_INTEN, field ERROREN[1] (RW)
01327  *
01328  * Values:
01329  * - 0 - Disables the ERROR interrupt.
01330  * - 1 - Enables the ERROR interrupt.
01331  */
01332 /*@{*/
01333 #define BP_USB_INTEN_ERROREN (1U)          /*!< Bit position for USB_INTEN_ERROREN. */
01334 #define BM_USB_INTEN_ERROREN (0x02U)       /*!< Bit mask for USB_INTEN_ERROREN. */
01335 #define BS_USB_INTEN_ERROREN (1U)          /*!< Bit field size in bits for USB_INTEN_ERROREN. */
01336 
01337 /*! @brief Read current value of the USB_INTEN_ERROREN field. */
01338 #define BR_USB_INTEN_ERROREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN)))
01339 
01340 /*! @brief Format value for bitfield USB_INTEN_ERROREN. */
01341 #define BF_USB_INTEN_ERROREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ERROREN) & BM_USB_INTEN_ERROREN)
01342 
01343 /*! @brief Set the ERROREN field to a new value. */
01344 #define BW_USB_INTEN_ERROREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ERROREN), v))
01345 /*@}*/
01346 
01347 /*!
01348  * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
01349  *
01350  * Values:
01351  * - 0 - Disbles the SOFTOK interrupt.
01352  * - 1 - Enables the SOFTOK interrupt.
01353  */
01354 /*@{*/
01355 #define BP_USB_INTEN_SOFTOKEN (2U)         /*!< Bit position for USB_INTEN_SOFTOKEN. */
01356 #define BM_USB_INTEN_SOFTOKEN (0x04U)      /*!< Bit mask for USB_INTEN_SOFTOKEN. */
01357 #define BS_USB_INTEN_SOFTOKEN (1U)         /*!< Bit field size in bits for USB_INTEN_SOFTOKEN. */
01358 
01359 /*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
01360 #define BR_USB_INTEN_SOFTOKEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN)))
01361 
01362 /*! @brief Format value for bitfield USB_INTEN_SOFTOKEN. */
01363 #define BF_USB_INTEN_SOFTOKEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SOFTOKEN) & BM_USB_INTEN_SOFTOKEN)
01364 
01365 /*! @brief Set the SOFTOKEN field to a new value. */
01366 #define BW_USB_INTEN_SOFTOKEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SOFTOKEN), v))
01367 /*@}*/
01368 
01369 /*!
01370  * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
01371  *
01372  * Values:
01373  * - 0 - Disables the TOKDNE interrupt.
01374  * - 1 - Enables the TOKDNE interrupt.
01375  */
01376 /*@{*/
01377 #define BP_USB_INTEN_TOKDNEEN (3U)         /*!< Bit position for USB_INTEN_TOKDNEEN. */
01378 #define BM_USB_INTEN_TOKDNEEN (0x08U)      /*!< Bit mask for USB_INTEN_TOKDNEEN. */
01379 #define BS_USB_INTEN_TOKDNEEN (1U)         /*!< Bit field size in bits for USB_INTEN_TOKDNEEN. */
01380 
01381 /*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
01382 #define BR_USB_INTEN_TOKDNEEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN)))
01383 
01384 /*! @brief Format value for bitfield USB_INTEN_TOKDNEEN. */
01385 #define BF_USB_INTEN_TOKDNEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_TOKDNEEN) & BM_USB_INTEN_TOKDNEEN)
01386 
01387 /*! @brief Set the TOKDNEEN field to a new value. */
01388 #define BW_USB_INTEN_TOKDNEEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_TOKDNEEN), v))
01389 /*@}*/
01390 
01391 /*!
01392  * @name Register USB_INTEN, field SLEEPEN[4] (RW)
01393  *
01394  * Values:
01395  * - 0 - Disables the SLEEP interrupt.
01396  * - 1 - Enables the SLEEP interrupt.
01397  */
01398 /*@{*/
01399 #define BP_USB_INTEN_SLEEPEN (4U)          /*!< Bit position for USB_INTEN_SLEEPEN. */
01400 #define BM_USB_INTEN_SLEEPEN (0x10U)       /*!< Bit mask for USB_INTEN_SLEEPEN. */
01401 #define BS_USB_INTEN_SLEEPEN (1U)          /*!< Bit field size in bits for USB_INTEN_SLEEPEN. */
01402 
01403 /*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
01404 #define BR_USB_INTEN_SLEEPEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN)))
01405 
01406 /*! @brief Format value for bitfield USB_INTEN_SLEEPEN. */
01407 #define BF_USB_INTEN_SLEEPEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_SLEEPEN) & BM_USB_INTEN_SLEEPEN)
01408 
01409 /*! @brief Set the SLEEPEN field to a new value. */
01410 #define BW_USB_INTEN_SLEEPEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_SLEEPEN), v))
01411 /*@}*/
01412 
01413 /*!
01414  * @name Register USB_INTEN, field RESUMEEN[5] (RW)
01415  *
01416  * Values:
01417  * - 0 - Disables the RESUME interrupt.
01418  * - 1 - Enables the RESUME interrupt.
01419  */
01420 /*@{*/
01421 #define BP_USB_INTEN_RESUMEEN (5U)         /*!< Bit position for USB_INTEN_RESUMEEN. */
01422 #define BM_USB_INTEN_RESUMEEN (0x20U)      /*!< Bit mask for USB_INTEN_RESUMEEN. */
01423 #define BS_USB_INTEN_RESUMEEN (1U)         /*!< Bit field size in bits for USB_INTEN_RESUMEEN. */
01424 
01425 /*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
01426 #define BR_USB_INTEN_RESUMEEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN)))
01427 
01428 /*! @brief Format value for bitfield USB_INTEN_RESUMEEN. */
01429 #define BF_USB_INTEN_RESUMEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_RESUMEEN) & BM_USB_INTEN_RESUMEEN)
01430 
01431 /*! @brief Set the RESUMEEN field to a new value. */
01432 #define BW_USB_INTEN_RESUMEEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_RESUMEEN), v))
01433 /*@}*/
01434 
01435 /*!
01436  * @name Register USB_INTEN, field ATTACHEN[6] (RW)
01437  *
01438  * Values:
01439  * - 0 - Disables the ATTACH interrupt.
01440  * - 1 - Enables the ATTACH interrupt.
01441  */
01442 /*@{*/
01443 #define BP_USB_INTEN_ATTACHEN (6U)         /*!< Bit position for USB_INTEN_ATTACHEN. */
01444 #define BM_USB_INTEN_ATTACHEN (0x40U)      /*!< Bit mask for USB_INTEN_ATTACHEN. */
01445 #define BS_USB_INTEN_ATTACHEN (1U)         /*!< Bit field size in bits for USB_INTEN_ATTACHEN. */
01446 
01447 /*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
01448 #define BR_USB_INTEN_ATTACHEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN)))
01449 
01450 /*! @brief Format value for bitfield USB_INTEN_ATTACHEN. */
01451 #define BF_USB_INTEN_ATTACHEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_ATTACHEN) & BM_USB_INTEN_ATTACHEN)
01452 
01453 /*! @brief Set the ATTACHEN field to a new value. */
01454 #define BW_USB_INTEN_ATTACHEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_ATTACHEN), v))
01455 /*@}*/
01456 
01457 /*!
01458  * @name Register USB_INTEN, field STALLEN[7] (RW)
01459  *
01460  * Values:
01461  * - 0 - Diasbles the STALL interrupt.
01462  * - 1 - Enables the STALL interrupt.
01463  */
01464 /*@{*/
01465 #define BP_USB_INTEN_STALLEN (7U)          /*!< Bit position for USB_INTEN_STALLEN. */
01466 #define BM_USB_INTEN_STALLEN (0x80U)       /*!< Bit mask for USB_INTEN_STALLEN. */
01467 #define BS_USB_INTEN_STALLEN (1U)          /*!< Bit field size in bits for USB_INTEN_STALLEN. */
01468 
01469 /*! @brief Read current value of the USB_INTEN_STALLEN field. */
01470 #define BR_USB_INTEN_STALLEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN)))
01471 
01472 /*! @brief Format value for bitfield USB_INTEN_STALLEN. */
01473 #define BF_USB_INTEN_STALLEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_INTEN_STALLEN) & BM_USB_INTEN_STALLEN)
01474 
01475 /*! @brief Set the STALLEN field to a new value. */
01476 #define BW_USB_INTEN_STALLEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_INTEN_ADDR(x), BP_USB_INTEN_STALLEN), v))
01477 /*@}*/
01478 
01479 /*******************************************************************************
01480  * HW_USB_ERRSTAT - Error Interrupt Status register
01481  ******************************************************************************/
01482 
01483 /*!
01484  * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW)
01485  *
01486  * Reset value: 0x00U
01487  *
01488  * Contains enable bits for each of the error sources within the USB Module.
01489  * Each of these bits are qualified with their respective error enable bits. All
01490  * bits of this register are logically OR'd together and the result placed in the
01491  * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
01492  * be cleared by writing a one to the respective interrupt bit. Each bit is set
01493  * as soon as the error condition is detected. Therefore, the interrupt does not
01494  * typically correspond with the end of a token being processed. This register
01495  * contains the value of 0x00 after a reset.
01496  */
01497 typedef union _hw_usb_errstat
01498 {
01499     uint8_t U;
01500     struct _hw_usb_errstat_bitfields
01501     {
01502         uint8_t PIDERR : 1;            /*!< [0]  */
01503         uint8_t CRC5EOF : 1;           /*!< [1]  */
01504         uint8_t CRC16 : 1;             /*!< [2]  */
01505         uint8_t DFN8 : 1;              /*!< [3]  */
01506         uint8_t BTOERR : 1;            /*!< [4]  */
01507         uint8_t DMAERR : 1;            /*!< [5]  */
01508         uint8_t RESERVED0 : 1;         /*!< [6]  */
01509         uint8_t BTSERR : 1;            /*!< [7]  */
01510     } B;
01511 } hw_usb_errstat_t;
01512 
01513 /*!
01514  * @name Constants and macros for entire USB_ERRSTAT register
01515  */
01516 /*@{*/
01517 #define HW_USB_ERRSTAT_ADDR(x)   ((x) + 0x88U)
01518 
01519 #define HW_USB_ERRSTAT(x)        (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR(x))
01520 #define HW_USB_ERRSTAT_RD(x)     (ADDRESS_READ(hw_usb_errstat_t, HW_USB_ERRSTAT_ADDR(x)))
01521 #define HW_USB_ERRSTAT_WR(x, v)  (ADDRESS_WRITE(hw_usb_errstat_t, HW_USB_ERRSTAT_ADDR(x), v))
01522 #define HW_USB_ERRSTAT_SET(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) |  (v)))
01523 #define HW_USB_ERRSTAT_CLR(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) & ~(v)))
01524 #define HW_USB_ERRSTAT_TOG(x, v) (HW_USB_ERRSTAT_WR(x, HW_USB_ERRSTAT_RD(x) ^  (v)))
01525 /*@}*/
01526 
01527 /*
01528  * Constants & macros for individual USB_ERRSTAT bitfields
01529  */
01530 
01531 /*!
01532  * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
01533  *
01534  * This bit is set when the PID check field fails.
01535  */
01536 /*@{*/
01537 #define BP_USB_ERRSTAT_PIDERR (0U)         /*!< Bit position for USB_ERRSTAT_PIDERR. */
01538 #define BM_USB_ERRSTAT_PIDERR (0x01U)      /*!< Bit mask for USB_ERRSTAT_PIDERR. */
01539 #define BS_USB_ERRSTAT_PIDERR (1U)         /*!< Bit field size in bits for USB_ERRSTAT_PIDERR. */
01540 
01541 /*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
01542 #define BR_USB_ERRSTAT_PIDERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR)))
01543 
01544 /*! @brief Format value for bitfield USB_ERRSTAT_PIDERR. */
01545 #define BF_USB_ERRSTAT_PIDERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_PIDERR) & BM_USB_ERRSTAT_PIDERR)
01546 
01547 /*! @brief Set the PIDERR field to a new value. */
01548 #define BW_USB_ERRSTAT_PIDERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_PIDERR), v))
01549 /*@}*/
01550 
01551 /*!
01552  * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
01553  *
01554  * This error interrupt has two functions. When the USB Module is operating in
01555  * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
01556  * packets generated by the host. If set the token packet was rejected due to a
01557  * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
01558  * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
01559  * USB Module is transmitting or receiving data and the SOF counter reaches zero.
01560  * This interrupt is useful when developing USB packet scheduling software to
01561  * ensure that no USB transactions cross the start of the next frame.
01562  */
01563 /*@{*/
01564 #define BP_USB_ERRSTAT_CRC5EOF (1U)        /*!< Bit position for USB_ERRSTAT_CRC5EOF. */
01565 #define BM_USB_ERRSTAT_CRC5EOF (0x02U)     /*!< Bit mask for USB_ERRSTAT_CRC5EOF. */
01566 #define BS_USB_ERRSTAT_CRC5EOF (1U)        /*!< Bit field size in bits for USB_ERRSTAT_CRC5EOF. */
01567 
01568 /*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
01569 #define BR_USB_ERRSTAT_CRC5EOF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF)))
01570 
01571 /*! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF. */
01572 #define BF_USB_ERRSTAT_CRC5EOF(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC5EOF) & BM_USB_ERRSTAT_CRC5EOF)
01573 
01574 /*! @brief Set the CRC5EOF field to a new value. */
01575 #define BW_USB_ERRSTAT_CRC5EOF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC5EOF), v))
01576 /*@}*/
01577 
01578 /*!
01579  * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
01580  *
01581  * This bit is set when a data packet is rejected due to a CRC16 error.
01582  */
01583 /*@{*/
01584 #define BP_USB_ERRSTAT_CRC16 (2U)          /*!< Bit position for USB_ERRSTAT_CRC16. */
01585 #define BM_USB_ERRSTAT_CRC16 (0x04U)       /*!< Bit mask for USB_ERRSTAT_CRC16. */
01586 #define BS_USB_ERRSTAT_CRC16 (1U)          /*!< Bit field size in bits for USB_ERRSTAT_CRC16. */
01587 
01588 /*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
01589 #define BR_USB_ERRSTAT_CRC16(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16)))
01590 
01591 /*! @brief Format value for bitfield USB_ERRSTAT_CRC16. */
01592 #define BF_USB_ERRSTAT_CRC16(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_CRC16) & BM_USB_ERRSTAT_CRC16)
01593 
01594 /*! @brief Set the CRC16 field to a new value. */
01595 #define BW_USB_ERRSTAT_CRC16(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_CRC16), v))
01596 /*@}*/
01597 
01598 /*!
01599  * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
01600  *
01601  * This bit is set if the data field received was not 8 bits in length. USB
01602  * Specification 1.0 requires that data fields be an integral number of bytes. If the
01603  * data field was not an integral number of bytes, this bit is set.
01604  */
01605 /*@{*/
01606 #define BP_USB_ERRSTAT_DFN8  (3U)          /*!< Bit position for USB_ERRSTAT_DFN8. */
01607 #define BM_USB_ERRSTAT_DFN8  (0x08U)       /*!< Bit mask for USB_ERRSTAT_DFN8. */
01608 #define BS_USB_ERRSTAT_DFN8  (1U)          /*!< Bit field size in bits for USB_ERRSTAT_DFN8. */
01609 
01610 /*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
01611 #define BR_USB_ERRSTAT_DFN8(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8)))
01612 
01613 /*! @brief Format value for bitfield USB_ERRSTAT_DFN8. */
01614 #define BF_USB_ERRSTAT_DFN8(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DFN8) & BM_USB_ERRSTAT_DFN8)
01615 
01616 /*! @brief Set the DFN8 field to a new value. */
01617 #define BW_USB_ERRSTAT_DFN8(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DFN8), v))
01618 /*@}*/
01619 
01620 /*!
01621  * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
01622  *
01623  * This bit is set when a bus turnaround timeout error occurs. The USB module
01624  * contains a bus turnaround timer that keeps track of the amount of time elapsed
01625  * between the token and data phases of a SETUP or OUT TOKEN or the data and
01626  * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
01627  * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
01628  */
01629 /*@{*/
01630 #define BP_USB_ERRSTAT_BTOERR (4U)         /*!< Bit position for USB_ERRSTAT_BTOERR. */
01631 #define BM_USB_ERRSTAT_BTOERR (0x10U)      /*!< Bit mask for USB_ERRSTAT_BTOERR. */
01632 #define BS_USB_ERRSTAT_BTOERR (1U)         /*!< Bit field size in bits for USB_ERRSTAT_BTOERR. */
01633 
01634 /*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
01635 #define BR_USB_ERRSTAT_BTOERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR)))
01636 
01637 /*! @brief Format value for bitfield USB_ERRSTAT_BTOERR. */
01638 #define BF_USB_ERRSTAT_BTOERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTOERR) & BM_USB_ERRSTAT_BTOERR)
01639 
01640 /*! @brief Set the BTOERR field to a new value. */
01641 #define BW_USB_ERRSTAT_BTOERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTOERR), v))
01642 /*@}*/
01643 
01644 /*!
01645  * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
01646  *
01647  * This bit is set if the USB Module has requested a DMA access to read a new
01648  * BDT but has not been given the bus before it needs to receive or transmit data.
01649  * If processing a TX transfer this would cause a transmit data underflow
01650  * condition. If processing a RX transfer this would cause a receive data overflow
01651  * condition. This interrupt is useful when developing device arbitration hardware for
01652  * the microprocessor and the USB module to minimize bus request and bus grant
01653  * latency. This bit is also set if a data packet to or from the host is larger
01654  * than the buffer size allocated in the BDT. In this case the data packet is
01655  * truncated as it is put in buffer memory.
01656  */
01657 /*@{*/
01658 #define BP_USB_ERRSTAT_DMAERR (5U)         /*!< Bit position for USB_ERRSTAT_DMAERR. */
01659 #define BM_USB_ERRSTAT_DMAERR (0x20U)      /*!< Bit mask for USB_ERRSTAT_DMAERR. */
01660 #define BS_USB_ERRSTAT_DMAERR (1U)         /*!< Bit field size in bits for USB_ERRSTAT_DMAERR. */
01661 
01662 /*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
01663 #define BR_USB_ERRSTAT_DMAERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR)))
01664 
01665 /*! @brief Format value for bitfield USB_ERRSTAT_DMAERR. */
01666 #define BF_USB_ERRSTAT_DMAERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_DMAERR) & BM_USB_ERRSTAT_DMAERR)
01667 
01668 /*! @brief Set the DMAERR field to a new value. */
01669 #define BW_USB_ERRSTAT_DMAERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_DMAERR), v))
01670 /*@}*/
01671 
01672 /*!
01673  * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
01674  *
01675  * This bit is set when a bit stuff error is detected. If set, the corresponding
01676  * packet is rejected due to the error.
01677  */
01678 /*@{*/
01679 #define BP_USB_ERRSTAT_BTSERR (7U)         /*!< Bit position for USB_ERRSTAT_BTSERR. */
01680 #define BM_USB_ERRSTAT_BTSERR (0x80U)      /*!< Bit mask for USB_ERRSTAT_BTSERR. */
01681 #define BS_USB_ERRSTAT_BTSERR (1U)         /*!< Bit field size in bits for USB_ERRSTAT_BTSERR. */
01682 
01683 /*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
01684 #define BR_USB_ERRSTAT_BTSERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR)))
01685 
01686 /*! @brief Format value for bitfield USB_ERRSTAT_BTSERR. */
01687 #define BF_USB_ERRSTAT_BTSERR(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERRSTAT_BTSERR) & BM_USB_ERRSTAT_BTSERR)
01688 
01689 /*! @brief Set the BTSERR field to a new value. */
01690 #define BW_USB_ERRSTAT_BTSERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERRSTAT_ADDR(x), BP_USB_ERRSTAT_BTSERR), v))
01691 /*@}*/
01692 
01693 /*******************************************************************************
01694  * HW_USB_ERREN - Error Interrupt Enable register
01695  ******************************************************************************/
01696 
01697 /*!
01698  * @brief HW_USB_ERREN - Error Interrupt Enable register (RW)
01699  *
01700  * Reset value: 0x00U
01701  *
01702  * Contains enable bits for each of the error interrupt sources within the USB
01703  * module. Setting any of these bits enables the respective interrupt source in
01704  * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
01705  * the interrupt does not typically correspond with the end of a token being
01706  * processed. This register contains the value of 0x00 after a reset.
01707  */
01708 typedef union _hw_usb_erren
01709 {
01710     uint8_t U;
01711     struct _hw_usb_erren_bitfields
01712     {
01713         uint8_t PIDERREN : 1;          /*!< [0] PIDERR Interrupt Enable */
01714         uint8_t CRC5EOFEN : 1;         /*!< [1] CRC5/EOF Interrupt Enable */
01715         uint8_t CRC16EN : 1;           /*!< [2] CRC16 Interrupt Enable */
01716         uint8_t DFN8EN : 1;            /*!< [3] DFN8 Interrupt Enable */
01717         uint8_t BTOERREN : 1;          /*!< [4] BTOERR Interrupt Enable */
01718         uint8_t DMAERREN : 1;          /*!< [5] DMAERR Interrupt Enable */
01719         uint8_t RESERVED0 : 1;         /*!< [6]  */
01720         uint8_t BTSERREN : 1;          /*!< [7] BTSERR Interrupt Enable */
01721     } B;
01722 } hw_usb_erren_t;
01723 
01724 /*!
01725  * @name Constants and macros for entire USB_ERREN register
01726  */
01727 /*@{*/
01728 #define HW_USB_ERREN_ADDR(x)     ((x) + 0x8CU)
01729 
01730 #define HW_USB_ERREN(x)          (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR(x))
01731 #define HW_USB_ERREN_RD(x)       (ADDRESS_READ(hw_usb_erren_t, HW_USB_ERREN_ADDR(x)))
01732 #define HW_USB_ERREN_WR(x, v)    (ADDRESS_WRITE(hw_usb_erren_t, HW_USB_ERREN_ADDR(x), v))
01733 #define HW_USB_ERREN_SET(x, v)   (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) |  (v)))
01734 #define HW_USB_ERREN_CLR(x, v)   (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) & ~(v)))
01735 #define HW_USB_ERREN_TOG(x, v)   (HW_USB_ERREN_WR(x, HW_USB_ERREN_RD(x) ^  (v)))
01736 /*@}*/
01737 
01738 /*
01739  * Constants & macros for individual USB_ERREN bitfields
01740  */
01741 
01742 /*!
01743  * @name Register USB_ERREN, field PIDERREN[0] (RW)
01744  *
01745  * Values:
01746  * - 0 - Disables the PIDERR interrupt.
01747  * - 1 - Enters the PIDERR interrupt.
01748  */
01749 /*@{*/
01750 #define BP_USB_ERREN_PIDERREN (0U)         /*!< Bit position for USB_ERREN_PIDERREN. */
01751 #define BM_USB_ERREN_PIDERREN (0x01U)      /*!< Bit mask for USB_ERREN_PIDERREN. */
01752 #define BS_USB_ERREN_PIDERREN (1U)         /*!< Bit field size in bits for USB_ERREN_PIDERREN. */
01753 
01754 /*! @brief Read current value of the USB_ERREN_PIDERREN field. */
01755 #define BR_USB_ERREN_PIDERREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN)))
01756 
01757 /*! @brief Format value for bitfield USB_ERREN_PIDERREN. */
01758 #define BF_USB_ERREN_PIDERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_PIDERREN) & BM_USB_ERREN_PIDERREN)
01759 
01760 /*! @brief Set the PIDERREN field to a new value. */
01761 #define BW_USB_ERREN_PIDERREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_PIDERREN), v))
01762 /*@}*/
01763 
01764 /*!
01765  * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
01766  *
01767  * Values:
01768  * - 0 - Disables the CRC5/EOF interrupt.
01769  * - 1 - Enables the CRC5/EOF interrupt.
01770  */
01771 /*@{*/
01772 #define BP_USB_ERREN_CRC5EOFEN (1U)        /*!< Bit position for USB_ERREN_CRC5EOFEN. */
01773 #define BM_USB_ERREN_CRC5EOFEN (0x02U)     /*!< Bit mask for USB_ERREN_CRC5EOFEN. */
01774 #define BS_USB_ERREN_CRC5EOFEN (1U)        /*!< Bit field size in bits for USB_ERREN_CRC5EOFEN. */
01775 
01776 /*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
01777 #define BR_USB_ERREN_CRC5EOFEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN)))
01778 
01779 /*! @brief Format value for bitfield USB_ERREN_CRC5EOFEN. */
01780 #define BF_USB_ERREN_CRC5EOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC5EOFEN) & BM_USB_ERREN_CRC5EOFEN)
01781 
01782 /*! @brief Set the CRC5EOFEN field to a new value. */
01783 #define BW_USB_ERREN_CRC5EOFEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC5EOFEN), v))
01784 /*@}*/
01785 
01786 /*!
01787  * @name Register USB_ERREN, field CRC16EN[2] (RW)
01788  *
01789  * Values:
01790  * - 0 - Disables the CRC16 interrupt.
01791  * - 1 - Enables the CRC16 interrupt.
01792  */
01793 /*@{*/
01794 #define BP_USB_ERREN_CRC16EN (2U)          /*!< Bit position for USB_ERREN_CRC16EN. */
01795 #define BM_USB_ERREN_CRC16EN (0x04U)       /*!< Bit mask for USB_ERREN_CRC16EN. */
01796 #define BS_USB_ERREN_CRC16EN (1U)          /*!< Bit field size in bits for USB_ERREN_CRC16EN. */
01797 
01798 /*! @brief Read current value of the USB_ERREN_CRC16EN field. */
01799 #define BR_USB_ERREN_CRC16EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN)))
01800 
01801 /*! @brief Format value for bitfield USB_ERREN_CRC16EN. */
01802 #define BF_USB_ERREN_CRC16EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_CRC16EN) & BM_USB_ERREN_CRC16EN)
01803 
01804 /*! @brief Set the CRC16EN field to a new value. */
01805 #define BW_USB_ERREN_CRC16EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_CRC16EN), v))
01806 /*@}*/
01807 
01808 /*!
01809  * @name Register USB_ERREN, field DFN8EN[3] (RW)
01810  *
01811  * Values:
01812  * - 0 - Disables the DFN8 interrupt.
01813  * - 1 - Enables the DFN8 interrupt.
01814  */
01815 /*@{*/
01816 #define BP_USB_ERREN_DFN8EN  (3U)          /*!< Bit position for USB_ERREN_DFN8EN. */
01817 #define BM_USB_ERREN_DFN8EN  (0x08U)       /*!< Bit mask for USB_ERREN_DFN8EN. */
01818 #define BS_USB_ERREN_DFN8EN  (1U)          /*!< Bit field size in bits for USB_ERREN_DFN8EN. */
01819 
01820 /*! @brief Read current value of the USB_ERREN_DFN8EN field. */
01821 #define BR_USB_ERREN_DFN8EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN)))
01822 
01823 /*! @brief Format value for bitfield USB_ERREN_DFN8EN. */
01824 #define BF_USB_ERREN_DFN8EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DFN8EN) & BM_USB_ERREN_DFN8EN)
01825 
01826 /*! @brief Set the DFN8EN field to a new value. */
01827 #define BW_USB_ERREN_DFN8EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DFN8EN), v))
01828 /*@}*/
01829 
01830 /*!
01831  * @name Register USB_ERREN, field BTOERREN[4] (RW)
01832  *
01833  * Values:
01834  * - 0 - Disables the BTOERR interrupt.
01835  * - 1 - Enables the BTOERR interrupt.
01836  */
01837 /*@{*/
01838 #define BP_USB_ERREN_BTOERREN (4U)         /*!< Bit position for USB_ERREN_BTOERREN. */
01839 #define BM_USB_ERREN_BTOERREN (0x10U)      /*!< Bit mask for USB_ERREN_BTOERREN. */
01840 #define BS_USB_ERREN_BTOERREN (1U)         /*!< Bit field size in bits for USB_ERREN_BTOERREN. */
01841 
01842 /*! @brief Read current value of the USB_ERREN_BTOERREN field. */
01843 #define BR_USB_ERREN_BTOERREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN)))
01844 
01845 /*! @brief Format value for bitfield USB_ERREN_BTOERREN. */
01846 #define BF_USB_ERREN_BTOERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTOERREN) & BM_USB_ERREN_BTOERREN)
01847 
01848 /*! @brief Set the BTOERREN field to a new value. */
01849 #define BW_USB_ERREN_BTOERREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTOERREN), v))
01850 /*@}*/
01851 
01852 /*!
01853  * @name Register USB_ERREN, field DMAERREN[5] (RW)
01854  *
01855  * Values:
01856  * - 0 - Disables the DMAERR interrupt.
01857  * - 1 - Enables the DMAERR interrupt.
01858  */
01859 /*@{*/
01860 #define BP_USB_ERREN_DMAERREN (5U)         /*!< Bit position for USB_ERREN_DMAERREN. */
01861 #define BM_USB_ERREN_DMAERREN (0x20U)      /*!< Bit mask for USB_ERREN_DMAERREN. */
01862 #define BS_USB_ERREN_DMAERREN (1U)         /*!< Bit field size in bits for USB_ERREN_DMAERREN. */
01863 
01864 /*! @brief Read current value of the USB_ERREN_DMAERREN field. */
01865 #define BR_USB_ERREN_DMAERREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN)))
01866 
01867 /*! @brief Format value for bitfield USB_ERREN_DMAERREN. */
01868 #define BF_USB_ERREN_DMAERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_DMAERREN) & BM_USB_ERREN_DMAERREN)
01869 
01870 /*! @brief Set the DMAERREN field to a new value. */
01871 #define BW_USB_ERREN_DMAERREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_DMAERREN), v))
01872 /*@}*/
01873 
01874 /*!
01875  * @name Register USB_ERREN, field BTSERREN[7] (RW)
01876  *
01877  * Values:
01878  * - 0 - Disables the BTSERR interrupt.
01879  * - 1 - Enables the BTSERR interrupt.
01880  */
01881 /*@{*/
01882 #define BP_USB_ERREN_BTSERREN (7U)         /*!< Bit position for USB_ERREN_BTSERREN. */
01883 #define BM_USB_ERREN_BTSERREN (0x80U)      /*!< Bit mask for USB_ERREN_BTSERREN. */
01884 #define BS_USB_ERREN_BTSERREN (1U)         /*!< Bit field size in bits for USB_ERREN_BTSERREN. */
01885 
01886 /*! @brief Read current value of the USB_ERREN_BTSERREN field. */
01887 #define BR_USB_ERREN_BTSERREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN)))
01888 
01889 /*! @brief Format value for bitfield USB_ERREN_BTSERREN. */
01890 #define BF_USB_ERREN_BTSERREN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ERREN_BTSERREN) & BM_USB_ERREN_BTSERREN)
01891 
01892 /*! @brief Set the BTSERREN field to a new value. */
01893 #define BW_USB_ERREN_BTSERREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ERREN_ADDR(x), BP_USB_ERREN_BTSERREN), v))
01894 /*@}*/
01895 
01896 /*******************************************************************************
01897  * HW_USB_STAT - Status register
01898  ******************************************************************************/
01899 
01900 /*!
01901  * @brief HW_USB_STAT - Status register (RO)
01902  *
01903  * Reset value: 0x00U
01904  *
01905  * Reports the transaction status within the USB module. When the processor's
01906  * interrupt controller has received a TOKDNE, interrupt the Status Register must
01907  * be read to determine the status of the previous endpoint communication. The
01908  * data in the status register is valid when TOKDNE interrupt is asserted. The
01909  * Status register is actually a read window into a status FIFO maintained by the USB
01910  * module. When the USB module uses a BD, it updates the Status register. If
01911  * another USB transaction is performed before the TOKDNE interrupt is serviced, the
01912  * USB module stores the status of the next transaction in the STAT FIFO. Thus
01913  * STAT is actually a four byte FIFO that allows the processor core to process one
01914  * transaction while the SIE is processing the next transaction. Clearing the
01915  * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
01916  * of the next STAT value. If the data in the STAT holding register is valid, the
01917  * SIE immediately reasserts to TOKDNE interrupt.
01918  */
01919 typedef union _hw_usb_stat
01920 {
01921     uint8_t U;
01922     struct _hw_usb_stat_bitfields
01923     {
01924         uint8_t RESERVED0 : 2;         /*!< [1:0]  */
01925         uint8_t ODD : 1;               /*!< [2]  */
01926         uint8_t TX : 1;                /*!< [3] Transmit Indicator */
01927         uint8_t ENDP : 4;              /*!< [7:4]  */
01928     } B;
01929 } hw_usb_stat_t;
01930 
01931 /*!
01932  * @name Constants and macros for entire USB_STAT register
01933  */
01934 /*@{*/
01935 #define HW_USB_STAT_ADDR(x)      ((x) + 0x90U)
01936 
01937 #define HW_USB_STAT(x)           (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR(x))
01938 #define HW_USB_STAT_RD(x)        (ADDRESS_READ(hw_usb_stat_t, HW_USB_STAT_ADDR(x)))
01939 /*@}*/
01940 
01941 /*
01942  * Constants & macros for individual USB_STAT bitfields
01943  */
01944 
01945 /*!
01946  * @name Register USB_STAT, field ODD[2] (RO)
01947  *
01948  * This bit is set if the last buffer descriptor updated was in the odd bank of
01949  * the BDT.
01950  */
01951 /*@{*/
01952 #define BP_USB_STAT_ODD      (2U)          /*!< Bit position for USB_STAT_ODD. */
01953 #define BM_USB_STAT_ODD      (0x04U)       /*!< Bit mask for USB_STAT_ODD. */
01954 #define BS_USB_STAT_ODD      (1U)          /*!< Bit field size in bits for USB_STAT_ODD. */
01955 
01956 /*! @brief Read current value of the USB_STAT_ODD field. */
01957 #define BR_USB_STAT_ODD(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_ODD)))
01958 /*@}*/
01959 
01960 /*!
01961  * @name Register USB_STAT, field TX[3] (RO)
01962  *
01963  * Values:
01964  * - 0 - The most recent transaction was a receive operation.
01965  * - 1 - The most recent transaction was a transmit operation.
01966  */
01967 /*@{*/
01968 #define BP_USB_STAT_TX       (3U)          /*!< Bit position for USB_STAT_TX. */
01969 #define BM_USB_STAT_TX       (0x08U)       /*!< Bit mask for USB_STAT_TX. */
01970 #define BS_USB_STAT_TX       (1U)          /*!< Bit field size in bits for USB_STAT_TX. */
01971 
01972 /*! @brief Read current value of the USB_STAT_TX field. */
01973 #define BR_USB_STAT_TX(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_STAT_ADDR(x), BP_USB_STAT_TX)))
01974 /*@}*/
01975 
01976 /*!
01977  * @name Register USB_STAT, field ENDP[7:4] (RO)
01978  *
01979  * This four-bit field encodes the endpoint address that received or transmitted
01980  * the previous token. This allows the processor core to determine the BDT entry
01981  * that was updated by the last USB transaction.
01982  */
01983 /*@{*/
01984 #define BP_USB_STAT_ENDP     (4U)          /*!< Bit position for USB_STAT_ENDP. */
01985 #define BM_USB_STAT_ENDP     (0xF0U)       /*!< Bit mask for USB_STAT_ENDP. */
01986 #define BS_USB_STAT_ENDP     (4U)          /*!< Bit field size in bits for USB_STAT_ENDP. */
01987 
01988 /*! @brief Read current value of the USB_STAT_ENDP field. */
01989 #define BR_USB_STAT_ENDP(x)  (UNION_READ(hw_usb_stat_t, HW_USB_STAT_ADDR(x), U, B.ENDP))
01990 /*@}*/
01991 
01992 /*******************************************************************************
01993  * HW_USB_CTL - Control register
01994  ******************************************************************************/
01995 
01996 /*!
01997  * @brief HW_USB_CTL - Control register (RW)
01998  *
01999  * Reset value: 0x00U
02000  *
02001  * Provides various control and configuration information for the USB module.
02002  */
02003 typedef union _hw_usb_ctl
02004 {
02005     uint8_t U;
02006     struct _hw_usb_ctl_bitfields
02007     {
02008         uint8_t USBENSOFEN : 1;        /*!< [0] USB Enable */
02009         uint8_t ODDRST : 1;            /*!< [1]  */
02010         uint8_t RESUME : 1;            /*!< [2]  */
02011         uint8_t HOSTMODEEN : 1;        /*!< [3]  */
02012         uint8_t RESET : 1;             /*!< [4]  */
02013         uint8_t TXSUSPENDTOKENBUSY : 1; /*!< [5]  */
02014         uint8_t SE0 : 1;               /*!< [6] Live USB Single Ended Zero signal */
02015         uint8_t JSTATE : 1;            /*!< [7] Live USB differential receiver JSTATE
02016                                         * signal */
02017     } B;
02018 } hw_usb_ctl_t;
02019 
02020 /*!
02021  * @name Constants and macros for entire USB_CTL register
02022  */
02023 /*@{*/
02024 #define HW_USB_CTL_ADDR(x)       ((x) + 0x94U)
02025 
02026 #define HW_USB_CTL(x)            (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR(x))
02027 #define HW_USB_CTL_RD(x)         (ADDRESS_READ(hw_usb_ctl_t, HW_USB_CTL_ADDR(x)))
02028 #define HW_USB_CTL_WR(x, v)      (ADDRESS_WRITE(hw_usb_ctl_t, HW_USB_CTL_ADDR(x), v))
02029 #define HW_USB_CTL_SET(x, v)     (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) |  (v)))
02030 #define HW_USB_CTL_CLR(x, v)     (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) & ~(v)))
02031 #define HW_USB_CTL_TOG(x, v)     (HW_USB_CTL_WR(x, HW_USB_CTL_RD(x) ^  (v)))
02032 /*@}*/
02033 
02034 /*
02035  * Constants & macros for individual USB_CTL bitfields
02036  */
02037 
02038 /*!
02039  * @name Register USB_CTL, field USBENSOFEN[0] (RW)
02040  *
02041  * Setting this bit enables the USB-FS to operate; clearing it disables the
02042  * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
02043  * Therefore, setting this bit resets much of the logic in the SIE. When host mode
02044  * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
02045  *
02046  * Values:
02047  * - 0 - Disables the USB Module.
02048  * - 1 - Enables the USB Module.
02049  */
02050 /*@{*/
02051 #define BP_USB_CTL_USBENSOFEN (0U)         /*!< Bit position for USB_CTL_USBENSOFEN. */
02052 #define BM_USB_CTL_USBENSOFEN (0x01U)      /*!< Bit mask for USB_CTL_USBENSOFEN. */
02053 #define BS_USB_CTL_USBENSOFEN (1U)         /*!< Bit field size in bits for USB_CTL_USBENSOFEN. */
02054 
02055 /*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
02056 #define BR_USB_CTL_USBENSOFEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN)))
02057 
02058 /*! @brief Format value for bitfield USB_CTL_USBENSOFEN. */
02059 #define BF_USB_CTL_USBENSOFEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_USBENSOFEN) & BM_USB_CTL_USBENSOFEN)
02060 
02061 /*! @brief Set the USBENSOFEN field to a new value. */
02062 #define BW_USB_CTL_USBENSOFEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_USBENSOFEN), v))
02063 /*@}*/
02064 
02065 /*!
02066  * @name Register USB_CTL, field ODDRST[1] (RW)
02067  *
02068  * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
02069  * then specifies the EVEN BDT bank.
02070  */
02071 /*@{*/
02072 #define BP_USB_CTL_ODDRST    (1U)          /*!< Bit position for USB_CTL_ODDRST. */
02073 #define BM_USB_CTL_ODDRST    (0x02U)       /*!< Bit mask for USB_CTL_ODDRST. */
02074 #define BS_USB_CTL_ODDRST    (1U)          /*!< Bit field size in bits for USB_CTL_ODDRST. */
02075 
02076 /*! @brief Read current value of the USB_CTL_ODDRST field. */
02077 #define BR_USB_CTL_ODDRST(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST)))
02078 
02079 /*! @brief Format value for bitfield USB_CTL_ODDRST. */
02080 #define BF_USB_CTL_ODDRST(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_ODDRST) & BM_USB_CTL_ODDRST)
02081 
02082 /*! @brief Set the ODDRST field to a new value. */
02083 #define BW_USB_CTL_ODDRST(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_ODDRST), v))
02084 /*@}*/
02085 
02086 /*!
02087  * @name Register USB_CTL, field RESUME[2] (RW)
02088  *
02089  * When set to 1 this bit enables the USB Module to execute resume signaling.
02090  * This allows the USB Module to perform remote wake-up. Software must set RESUME
02091  * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
02092  * bit is set, the USB module appends a Low Speed End of Packet to the Resume
02093  * signaling when the RESUME bit is cleared. For more information on RESUME
02094  * signaling see Section 7.1.4.5 of the USB specification version 1.0.
02095  */
02096 /*@{*/
02097 #define BP_USB_CTL_RESUME    (2U)          /*!< Bit position for USB_CTL_RESUME. */
02098 #define BM_USB_CTL_RESUME    (0x04U)       /*!< Bit mask for USB_CTL_RESUME. */
02099 #define BS_USB_CTL_RESUME    (1U)          /*!< Bit field size in bits for USB_CTL_RESUME. */
02100 
02101 /*! @brief Read current value of the USB_CTL_RESUME field. */
02102 #define BR_USB_CTL_RESUME(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME)))
02103 
02104 /*! @brief Format value for bitfield USB_CTL_RESUME. */
02105 #define BF_USB_CTL_RESUME(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESUME) & BM_USB_CTL_RESUME)
02106 
02107 /*! @brief Set the RESUME field to a new value. */
02108 #define BW_USB_CTL_RESUME(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESUME), v))
02109 /*@}*/
02110 
02111 /*!
02112  * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
02113  *
02114  * When set to 1, this bit enables the USB Module to operate in Host mode. In
02115  * host mode, the USB module performs USB transactions under the programmed control
02116  * of the host processor.
02117  */
02118 /*@{*/
02119 #define BP_USB_CTL_HOSTMODEEN (3U)         /*!< Bit position for USB_CTL_HOSTMODEEN. */
02120 #define BM_USB_CTL_HOSTMODEEN (0x08U)      /*!< Bit mask for USB_CTL_HOSTMODEEN. */
02121 #define BS_USB_CTL_HOSTMODEEN (1U)         /*!< Bit field size in bits for USB_CTL_HOSTMODEEN. */
02122 
02123 /*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
02124 #define BR_USB_CTL_HOSTMODEEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN)))
02125 
02126 /*! @brief Format value for bitfield USB_CTL_HOSTMODEEN. */
02127 #define BF_USB_CTL_HOSTMODEEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_HOSTMODEEN) & BM_USB_CTL_HOSTMODEEN)
02128 
02129 /*! @brief Set the HOSTMODEEN field to a new value. */
02130 #define BW_USB_CTL_HOSTMODEEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_HOSTMODEEN), v))
02131 /*@}*/
02132 
02133 /*!
02134  * @name Register USB_CTL, field RESET[4] (RW)
02135  *
02136  * Setting this bit enables the USB Module to generate USB reset signaling. This
02137  * allows the USB Module to reset USB peripherals. This control signal is only
02138  * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
02139  * required amount of time and then clear it to 0 to end reset signaling. For more
02140  * information on reset signaling see Section 7.1.4.3 of the USB specification version
02141  * 1.0.
02142  */
02143 /*@{*/
02144 #define BP_USB_CTL_RESET     (4U)          /*!< Bit position for USB_CTL_RESET. */
02145 #define BM_USB_CTL_RESET     (0x10U)       /*!< Bit mask for USB_CTL_RESET. */
02146 #define BS_USB_CTL_RESET     (1U)          /*!< Bit field size in bits for USB_CTL_RESET. */
02147 
02148 /*! @brief Read current value of the USB_CTL_RESET field. */
02149 #define BR_USB_CTL_RESET(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET)))
02150 
02151 /*! @brief Format value for bitfield USB_CTL_RESET. */
02152 #define BF_USB_CTL_RESET(v)  ((uint8_t)((uint8_t)(v) << BP_USB_CTL_RESET) & BM_USB_CTL_RESET)
02153 
02154 /*! @brief Set the RESET field to a new value. */
02155 #define BW_USB_CTL_RESET(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_RESET), v))
02156 /*@}*/
02157 
02158 /*!
02159  * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
02160  *
02161  * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
02162  * token. Software must not write more token commands to the Token Register when
02163  * TOKEN_BUSY is set. Software should check this field before writing any tokens
02164  * to the Token Register to ensure that token commands are not lost. In Target
02165  * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
02166  * reception. Clearing this bit allows the SIE to continue token processing. This bit
02167  * is set by the SIE when a SETUP Token is received allowing software to dequeue
02168  * any pending packet transactions in the BDT before resuming token processing.
02169  */
02170 /*@{*/
02171 #define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) /*!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY. */
02172 #define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) /*!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY. */
02173 #define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) /*!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY. */
02174 
02175 /*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
02176 #define BR_USB_CTL_TXSUSPENDTOKENBUSY(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY)))
02177 
02178 /*! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY. */
02179 #define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_TXSUSPENDTOKENBUSY) & BM_USB_CTL_TXSUSPENDTOKENBUSY)
02180 
02181 /*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
02182 #define BW_USB_CTL_TXSUSPENDTOKENBUSY(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_TXSUSPENDTOKENBUSY), v))
02183 /*@}*/
02184 
02185 /*!
02186  * @name Register USB_CTL, field SE0[6] (RW)
02187  */
02188 /*@{*/
02189 #define BP_USB_CTL_SE0       (6U)          /*!< Bit position for USB_CTL_SE0. */
02190 #define BM_USB_CTL_SE0       (0x40U)       /*!< Bit mask for USB_CTL_SE0. */
02191 #define BS_USB_CTL_SE0       (1U)          /*!< Bit field size in bits for USB_CTL_SE0. */
02192 
02193 /*! @brief Read current value of the USB_CTL_SE0 field. */
02194 #define BR_USB_CTL_SE0(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0)))
02195 
02196 /*! @brief Format value for bitfield USB_CTL_SE0. */
02197 #define BF_USB_CTL_SE0(v)    ((uint8_t)((uint8_t)(v) << BP_USB_CTL_SE0) & BM_USB_CTL_SE0)
02198 
02199 /*! @brief Set the SE0 field to a new value. */
02200 #define BW_USB_CTL_SE0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_SE0), v))
02201 /*@}*/
02202 
02203 /*!
02204  * @name Register USB_CTL, field JSTATE[7] (RW)
02205  *
02206  * The polarity of this signal is affected by the current state of LSEN .
02207  */
02208 /*@{*/
02209 #define BP_USB_CTL_JSTATE    (7U)          /*!< Bit position for USB_CTL_JSTATE. */
02210 #define BM_USB_CTL_JSTATE    (0x80U)       /*!< Bit mask for USB_CTL_JSTATE. */
02211 #define BS_USB_CTL_JSTATE    (1U)          /*!< Bit field size in bits for USB_CTL_JSTATE. */
02212 
02213 /*! @brief Read current value of the USB_CTL_JSTATE field. */
02214 #define BR_USB_CTL_JSTATE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE)))
02215 
02216 /*! @brief Format value for bitfield USB_CTL_JSTATE. */
02217 #define BF_USB_CTL_JSTATE(v) ((uint8_t)((uint8_t)(v) << BP_USB_CTL_JSTATE) & BM_USB_CTL_JSTATE)
02218 
02219 /*! @brief Set the JSTATE field to a new value. */
02220 #define BW_USB_CTL_JSTATE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CTL_ADDR(x), BP_USB_CTL_JSTATE), v))
02221 /*@}*/
02222 
02223 /*******************************************************************************
02224  * HW_USB_ADDR - Address register
02225  ******************************************************************************/
02226 
02227 /*!
02228  * @brief HW_USB_ADDR - Address register (RW)
02229  *
02230  * Reset value: 0x00U
02231  *
02232  * Holds the unique USB address that the USB module decodes when in Peripheral
02233  * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
02234  * transmits this address with a TOKEN packet. This enables the USB module to
02235  * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
02236  * The Address register is reset to 0x00 after the reset input becomes active or
02237  * the USB module decodes a USB reset signal. This action initializes the Address
02238  * register to decode address 0x00 as required by the USB specification.
02239  */
02240 typedef union _hw_usb_addr
02241 {
02242     uint8_t U;
02243     struct _hw_usb_addr_bitfields
02244     {
02245         uint8_t ADDR : 7;              /*!< [6:0] USB Address */
02246         uint8_t LSEN : 1;              /*!< [7] Low Speed Enable bit */
02247     } B;
02248 } hw_usb_addr_t;
02249 
02250 /*!
02251  * @name Constants and macros for entire USB_ADDR register
02252  */
02253 /*@{*/
02254 #define HW_USB_ADDR_ADDR(x)      ((x) + 0x98U)
02255 
02256 #define HW_USB_ADDR(x)           (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR(x))
02257 #define HW_USB_ADDR_RD(x)        (ADDRESS_READ(hw_usb_addr_t, HW_USB_ADDR_ADDR(x)))
02258 #define HW_USB_ADDR_WR(x, v)     (ADDRESS_WRITE(hw_usb_addr_t, HW_USB_ADDR_ADDR(x), v))
02259 #define HW_USB_ADDR_SET(x, v)    (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) |  (v)))
02260 #define HW_USB_ADDR_CLR(x, v)    (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) & ~(v)))
02261 #define HW_USB_ADDR_TOG(x, v)    (HW_USB_ADDR_WR(x, HW_USB_ADDR_RD(x) ^  (v)))
02262 /*@}*/
02263 
02264 /*
02265  * Constants & macros for individual USB_ADDR bitfields
02266  */
02267 
02268 /*!
02269  * @name Register USB_ADDR, field ADDR[6:0] (RW)
02270  *
02271  * Defines the USB address that the USB module decodes in peripheral mode, or
02272  * transmits when in host mode.
02273  */
02274 /*@{*/
02275 #define BP_USB_ADDR_ADDR     (0U)          /*!< Bit position for USB_ADDR_ADDR. */
02276 #define BM_USB_ADDR_ADDR     (0x7FU)       /*!< Bit mask for USB_ADDR_ADDR. */
02277 #define BS_USB_ADDR_ADDR     (7U)          /*!< Bit field size in bits for USB_ADDR_ADDR. */
02278 
02279 /*! @brief Read current value of the USB_ADDR_ADDR field. */
02280 #define BR_USB_ADDR_ADDR(x)  (UNION_READ(hw_usb_addr_t, HW_USB_ADDR_ADDR(x), U, B.ADDR))
02281 
02282 /*! @brief Format value for bitfield USB_ADDR_ADDR. */
02283 #define BF_USB_ADDR_ADDR(v)  ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_ADDR) & BM_USB_ADDR_ADDR)
02284 
02285 /*! @brief Set the ADDR field to a new value. */
02286 #define BW_USB_ADDR_ADDR(x, v) (HW_USB_ADDR_WR(x, (HW_USB_ADDR_RD(x) & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v)))
02287 /*@}*/
02288 
02289 /*!
02290  * @name Register USB_ADDR, field LSEN[7] (RW)
02291  *
02292  * Informs the USB module that the next token command written to the token
02293  * register must be performed at low speed. This enables the USB module to perform the
02294  * necessary preamble required for low-speed data transmissions.
02295  */
02296 /*@{*/
02297 #define BP_USB_ADDR_LSEN     (7U)          /*!< Bit position for USB_ADDR_LSEN. */
02298 #define BM_USB_ADDR_LSEN     (0x80U)       /*!< Bit mask for USB_ADDR_LSEN. */
02299 #define BS_USB_ADDR_LSEN     (1U)          /*!< Bit field size in bits for USB_ADDR_LSEN. */
02300 
02301 /*! @brief Read current value of the USB_ADDR_LSEN field. */
02302 #define BR_USB_ADDR_LSEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN)))
02303 
02304 /*! @brief Format value for bitfield USB_ADDR_LSEN. */
02305 #define BF_USB_ADDR_LSEN(v)  ((uint8_t)((uint8_t)(v) << BP_USB_ADDR_LSEN) & BM_USB_ADDR_LSEN)
02306 
02307 /*! @brief Set the LSEN field to a new value. */
02308 #define BW_USB_ADDR_LSEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ADDR_ADDR(x), BP_USB_ADDR_LSEN), v))
02309 /*@}*/
02310 
02311 /*******************************************************************************
02312  * HW_USB_BDTPAGE1 - BDT Page register 1
02313  ******************************************************************************/
02314 
02315 /*!
02316  * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW)
02317  *
02318  * Reset value: 0x00U
02319  *
02320  * Provides address bits 15 through 9 of the base address where the current
02321  * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
02322  * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
02323  * bits 8 through 0 of the base address are always zero.
02324  */
02325 typedef union _hw_usb_bdtpage1
02326 {
02327     uint8_t U;
02328     struct _hw_usb_bdtpage1_bitfields
02329     {
02330         uint8_t RESERVED0 : 1;         /*!< [0]  */
02331         uint8_t BDTBA : 7;             /*!< [7:1]  */
02332     } B;
02333 } hw_usb_bdtpage1_t;
02334 
02335 /*!
02336  * @name Constants and macros for entire USB_BDTPAGE1 register
02337  */
02338 /*@{*/
02339 #define HW_USB_BDTPAGE1_ADDR(x)  ((x) + 0x9CU)
02340 
02341 #define HW_USB_BDTPAGE1(x)       (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR(x))
02342 #define HW_USB_BDTPAGE1_RD(x)    (ADDRESS_READ(hw_usb_bdtpage1_t, HW_USB_BDTPAGE1_ADDR(x)))
02343 #define HW_USB_BDTPAGE1_WR(x, v) (ADDRESS_WRITE(hw_usb_bdtpage1_t, HW_USB_BDTPAGE1_ADDR(x), v))
02344 #define HW_USB_BDTPAGE1_SET(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) |  (v)))
02345 #define HW_USB_BDTPAGE1_CLR(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) & ~(v)))
02346 #define HW_USB_BDTPAGE1_TOG(x, v) (HW_USB_BDTPAGE1_WR(x, HW_USB_BDTPAGE1_RD(x) ^  (v)))
02347 /*@}*/
02348 
02349 /*
02350  * Constants & macros for individual USB_BDTPAGE1 bitfields
02351  */
02352 
02353 /*!
02354  * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
02355  *
02356  * Provides address bits 15 through 9 of the BDT base address.
02357  */
02358 /*@{*/
02359 #define BP_USB_BDTPAGE1_BDTBA (1U)         /*!< Bit position for USB_BDTPAGE1_BDTBA. */
02360 #define BM_USB_BDTPAGE1_BDTBA (0xFEU)      /*!< Bit mask for USB_BDTPAGE1_BDTBA. */
02361 #define BS_USB_BDTPAGE1_BDTBA (7U)         /*!< Bit field size in bits for USB_BDTPAGE1_BDTBA. */
02362 
02363 /*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
02364 #define BR_USB_BDTPAGE1_BDTBA(x) (UNION_READ(hw_usb_bdtpage1_t, HW_USB_BDTPAGE1_ADDR(x), U, B.BDTBA))
02365 
02366 /*! @brief Format value for bitfield USB_BDTPAGE1_BDTBA. */
02367 #define BF_USB_BDTPAGE1_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE1_BDTBA) & BM_USB_BDTPAGE1_BDTBA)
02368 
02369 /*! @brief Set the BDTBA field to a new value. */
02370 #define BW_USB_BDTPAGE1_BDTBA(x, v) (HW_USB_BDTPAGE1_WR(x, (HW_USB_BDTPAGE1_RD(x) & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v)))
02371 /*@}*/
02372 
02373 /*******************************************************************************
02374  * HW_USB_FRMNUML - Frame Number register Low
02375  ******************************************************************************/
02376 
02377 /*!
02378  * @brief HW_USB_FRMNUML - Frame Number register Low (RW)
02379  *
02380  * Reset value: 0x00U
02381  *
02382  * The Frame Number registers (low and high) contain the 11-bit frame number.
02383  * These registers are updated with the current frame number whenever a SOF TOKEN
02384  * is received.
02385  */
02386 typedef union _hw_usb_frmnuml
02387 {
02388     uint8_t U;
02389     struct _hw_usb_frmnuml_bitfields
02390     {
02391         uint8_t FRM : 8;               /*!< [7:0]  */
02392     } B;
02393 } hw_usb_frmnuml_t;
02394 
02395 /*!
02396  * @name Constants and macros for entire USB_FRMNUML register
02397  */
02398 /*@{*/
02399 #define HW_USB_FRMNUML_ADDR(x)   ((x) + 0xA0U)
02400 
02401 #define HW_USB_FRMNUML(x)        (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR(x))
02402 #define HW_USB_FRMNUML_RD(x)     (ADDRESS_READ(hw_usb_frmnuml_t, HW_USB_FRMNUML_ADDR(x)))
02403 #define HW_USB_FRMNUML_WR(x, v)  (ADDRESS_WRITE(hw_usb_frmnuml_t, HW_USB_FRMNUML_ADDR(x), v))
02404 #define HW_USB_FRMNUML_SET(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) |  (v)))
02405 #define HW_USB_FRMNUML_CLR(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) & ~(v)))
02406 #define HW_USB_FRMNUML_TOG(x, v) (HW_USB_FRMNUML_WR(x, HW_USB_FRMNUML_RD(x) ^  (v)))
02407 /*@}*/
02408 
02409 /*
02410  * Constants & macros for individual USB_FRMNUML bitfields
02411  */
02412 
02413 /*!
02414  * @name Register USB_FRMNUML, field FRM[7:0] (RW)
02415  *
02416  * This 8-bit field and the 3-bit field in the Frame Number Register High are
02417  * used to compute the address where the current Buffer Descriptor Table (BDT)
02418  * resides in system memory.
02419  */
02420 /*@{*/
02421 #define BP_USB_FRMNUML_FRM   (0U)          /*!< Bit position for USB_FRMNUML_FRM. */
02422 #define BM_USB_FRMNUML_FRM   (0xFFU)       /*!< Bit mask for USB_FRMNUML_FRM. */
02423 #define BS_USB_FRMNUML_FRM   (8U)          /*!< Bit field size in bits for USB_FRMNUML_FRM. */
02424 
02425 /*! @brief Read current value of the USB_FRMNUML_FRM field. */
02426 #define BR_USB_FRMNUML_FRM(x) (HW_USB_FRMNUML(x).U)
02427 
02428 /*! @brief Format value for bitfield USB_FRMNUML_FRM. */
02429 #define BF_USB_FRMNUML_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUML_FRM) & BM_USB_FRMNUML_FRM)
02430 
02431 /*! @brief Set the FRM field to a new value. */
02432 #define BW_USB_FRMNUML_FRM(x, v) (HW_USB_FRMNUML_WR(x, v))
02433 /*@}*/
02434 
02435 /*******************************************************************************
02436  * HW_USB_FRMNUMH - Frame Number register High
02437  ******************************************************************************/
02438 
02439 /*!
02440  * @brief HW_USB_FRMNUMH - Frame Number register High (RW)
02441  *
02442  * Reset value: 0x00U
02443  *
02444  * The Frame Number registers (low and high) contain the 11-bit frame number.
02445  * These registers are updated with the current frame number whenever a SOF TOKEN
02446  * is received.
02447  */
02448 typedef union _hw_usb_frmnumh
02449 {
02450     uint8_t U;
02451     struct _hw_usb_frmnumh_bitfields
02452     {
02453         uint8_t FRM : 3;               /*!< [2:0]  */
02454         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
02455     } B;
02456 } hw_usb_frmnumh_t;
02457 
02458 /*!
02459  * @name Constants and macros for entire USB_FRMNUMH register
02460  */
02461 /*@{*/
02462 #define HW_USB_FRMNUMH_ADDR(x)   ((x) + 0xA4U)
02463 
02464 #define HW_USB_FRMNUMH(x)        (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR(x))
02465 #define HW_USB_FRMNUMH_RD(x)     (ADDRESS_READ(hw_usb_frmnumh_t, HW_USB_FRMNUMH_ADDR(x)))
02466 #define HW_USB_FRMNUMH_WR(x, v)  (ADDRESS_WRITE(hw_usb_frmnumh_t, HW_USB_FRMNUMH_ADDR(x), v))
02467 #define HW_USB_FRMNUMH_SET(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) |  (v)))
02468 #define HW_USB_FRMNUMH_CLR(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) & ~(v)))
02469 #define HW_USB_FRMNUMH_TOG(x, v) (HW_USB_FRMNUMH_WR(x, HW_USB_FRMNUMH_RD(x) ^  (v)))
02470 /*@}*/
02471 
02472 /*
02473  * Constants & macros for individual USB_FRMNUMH bitfields
02474  */
02475 
02476 /*!
02477  * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
02478  *
02479  * This 3-bit field and the 8-bit field in the Frame Number Register Low are
02480  * used to compute the address where the current Buffer Descriptor Table (BDT)
02481  * resides in system memory.
02482  */
02483 /*@{*/
02484 #define BP_USB_FRMNUMH_FRM   (0U)          /*!< Bit position for USB_FRMNUMH_FRM. */
02485 #define BM_USB_FRMNUMH_FRM   (0x07U)       /*!< Bit mask for USB_FRMNUMH_FRM. */
02486 #define BS_USB_FRMNUMH_FRM   (3U)          /*!< Bit field size in bits for USB_FRMNUMH_FRM. */
02487 
02488 /*! @brief Read current value of the USB_FRMNUMH_FRM field. */
02489 #define BR_USB_FRMNUMH_FRM(x) (UNION_READ(hw_usb_frmnumh_t, HW_USB_FRMNUMH_ADDR(x), U, B.FRM))
02490 
02491 /*! @brief Format value for bitfield USB_FRMNUMH_FRM. */
02492 #define BF_USB_FRMNUMH_FRM(v) ((uint8_t)((uint8_t)(v) << BP_USB_FRMNUMH_FRM) & BM_USB_FRMNUMH_FRM)
02493 
02494 /*! @brief Set the FRM field to a new value. */
02495 #define BW_USB_FRMNUMH_FRM(x, v) (HW_USB_FRMNUMH_WR(x, (HW_USB_FRMNUMH_RD(x) & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v)))
02496 /*@}*/
02497 
02498 /*******************************************************************************
02499  * HW_USB_TOKEN - Token register
02500  ******************************************************************************/
02501 
02502 /*!
02503  * @brief HW_USB_TOKEN - Token register (RW)
02504  *
02505  * Reset value: 0x00U
02506  *
02507  * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
02508  * software needs to execute a USB transaction to a peripheral, it writes the
02509  * TOKEN type and endpoint to this register. After this register has been written,
02510  * the USB module begins the specified USB transaction to the address contained in
02511  * the address register. The processor core must always check that the
02512  * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
02513  * This ensures that the token commands are not overwritten before they can be
02514  * executed. The address register and endpoint control register 0 are also used when
02515  * performing a token command and therefore must also be written before the
02516  * Token Register. The address register is used to select the USB peripheral address
02517  * transmitted by the token command. The endpoint control register determines the
02518  * handshake and retry policies used during the transfer.
02519  */
02520 typedef union _hw_usb_token
02521 {
02522     uint8_t U;
02523     struct _hw_usb_token_bitfields
02524     {
02525         uint8_t TOKENENDPT : 4;        /*!< [3:0]  */
02526         uint8_t TOKENPID : 4;          /*!< [7:4]  */
02527     } B;
02528 } hw_usb_token_t;
02529 
02530 /*!
02531  * @name Constants and macros for entire USB_TOKEN register
02532  */
02533 /*@{*/
02534 #define HW_USB_TOKEN_ADDR(x)     ((x) + 0xA8U)
02535 
02536 #define HW_USB_TOKEN(x)          (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR(x))
02537 #define HW_USB_TOKEN_RD(x)       (ADDRESS_READ(hw_usb_token_t, HW_USB_TOKEN_ADDR(x)))
02538 #define HW_USB_TOKEN_WR(x, v)    (ADDRESS_WRITE(hw_usb_token_t, HW_USB_TOKEN_ADDR(x), v))
02539 #define HW_USB_TOKEN_SET(x, v)   (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) |  (v)))
02540 #define HW_USB_TOKEN_CLR(x, v)   (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) & ~(v)))
02541 #define HW_USB_TOKEN_TOG(x, v)   (HW_USB_TOKEN_WR(x, HW_USB_TOKEN_RD(x) ^  (v)))
02542 /*@}*/
02543 
02544 /*
02545  * Constants & macros for individual USB_TOKEN bitfields
02546  */
02547 
02548 /*!
02549  * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
02550  *
02551  * Holds the Endpoint address for the token command. The four bit value written
02552  * must be a valid endpoint.
02553  */
02554 /*@{*/
02555 #define BP_USB_TOKEN_TOKENENDPT (0U)       /*!< Bit position for USB_TOKEN_TOKENENDPT. */
02556 #define BM_USB_TOKEN_TOKENENDPT (0x0FU)    /*!< Bit mask for USB_TOKEN_TOKENENDPT. */
02557 #define BS_USB_TOKEN_TOKENENDPT (4U)       /*!< Bit field size in bits for USB_TOKEN_TOKENENDPT. */
02558 
02559 /*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
02560 #define BR_USB_TOKEN_TOKENENDPT(x) (UNION_READ(hw_usb_token_t, HW_USB_TOKEN_ADDR(x), U, B.TOKENENDPT))
02561 
02562 /*! @brief Format value for bitfield USB_TOKEN_TOKENENDPT. */
02563 #define BF_USB_TOKEN_TOKENENDPT(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENENDPT) & BM_USB_TOKEN_TOKENENDPT)
02564 
02565 /*! @brief Set the TOKENENDPT field to a new value. */
02566 #define BW_USB_TOKEN_TOKENENDPT(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v)))
02567 /*@}*/
02568 
02569 /*!
02570  * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
02571  *
02572  * Contains the token type executed by the USB module.
02573  *
02574  * Values:
02575  * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction.
02576  * - 1001 - IN Token. USB Module performs an In (RX) transaction.
02577  * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
02578  */
02579 /*@{*/
02580 #define BP_USB_TOKEN_TOKENPID (4U)         /*!< Bit position for USB_TOKEN_TOKENPID. */
02581 #define BM_USB_TOKEN_TOKENPID (0xF0U)      /*!< Bit mask for USB_TOKEN_TOKENPID. */
02582 #define BS_USB_TOKEN_TOKENPID (4U)         /*!< Bit field size in bits for USB_TOKEN_TOKENPID. */
02583 
02584 /*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
02585 #define BR_USB_TOKEN_TOKENPID(x) (UNION_READ(hw_usb_token_t, HW_USB_TOKEN_ADDR(x), U, B.TOKENPID))
02586 
02587 /*! @brief Format value for bitfield USB_TOKEN_TOKENPID. */
02588 #define BF_USB_TOKEN_TOKENPID(v) ((uint8_t)((uint8_t)(v) << BP_USB_TOKEN_TOKENPID) & BM_USB_TOKEN_TOKENPID)
02589 
02590 /*! @brief Set the TOKENPID field to a new value. */
02591 #define BW_USB_TOKEN_TOKENPID(x, v) (HW_USB_TOKEN_WR(x, (HW_USB_TOKEN_RD(x) & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v)))
02592 /*@}*/
02593 
02594 /*******************************************************************************
02595  * HW_USB_SOFTHLD - SOF Threshold register
02596  ******************************************************************************/
02597 
02598 /*!
02599  * @brief HW_USB_SOFTHLD - SOF Threshold register (RW)
02600  *
02601  * Reset value: 0x00U
02602  *
02603  * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
02604  * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
02605  * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
02606  * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
02607  * token is transmitted. The SOF threshold register is used to program the number
02608  * of USB byte times before the SOF to stop initiating token packet transactions.
02609  * This register must be set to a value that ensures that other packets are not
02610  * actively being transmitted when the SOF time counts to zero. When the SOF
02611  * counter reaches the threshold value, no more tokens are transmitted until after the
02612  * SOF has been transmitted. The value programmed into the threshold register
02613  * must reserve enough time to ensure the worst case transaction completes. In
02614  * general the worst case transaction is an IN token followed by a data packet from
02615  * the target followed by the response from the host. The actual time required is
02616  * a function of the maximum packet size on the bus. Typical values for the SOF
02617  * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
02618  * 8-byte packets=18.
02619  */
02620 typedef union _hw_usb_softhld
02621 {
02622     uint8_t U;
02623     struct _hw_usb_softhld_bitfields
02624     {
02625         uint8_t CNT : 8;               /*!< [7:0]  */
02626     } B;
02627 } hw_usb_softhld_t;
02628 
02629 /*!
02630  * @name Constants and macros for entire USB_SOFTHLD register
02631  */
02632 /*@{*/
02633 #define HW_USB_SOFTHLD_ADDR(x)   ((x) + 0xACU)
02634 
02635 #define HW_USB_SOFTHLD(x)        (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR(x))
02636 #define HW_USB_SOFTHLD_RD(x)     (ADDRESS_READ(hw_usb_softhld_t, HW_USB_SOFTHLD_ADDR(x)))
02637 #define HW_USB_SOFTHLD_WR(x, v)  (ADDRESS_WRITE(hw_usb_softhld_t, HW_USB_SOFTHLD_ADDR(x), v))
02638 #define HW_USB_SOFTHLD_SET(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) |  (v)))
02639 #define HW_USB_SOFTHLD_CLR(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) & ~(v)))
02640 #define HW_USB_SOFTHLD_TOG(x, v) (HW_USB_SOFTHLD_WR(x, HW_USB_SOFTHLD_RD(x) ^  (v)))
02641 /*@}*/
02642 
02643 /*
02644  * Constants & macros for individual USB_SOFTHLD bitfields
02645  */
02646 
02647 /*!
02648  * @name Register USB_SOFTHLD, field CNT[7:0] (RW)
02649  *
02650  * Represents the SOF count threshold in byte times.
02651  */
02652 /*@{*/
02653 #define BP_USB_SOFTHLD_CNT   (0U)          /*!< Bit position for USB_SOFTHLD_CNT. */
02654 #define BM_USB_SOFTHLD_CNT   (0xFFU)       /*!< Bit mask for USB_SOFTHLD_CNT. */
02655 #define BS_USB_SOFTHLD_CNT   (8U)          /*!< Bit field size in bits for USB_SOFTHLD_CNT. */
02656 
02657 /*! @brief Read current value of the USB_SOFTHLD_CNT field. */
02658 #define BR_USB_SOFTHLD_CNT(x) (HW_USB_SOFTHLD(x).U)
02659 
02660 /*! @brief Format value for bitfield USB_SOFTHLD_CNT. */
02661 #define BF_USB_SOFTHLD_CNT(v) ((uint8_t)((uint8_t)(v) << BP_USB_SOFTHLD_CNT) & BM_USB_SOFTHLD_CNT)
02662 
02663 /*! @brief Set the CNT field to a new value. */
02664 #define BW_USB_SOFTHLD_CNT(x, v) (HW_USB_SOFTHLD_WR(x, v))
02665 /*@}*/
02666 
02667 /*******************************************************************************
02668  * HW_USB_BDTPAGE2 - BDT Page Register 2
02669  ******************************************************************************/
02670 
02671 /*!
02672  * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW)
02673  *
02674  * Reset value: 0x00U
02675  *
02676  * Contains an 8-bit value used to compute the address where the current Buffer
02677  * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
02678  */
02679 typedef union _hw_usb_bdtpage2
02680 {
02681     uint8_t U;
02682     struct _hw_usb_bdtpage2_bitfields
02683     {
02684         uint8_t BDTBA : 8;             /*!< [7:0]  */
02685     } B;
02686 } hw_usb_bdtpage2_t;
02687 
02688 /*!
02689  * @name Constants and macros for entire USB_BDTPAGE2 register
02690  */
02691 /*@{*/
02692 #define HW_USB_BDTPAGE2_ADDR(x)  ((x) + 0xB0U)
02693 
02694 #define HW_USB_BDTPAGE2(x)       (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR(x))
02695 #define HW_USB_BDTPAGE2_RD(x)    (ADDRESS_READ(hw_usb_bdtpage2_t, HW_USB_BDTPAGE2_ADDR(x)))
02696 #define HW_USB_BDTPAGE2_WR(x, v) (ADDRESS_WRITE(hw_usb_bdtpage2_t, HW_USB_BDTPAGE2_ADDR(x), v))
02697 #define HW_USB_BDTPAGE2_SET(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) |  (v)))
02698 #define HW_USB_BDTPAGE2_CLR(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) & ~(v)))
02699 #define HW_USB_BDTPAGE2_TOG(x, v) (HW_USB_BDTPAGE2_WR(x, HW_USB_BDTPAGE2_RD(x) ^  (v)))
02700 /*@}*/
02701 
02702 /*
02703  * Constants & macros for individual USB_BDTPAGE2 bitfields
02704  */
02705 
02706 /*!
02707  * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW)
02708  *
02709  * Provides address bits 23 through 16 of the BDT base address that defines the
02710  * location of Buffer Descriptor Table resides in system memory.
02711  */
02712 /*@{*/
02713 #define BP_USB_BDTPAGE2_BDTBA (0U)         /*!< Bit position for USB_BDTPAGE2_BDTBA. */
02714 #define BM_USB_BDTPAGE2_BDTBA (0xFFU)      /*!< Bit mask for USB_BDTPAGE2_BDTBA. */
02715 #define BS_USB_BDTPAGE2_BDTBA (8U)         /*!< Bit field size in bits for USB_BDTPAGE2_BDTBA. */
02716 
02717 /*! @brief Read current value of the USB_BDTPAGE2_BDTBA field. */
02718 #define BR_USB_BDTPAGE2_BDTBA(x) (HW_USB_BDTPAGE2(x).U)
02719 
02720 /*! @brief Format value for bitfield USB_BDTPAGE2_BDTBA. */
02721 #define BF_USB_BDTPAGE2_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE2_BDTBA) & BM_USB_BDTPAGE2_BDTBA)
02722 
02723 /*! @brief Set the BDTBA field to a new value. */
02724 #define BW_USB_BDTPAGE2_BDTBA(x, v) (HW_USB_BDTPAGE2_WR(x, v))
02725 /*@}*/
02726 
02727 /*******************************************************************************
02728  * HW_USB_BDTPAGE3 - BDT Page Register 3
02729  ******************************************************************************/
02730 
02731 /*!
02732  * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW)
02733  *
02734  * Reset value: 0x00U
02735  *
02736  * Contains an 8-bit value used to compute the address where the current Buffer
02737  * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
02738  */
02739 typedef union _hw_usb_bdtpage3
02740 {
02741     uint8_t U;
02742     struct _hw_usb_bdtpage3_bitfields
02743     {
02744         uint8_t BDTBA : 8;             /*!< [7:0]  */
02745     } B;
02746 } hw_usb_bdtpage3_t;
02747 
02748 /*!
02749  * @name Constants and macros for entire USB_BDTPAGE3 register
02750  */
02751 /*@{*/
02752 #define HW_USB_BDTPAGE3_ADDR(x)  ((x) + 0xB4U)
02753 
02754 #define HW_USB_BDTPAGE3(x)       (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR(x))
02755 #define HW_USB_BDTPAGE3_RD(x)    (ADDRESS_READ(hw_usb_bdtpage3_t, HW_USB_BDTPAGE3_ADDR(x)))
02756 #define HW_USB_BDTPAGE3_WR(x, v) (ADDRESS_WRITE(hw_usb_bdtpage3_t, HW_USB_BDTPAGE3_ADDR(x), v))
02757 #define HW_USB_BDTPAGE3_SET(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) |  (v)))
02758 #define HW_USB_BDTPAGE3_CLR(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) & ~(v)))
02759 #define HW_USB_BDTPAGE3_TOG(x, v) (HW_USB_BDTPAGE3_WR(x, HW_USB_BDTPAGE3_RD(x) ^  (v)))
02760 /*@}*/
02761 
02762 /*
02763  * Constants & macros for individual USB_BDTPAGE3 bitfields
02764  */
02765 
02766 /*!
02767  * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW)
02768  *
02769  * Provides address bits 31 through 24 of the BDT base address that defines the
02770  * location of Buffer Descriptor Table resides in system memory.
02771  */
02772 /*@{*/
02773 #define BP_USB_BDTPAGE3_BDTBA (0U)         /*!< Bit position for USB_BDTPAGE3_BDTBA. */
02774 #define BM_USB_BDTPAGE3_BDTBA (0xFFU)      /*!< Bit mask for USB_BDTPAGE3_BDTBA. */
02775 #define BS_USB_BDTPAGE3_BDTBA (8U)         /*!< Bit field size in bits for USB_BDTPAGE3_BDTBA. */
02776 
02777 /*! @brief Read current value of the USB_BDTPAGE3_BDTBA field. */
02778 #define BR_USB_BDTPAGE3_BDTBA(x) (HW_USB_BDTPAGE3(x).U)
02779 
02780 /*! @brief Format value for bitfield USB_BDTPAGE3_BDTBA. */
02781 #define BF_USB_BDTPAGE3_BDTBA(v) ((uint8_t)((uint8_t)(v) << BP_USB_BDTPAGE3_BDTBA) & BM_USB_BDTPAGE3_BDTBA)
02782 
02783 /*! @brief Set the BDTBA field to a new value. */
02784 #define BW_USB_BDTPAGE3_BDTBA(x, v) (HW_USB_BDTPAGE3_WR(x, v))
02785 /*@}*/
02786 
02787 /*******************************************************************************
02788  * HW_USB_ENDPTn - Endpoint Control register
02789  ******************************************************************************/
02790 
02791 /*!
02792  * @brief HW_USB_ENDPTn - Endpoint Control register (RW)
02793  *
02794  * Reset value: 0x00U
02795  *
02796  * Contains the endpoint control bits for each of the 16 endpoints available
02797  * within the USB module for a decoded address. The format for these registers is
02798  * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
02799  * pipe 0, which is required for all USB functions. Therefore, after a USBRST
02800  * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
02801  * ENDPT0 is used to determine the handshake, retry and low speed
02802  * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
02803  * bit should be 1. For Isochronous transfers it should be 0. Common values to
02804  * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
02805  * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
02806  * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
02807  * The endpoint enable/direction control is defined in the following table.
02808  * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
02809  * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
02810  * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
02811  * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
02812  * transfers.
02813  */
02814 typedef union _hw_usb_endptn
02815 {
02816     uint8_t U;
02817     struct _hw_usb_endptn_bitfields
02818     {
02819         uint8_t EPHSHK : 1;            /*!< [0]  */
02820         uint8_t EPSTALL : 1;           /*!< [1]  */
02821         uint8_t EPTXEN : 1;            /*!< [2]  */
02822         uint8_t EPRXEN : 1;            /*!< [3]  */
02823         uint8_t EPCTLDIS : 1;          /*!< [4]  */
02824         uint8_t RESERVED0 : 1;         /*!< [5]  */
02825         uint8_t RETRYDIS : 1;          /*!< [6]  */
02826         uint8_t HOSTWOHUB : 1;         /*!< [7]  */
02827     } B;
02828 } hw_usb_endptn_t;
02829 
02830 /*!
02831  * @name Constants and macros for entire USB_ENDPTn register
02832  */
02833 /*@{*/
02834 #define HW_USB_ENDPTn_COUNT (16U)
02835 
02836 #define HW_USB_ENDPTn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n)))
02837 
02838 #define HW_USB_ENDPTn(x, n)      (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(x, n))
02839 #define HW_USB_ENDPTn_RD(x, n)   (ADDRESS_READ(hw_usb_endptn_t, HW_USB_ENDPTn_ADDR(x, n)))
02840 #define HW_USB_ENDPTn_WR(x, n, v) (ADDRESS_WRITE(hw_usb_endptn_t, HW_USB_ENDPTn_ADDR(x, n), v))
02841 #define HW_USB_ENDPTn_SET(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) |  (v)))
02842 #define HW_USB_ENDPTn_CLR(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) & ~(v)))
02843 #define HW_USB_ENDPTn_TOG(x, n, v) (HW_USB_ENDPTn_WR(x, n, HW_USB_ENDPTn_RD(x, n) ^  (v)))
02844 /*@}*/
02845 
02846 /*
02847  * Constants & macros for individual USB_ENDPTn bitfields
02848  */
02849 
02850 /*!
02851  * @name Register USB_ENDPTn, field EPHSHK[0] (RW)
02852  *
02853  * When set this bit enables an endpoint to perform handshaking during a
02854  * transaction to this endpoint. This bit is generally 1 unless the endpoint is
02855  * Isochronous.
02856  */
02857 /*@{*/
02858 #define BP_USB_ENDPTn_EPHSHK (0U)          /*!< Bit position for USB_ENDPTn_EPHSHK. */
02859 #define BM_USB_ENDPTn_EPHSHK (0x01U)       /*!< Bit mask for USB_ENDPTn_EPHSHK. */
02860 #define BS_USB_ENDPTn_EPHSHK (1U)          /*!< Bit field size in bits for USB_ENDPTn_EPHSHK. */
02861 
02862 /*! @brief Read current value of the USB_ENDPTn_EPHSHK field. */
02863 #define BR_USB_ENDPTn_EPHSHK(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK)))
02864 
02865 /*! @brief Format value for bitfield USB_ENDPTn_EPHSHK. */
02866 #define BF_USB_ENDPTn_EPHSHK(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPHSHK) & BM_USB_ENDPTn_EPHSHK)
02867 
02868 /*! @brief Set the EPHSHK field to a new value. */
02869 #define BW_USB_ENDPTn_EPHSHK(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPHSHK), v))
02870 /*@}*/
02871 
02872 /*!
02873  * @name Register USB_ENDPTn, field EPSTALL[1] (RW)
02874  *
02875  * When set this bit indicates that the endpoint is called. This bit has
02876  * priority over all other control bits in the EndPoint Enable Register, but it is only
02877  * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
02878  * Module to return a STALL handshake. After an endpoint is stalled it requires
02879  * intervention from the Host Controller.
02880  */
02881 /*@{*/
02882 #define BP_USB_ENDPTn_EPSTALL (1U)         /*!< Bit position for USB_ENDPTn_EPSTALL. */
02883 #define BM_USB_ENDPTn_EPSTALL (0x02U)      /*!< Bit mask for USB_ENDPTn_EPSTALL. */
02884 #define BS_USB_ENDPTn_EPSTALL (1U)         /*!< Bit field size in bits for USB_ENDPTn_EPSTALL. */
02885 
02886 /*! @brief Read current value of the USB_ENDPTn_EPSTALL field. */
02887 #define BR_USB_ENDPTn_EPSTALL(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL)))
02888 
02889 /*! @brief Format value for bitfield USB_ENDPTn_EPSTALL. */
02890 #define BF_USB_ENDPTn_EPSTALL(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPSTALL) & BM_USB_ENDPTn_EPSTALL)
02891 
02892 /*! @brief Set the EPSTALL field to a new value. */
02893 #define BW_USB_ENDPTn_EPSTALL(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPSTALL), v))
02894 /*@}*/
02895 
02896 /*!
02897  * @name Register USB_ENDPTn, field EPTXEN[2] (RW)
02898  *
02899  * This bit, when set, enables the endpoint for TX transfers.
02900  */
02901 /*@{*/
02902 #define BP_USB_ENDPTn_EPTXEN (2U)          /*!< Bit position for USB_ENDPTn_EPTXEN. */
02903 #define BM_USB_ENDPTn_EPTXEN (0x04U)       /*!< Bit mask for USB_ENDPTn_EPTXEN. */
02904 #define BS_USB_ENDPTn_EPTXEN (1U)          /*!< Bit field size in bits for USB_ENDPTn_EPTXEN. */
02905 
02906 /*! @brief Read current value of the USB_ENDPTn_EPTXEN field. */
02907 #define BR_USB_ENDPTn_EPTXEN(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN)))
02908 
02909 /*! @brief Format value for bitfield USB_ENDPTn_EPTXEN. */
02910 #define BF_USB_ENDPTn_EPTXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPTXEN) & BM_USB_ENDPTn_EPTXEN)
02911 
02912 /*! @brief Set the EPTXEN field to a new value. */
02913 #define BW_USB_ENDPTn_EPTXEN(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPTXEN), v))
02914 /*@}*/
02915 
02916 /*!
02917  * @name Register USB_ENDPTn, field EPRXEN[3] (RW)
02918  *
02919  * This bit, when set, enables the endpoint for RX transfers.
02920  */
02921 /*@{*/
02922 #define BP_USB_ENDPTn_EPRXEN (3U)          /*!< Bit position for USB_ENDPTn_EPRXEN. */
02923 #define BM_USB_ENDPTn_EPRXEN (0x08U)       /*!< Bit mask for USB_ENDPTn_EPRXEN. */
02924 #define BS_USB_ENDPTn_EPRXEN (1U)          /*!< Bit field size in bits for USB_ENDPTn_EPRXEN. */
02925 
02926 /*! @brief Read current value of the USB_ENDPTn_EPRXEN field. */
02927 #define BR_USB_ENDPTn_EPRXEN(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN)))
02928 
02929 /*! @brief Format value for bitfield USB_ENDPTn_EPRXEN. */
02930 #define BF_USB_ENDPTn_EPRXEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPRXEN) & BM_USB_ENDPTn_EPRXEN)
02931 
02932 /*! @brief Set the EPRXEN field to a new value. */
02933 #define BW_USB_ENDPTn_EPRXEN(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPRXEN), v))
02934 /*@}*/
02935 
02936 /*!
02937  * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW)
02938  *
02939  * This bit, when set, disables control (SETUP) transfers. When cleared, control
02940  * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
02941  * are also set.
02942  */
02943 /*@{*/
02944 #define BP_USB_ENDPTn_EPCTLDIS (4U)        /*!< Bit position for USB_ENDPTn_EPCTLDIS. */
02945 #define BM_USB_ENDPTn_EPCTLDIS (0x10U)     /*!< Bit mask for USB_ENDPTn_EPCTLDIS. */
02946 #define BS_USB_ENDPTn_EPCTLDIS (1U)        /*!< Bit field size in bits for USB_ENDPTn_EPCTLDIS. */
02947 
02948 /*! @brief Read current value of the USB_ENDPTn_EPCTLDIS field. */
02949 #define BR_USB_ENDPTn_EPCTLDIS(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS)))
02950 
02951 /*! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS. */
02952 #define BF_USB_ENDPTn_EPCTLDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_EPCTLDIS) & BM_USB_ENDPTn_EPCTLDIS)
02953 
02954 /*! @brief Set the EPCTLDIS field to a new value. */
02955 #define BW_USB_ENDPTn_EPCTLDIS(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_EPCTLDIS), v))
02956 /*@}*/
02957 
02958 /*!
02959  * @name Register USB_ENDPTn, field RETRYDIS[6] (RW)
02960  *
02961  * This is a Host mode only bit and is present in the control register for
02962  * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
02963  * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
02964  * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
02965  * this bit is cleared, NAKed transactions are retried in hardware. This bit must
02966  * be set when the host is attempting to poll an interrupt endpoint.
02967  */
02968 /*@{*/
02969 #define BP_USB_ENDPTn_RETRYDIS (6U)        /*!< Bit position for USB_ENDPTn_RETRYDIS. */
02970 #define BM_USB_ENDPTn_RETRYDIS (0x40U)     /*!< Bit mask for USB_ENDPTn_RETRYDIS. */
02971 #define BS_USB_ENDPTn_RETRYDIS (1U)        /*!< Bit field size in bits for USB_ENDPTn_RETRYDIS. */
02972 
02973 /*! @brief Read current value of the USB_ENDPTn_RETRYDIS field. */
02974 #define BR_USB_ENDPTn_RETRYDIS(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS)))
02975 
02976 /*! @brief Format value for bitfield USB_ENDPTn_RETRYDIS. */
02977 #define BF_USB_ENDPTn_RETRYDIS(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_RETRYDIS) & BM_USB_ENDPTn_RETRYDIS)
02978 
02979 /*! @brief Set the RETRYDIS field to a new value. */
02980 #define BW_USB_ENDPTn_RETRYDIS(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_RETRYDIS), v))
02981 /*@}*/
02982 
02983 /*!
02984  * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
02985  *
02986  * This is a Host mode only field and is present in the control register for
02987  * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
02988  * directly connected low speed device. When cleared, the host produces the
02989  * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
02990  * device as required to communicate with a low speed device through a hub.
02991  */
02992 /*@{*/
02993 #define BP_USB_ENDPTn_HOSTWOHUB (7U)       /*!< Bit position for USB_ENDPTn_HOSTWOHUB. */
02994 #define BM_USB_ENDPTn_HOSTWOHUB (0x80U)    /*!< Bit mask for USB_ENDPTn_HOSTWOHUB. */
02995 #define BS_USB_ENDPTn_HOSTWOHUB (1U)       /*!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB. */
02996 
02997 /*! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field. */
02998 #define BR_USB_ENDPTn_HOSTWOHUB(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB)))
02999 
03000 /*! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB. */
03001 #define BF_USB_ENDPTn_HOSTWOHUB(v) ((uint8_t)((uint8_t)(v) << BP_USB_ENDPTn_HOSTWOHUB) & BM_USB_ENDPTn_HOSTWOHUB)
03002 
03003 /*! @brief Set the HOSTWOHUB field to a new value. */
03004 #define BW_USB_ENDPTn_HOSTWOHUB(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_ENDPTn_ADDR(x, n), BP_USB_ENDPTn_HOSTWOHUB), v))
03005 /*@}*/
03006 
03007 /*******************************************************************************
03008  * HW_USB_USBCTRL - USB Control register
03009  ******************************************************************************/
03010 
03011 /*!
03012  * @brief HW_USB_USBCTRL - USB Control register (RW)
03013  *
03014  * Reset value: 0xC0U
03015  */
03016 typedef union _hw_usb_usbctrl
03017 {
03018     uint8_t U;
03019     struct _hw_usb_usbctrl_bitfields
03020     {
03021         uint8_t RESERVED0 : 6;         /*!< [5:0]  */
03022         uint8_t PDE : 1;               /*!< [6]  */
03023         uint8_t SUSP : 1;              /*!< [7]  */
03024     } B;
03025 } hw_usb_usbctrl_t;
03026 
03027 /*!
03028  * @name Constants and macros for entire USB_USBCTRL register
03029  */
03030 /*@{*/
03031 #define HW_USB_USBCTRL_ADDR(x)   ((x) + 0x100U)
03032 
03033 #define HW_USB_USBCTRL(x)        (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR(x))
03034 #define HW_USB_USBCTRL_RD(x)     (ADDRESS_READ(hw_usb_usbctrl_t, HW_USB_USBCTRL_ADDR(x)))
03035 #define HW_USB_USBCTRL_WR(x, v)  (ADDRESS_WRITE(hw_usb_usbctrl_t, HW_USB_USBCTRL_ADDR(x), v))
03036 #define HW_USB_USBCTRL_SET(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) |  (v)))
03037 #define HW_USB_USBCTRL_CLR(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) & ~(v)))
03038 #define HW_USB_USBCTRL_TOG(x, v) (HW_USB_USBCTRL_WR(x, HW_USB_USBCTRL_RD(x) ^  (v)))
03039 /*@}*/
03040 
03041 /*
03042  * Constants & macros for individual USB_USBCTRL bitfields
03043  */
03044 
03045 /*!
03046  * @name Register USB_USBCTRL, field PDE[6] (RW)
03047  *
03048  * Enables the weak pulldowns on the USB transceiver.
03049  *
03050  * Values:
03051  * - 0 - Weak pulldowns are disabled on D+ and D-.
03052  * - 1 - Weak pulldowns are enabled on D+ and D-.
03053  */
03054 /*@{*/
03055 #define BP_USB_USBCTRL_PDE   (6U)          /*!< Bit position for USB_USBCTRL_PDE. */
03056 #define BM_USB_USBCTRL_PDE   (0x40U)       /*!< Bit mask for USB_USBCTRL_PDE. */
03057 #define BS_USB_USBCTRL_PDE   (1U)          /*!< Bit field size in bits for USB_USBCTRL_PDE. */
03058 
03059 /*! @brief Read current value of the USB_USBCTRL_PDE field. */
03060 #define BR_USB_USBCTRL_PDE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE)))
03061 
03062 /*! @brief Format value for bitfield USB_USBCTRL_PDE. */
03063 #define BF_USB_USBCTRL_PDE(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_PDE) & BM_USB_USBCTRL_PDE)
03064 
03065 /*! @brief Set the PDE field to a new value. */
03066 #define BW_USB_USBCTRL_PDE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_PDE), v))
03067 /*@}*/
03068 
03069 /*!
03070  * @name Register USB_USBCTRL, field SUSP[7] (RW)
03071  *
03072  * Places the USB transceiver into the suspend state.
03073  *
03074  * Values:
03075  * - 0 - USB transceiver is not in suspend state.
03076  * - 1 - USB transceiver is in suspend state.
03077  */
03078 /*@{*/
03079 #define BP_USB_USBCTRL_SUSP  (7U)          /*!< Bit position for USB_USBCTRL_SUSP. */
03080 #define BM_USB_USBCTRL_SUSP  (0x80U)       /*!< Bit mask for USB_USBCTRL_SUSP. */
03081 #define BS_USB_USBCTRL_SUSP  (1U)          /*!< Bit field size in bits for USB_USBCTRL_SUSP. */
03082 
03083 /*! @brief Read current value of the USB_USBCTRL_SUSP field. */
03084 #define BR_USB_USBCTRL_SUSP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP)))
03085 
03086 /*! @brief Format value for bitfield USB_USBCTRL_SUSP. */
03087 #define BF_USB_USBCTRL_SUSP(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBCTRL_SUSP) & BM_USB_USBCTRL_SUSP)
03088 
03089 /*! @brief Set the SUSP field to a new value. */
03090 #define BW_USB_USBCTRL_SUSP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_USBCTRL_ADDR(x), BP_USB_USBCTRL_SUSP), v))
03091 /*@}*/
03092 
03093 /*******************************************************************************
03094  * HW_USB_OBSERVE - USB OTG Observe register
03095  ******************************************************************************/
03096 
03097 /*!
03098  * @brief HW_USB_OBSERVE - USB OTG Observe register (RO)
03099  *
03100  * Reset value: 0x50U
03101  *
03102  * Provides visibility on the state of the pull-ups and pull-downs at the
03103  * transceiver. Useful when interfacing to an external OTG control module via a serial
03104  * interface.
03105  */
03106 typedef union _hw_usb_observe
03107 {
03108     uint8_t U;
03109     struct _hw_usb_observe_bitfields
03110     {
03111         uint8_t RESERVED0 : 4;         /*!< [3:0]  */
03112         uint8_t DMPD : 1;              /*!< [4]  */
03113         uint8_t RESERVED1 : 1;         /*!< [5]  */
03114         uint8_t DPPD : 1;              /*!< [6]  */
03115         uint8_t DPPU : 1;              /*!< [7]  */
03116     } B;
03117 } hw_usb_observe_t;
03118 
03119 /*!
03120  * @name Constants and macros for entire USB_OBSERVE register
03121  */
03122 /*@{*/
03123 #define HW_USB_OBSERVE_ADDR(x)   ((x) + 0x104U)
03124 
03125 #define HW_USB_OBSERVE(x)        (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR(x))
03126 #define HW_USB_OBSERVE_RD(x)     (ADDRESS_READ(hw_usb_observe_t, HW_USB_OBSERVE_ADDR(x)))
03127 /*@}*/
03128 
03129 /*
03130  * Constants & macros for individual USB_OBSERVE bitfields
03131  */
03132 
03133 /*!
03134  * @name Register USB_OBSERVE, field DMPD[4] (RO)
03135  *
03136  * Provides observability of the D- Pulldown enable at the USB transceiver.
03137  *
03138  * Values:
03139  * - 0 - D- pulldown disabled.
03140  * - 1 - D- pulldown enabled.
03141  */
03142 /*@{*/
03143 #define BP_USB_OBSERVE_DMPD  (4U)          /*!< Bit position for USB_OBSERVE_DMPD. */
03144 #define BM_USB_OBSERVE_DMPD  (0x10U)       /*!< Bit mask for USB_OBSERVE_DMPD. */
03145 #define BS_USB_OBSERVE_DMPD  (1U)          /*!< Bit field size in bits for USB_OBSERVE_DMPD. */
03146 
03147 /*! @brief Read current value of the USB_OBSERVE_DMPD field. */
03148 #define BR_USB_OBSERVE_DMPD(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DMPD)))
03149 /*@}*/
03150 
03151 /*!
03152  * @name Register USB_OBSERVE, field DPPD[6] (RO)
03153  *
03154  * Provides observability of the D+ Pulldown enable at the USB transceiver.
03155  *
03156  * Values:
03157  * - 0 - D+ pulldown disabled.
03158  * - 1 - D+ pulldown enabled.
03159  */
03160 /*@{*/
03161 #define BP_USB_OBSERVE_DPPD  (6U)          /*!< Bit position for USB_OBSERVE_DPPD. */
03162 #define BM_USB_OBSERVE_DPPD  (0x40U)       /*!< Bit mask for USB_OBSERVE_DPPD. */
03163 #define BS_USB_OBSERVE_DPPD  (1U)          /*!< Bit field size in bits for USB_OBSERVE_DPPD. */
03164 
03165 /*! @brief Read current value of the USB_OBSERVE_DPPD field. */
03166 #define BR_USB_OBSERVE_DPPD(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPD)))
03167 /*@}*/
03168 
03169 /*!
03170  * @name Register USB_OBSERVE, field DPPU[7] (RO)
03171  *
03172  * Provides observability of the D+ Pullup enable at the USB transceiver.
03173  *
03174  * Values:
03175  * - 0 - D+ pullup disabled.
03176  * - 1 - D+ pullup enabled.
03177  */
03178 /*@{*/
03179 #define BP_USB_OBSERVE_DPPU  (7U)          /*!< Bit position for USB_OBSERVE_DPPU. */
03180 #define BM_USB_OBSERVE_DPPU  (0x80U)       /*!< Bit mask for USB_OBSERVE_DPPU. */
03181 #define BS_USB_OBSERVE_DPPU  (1U)          /*!< Bit field size in bits for USB_OBSERVE_DPPU. */
03182 
03183 /*! @brief Read current value of the USB_OBSERVE_DPPU field. */
03184 #define BR_USB_OBSERVE_DPPU(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_OBSERVE_ADDR(x), BP_USB_OBSERVE_DPPU)))
03185 /*@}*/
03186 
03187 /*******************************************************************************
03188  * HW_USB_CONTROL - USB OTG Control register
03189  ******************************************************************************/
03190 
03191 /*!
03192  * @brief HW_USB_CONTROL - USB OTG Control register (RW)
03193  *
03194  * Reset value: 0x00U
03195  */
03196 typedef union _hw_usb_control
03197 {
03198     uint8_t U;
03199     struct _hw_usb_control_bitfields
03200     {
03201         uint8_t RESERVED0 : 4;         /*!< [3:0]  */
03202         uint8_t DPPULLUPNONOTG : 1;    /*!< [4]  */
03203         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
03204     } B;
03205 } hw_usb_control_t;
03206 
03207 /*!
03208  * @name Constants and macros for entire USB_CONTROL register
03209  */
03210 /*@{*/
03211 #define HW_USB_CONTROL_ADDR(x)   ((x) + 0x108U)
03212 
03213 #define HW_USB_CONTROL(x)        (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR(x))
03214 #define HW_USB_CONTROL_RD(x)     (ADDRESS_READ(hw_usb_control_t, HW_USB_CONTROL_ADDR(x)))
03215 #define HW_USB_CONTROL_WR(x, v)  (ADDRESS_WRITE(hw_usb_control_t, HW_USB_CONTROL_ADDR(x), v))
03216 #define HW_USB_CONTROL_SET(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) |  (v)))
03217 #define HW_USB_CONTROL_CLR(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) & ~(v)))
03218 #define HW_USB_CONTROL_TOG(x, v) (HW_USB_CONTROL_WR(x, HW_USB_CONTROL_RD(x) ^  (v)))
03219 /*@}*/
03220 
03221 /*
03222  * Constants & macros for individual USB_CONTROL bitfields
03223  */
03224 
03225 /*!
03226  * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
03227  *
03228  * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
03229  * device mode.
03230  *
03231  * Values:
03232  * - 0 - DP Pullup in non-OTG device mode is not enabled.
03233  * - 1 - DP Pullup in non-OTG device mode is enabled.
03234  */
03235 /*@{*/
03236 #define BP_USB_CONTROL_DPPULLUPNONOTG (4U) /*!< Bit position for USB_CONTROL_DPPULLUPNONOTG. */
03237 #define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) /*!< Bit mask for USB_CONTROL_DPPULLUPNONOTG. */
03238 #define BS_USB_CONTROL_DPPULLUPNONOTG (1U) /*!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG. */
03239 
03240 /*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
03241 #define BR_USB_CONTROL_DPPULLUPNONOTG(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG)))
03242 
03243 /*! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG. */
03244 #define BF_USB_CONTROL_DPPULLUPNONOTG(v) ((uint8_t)((uint8_t)(v) << BP_USB_CONTROL_DPPULLUPNONOTG) & BM_USB_CONTROL_DPPULLUPNONOTG)
03245 
03246 /*! @brief Set the DPPULLUPNONOTG field to a new value. */
03247 #define BW_USB_CONTROL_DPPULLUPNONOTG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CONTROL_ADDR(x), BP_USB_CONTROL_DPPULLUPNONOTG), v))
03248 /*@}*/
03249 
03250 /*******************************************************************************
03251  * HW_USB_USBTRC0 - USB Transceiver Control register 0
03252  ******************************************************************************/
03253 
03254 /*!
03255  * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW)
03256  *
03257  * Reset value: 0x00U
03258  *
03259  * Includes signals for basic operation of the on-chip USB Full Speed
03260  * transceiver and configuration of the USB data connection that are not otherwise included
03261  * in the USB Full Speed controller registers.
03262  */
03263 typedef union _hw_usb_usbtrc0
03264 {
03265     uint8_t U;
03266     struct _hw_usb_usbtrc0_bitfields
03267     {
03268         uint8_t USB_RESUME_INT : 1;    /*!< [0] USB Asynchronous Interrupt */
03269         uint8_t SYNC_DET : 1;          /*!< [1] Synchronous USB Interrupt Detect */
03270         uint8_t USB_CLK_RECOVERY_INT : 1; /*!< [2] Combined USB Clock
03271                                         * Recovery interrupt status */
03272         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
03273         uint8_t USBRESMEN : 1;         /*!< [5] Asynchronous Resume Interrupt Enable
03274                                         * */
03275         uint8_t RESERVED1 : 1;         /*!< [6]  */
03276         uint8_t USBRESET : 1;          /*!< [7] USB Reset */
03277     } B;
03278 } hw_usb_usbtrc0_t;
03279 
03280 /*!
03281  * @name Constants and macros for entire USB_USBTRC0 register
03282  */
03283 /*@{*/
03284 #define HW_USB_USBTRC0_ADDR(x)   ((x) + 0x10CU)
03285 
03286 #define HW_USB_USBTRC0(x)        (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR(x))
03287 #define HW_USB_USBTRC0_RD(x)     (ADDRESS_READ(hw_usb_usbtrc0_t, HW_USB_USBTRC0_ADDR(x)))
03288 #define HW_USB_USBTRC0_WR(x, v)  (ADDRESS_WRITE(hw_usb_usbtrc0_t, HW_USB_USBTRC0_ADDR(x), v))
03289 #define HW_USB_USBTRC0_SET(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) |  (v)))
03290 #define HW_USB_USBTRC0_CLR(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) & ~(v)))
03291 #define HW_USB_USBTRC0_TOG(x, v) (HW_USB_USBTRC0_WR(x, HW_USB_USBTRC0_RD(x) ^  (v)))
03292 /*@}*/
03293 
03294 /*
03295  * Constants & macros for individual USB_USBTRC0 bitfields
03296  */
03297 
03298 /*!
03299  * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
03300  *
03301  * Values:
03302  * - 0 - No interrupt was generated.
03303  * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
03304  */
03305 /*@{*/
03306 #define BP_USB_USBTRC0_USB_RESUME_INT (0U) /*!< Bit position for USB_USBTRC0_USB_RESUME_INT. */
03307 #define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) /*!< Bit mask for USB_USBTRC0_USB_RESUME_INT. */
03308 #define BS_USB_USBTRC0_USB_RESUME_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT. */
03309 
03310 /*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
03311 #define BR_USB_USBTRC0_USB_RESUME_INT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_RESUME_INT)))
03312 /*@}*/
03313 
03314 /*!
03315  * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
03316  *
03317  * Values:
03318  * - 0 - Synchronous interrupt has not been detected.
03319  * - 1 - Synchronous interrupt has been detected.
03320  */
03321 /*@{*/
03322 #define BP_USB_USBTRC0_SYNC_DET (1U)       /*!< Bit position for USB_USBTRC0_SYNC_DET. */
03323 #define BM_USB_USBTRC0_SYNC_DET (0x02U)    /*!< Bit mask for USB_USBTRC0_SYNC_DET. */
03324 #define BS_USB_USBTRC0_SYNC_DET (1U)       /*!< Bit field size in bits for USB_USBTRC0_SYNC_DET. */
03325 
03326 /*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
03327 #define BR_USB_USBTRC0_SYNC_DET(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_SYNC_DET)))
03328 /*@}*/
03329 
03330 /*!
03331  * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
03332  *
03333  * This read-only field will be set to value high at 1'b1 when any of USB clock
03334  * recovery interrupt conditions are detected and those interrupts are unmasked.
03335  * For customer use the only unmasked USB clock recovery interrupt condition
03336  * results from an overflow of the frequency trim setting values indicating that the
03337  * frequency trim calculated is out of the adjustment range of the IRC48M output
03338  * clock. To clear this bit after it has been set, Write 0xFF to register
03339  * USB_CLK_RECOVER_INT_STATUS.
03340  */
03341 /*@{*/
03342 #define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) /*!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
03343 #define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) /*!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
03344 #define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) /*!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT. */
03345 
03346 /*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
03347 #define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USB_CLK_RECOVERY_INT)))
03348 /*@}*/
03349 
03350 /*!
03351  * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
03352  *
03353  * This bit, when set, allows the USB module to send an asynchronous wakeup
03354  * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
03355  * re-enables clocks to the USB module. It is used for low-power suspend mode when
03356  * USB module clocks are stopped or the USB transceiver is in Suspend mode.
03357  * Async wakeup only works in device mode.
03358  *
03359  * Values:
03360  * - 0 - USB asynchronous wakeup from suspend mode disabled.
03361  * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
03362  *     resume interrupt differs from the synchronous resume interrupt in that it
03363  *     asynchronously detects K-state using the unfiltered state of the D+ and D-
03364  *     pins. This interrupt should only be enabled when the Transceiver is
03365  *     suspended.
03366  */
03367 /*@{*/
03368 #define BP_USB_USBTRC0_USBRESMEN (5U)      /*!< Bit position for USB_USBTRC0_USBRESMEN. */
03369 #define BM_USB_USBTRC0_USBRESMEN (0x20U)   /*!< Bit mask for USB_USBTRC0_USBRESMEN. */
03370 #define BS_USB_USBTRC0_USBRESMEN (1U)      /*!< Bit field size in bits for USB_USBTRC0_USBRESMEN. */
03371 
03372 /*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
03373 #define BR_USB_USBTRC0_USBRESMEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN)))
03374 
03375 /*! @brief Format value for bitfield USB_USBTRC0_USBRESMEN. */
03376 #define BF_USB_USBTRC0_USBRESMEN(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESMEN) & BM_USB_USBTRC0_USBRESMEN)
03377 
03378 /*! @brief Set the USBRESMEN field to a new value. */
03379 #define BW_USB_USBTRC0_USBRESMEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_USBTRC0_ADDR(x), BP_USB_USBTRC0_USBRESMEN), v))
03380 /*@}*/
03381 
03382 /*!
03383  * @name Register USB_USBTRC0, field USBRESET[7] (WO)
03384  *
03385  * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
03386  * this bit is automatically cleared. This bit is always read as zero. Wait two
03387  * USB clock cycles after setting this bit.
03388  *
03389  * Values:
03390  * - 0 - Normal USB module operation.
03391  * - 1 - Returns the USB module to its reset state.
03392  */
03393 /*@{*/
03394 #define BP_USB_USBTRC0_USBRESET (7U)       /*!< Bit position for USB_USBTRC0_USBRESET. */
03395 #define BM_USB_USBTRC0_USBRESET (0x80U)    /*!< Bit mask for USB_USBTRC0_USBRESET. */
03396 #define BS_USB_USBTRC0_USBRESET (1U)       /*!< Bit field size in bits for USB_USBTRC0_USBRESET. */
03397 
03398 /*! @brief Format value for bitfield USB_USBTRC0_USBRESET. */
03399 #define BF_USB_USBTRC0_USBRESET(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBTRC0_USBRESET) & BM_USB_USBTRC0_USBRESET)
03400 /*@}*/
03401 
03402 /*******************************************************************************
03403  * HW_USB_USBFRMADJUST - Frame Adjust Register
03404  ******************************************************************************/
03405 
03406 /*!
03407  * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW)
03408  *
03409  * Reset value: 0x00U
03410  */
03411 typedef union _hw_usb_usbfrmadjust
03412 {
03413     uint8_t U;
03414     struct _hw_usb_usbfrmadjust_bitfields
03415     {
03416         uint8_t ADJ : 8;               /*!< [7:0] Frame Adjustment */
03417     } B;
03418 } hw_usb_usbfrmadjust_t;
03419 
03420 /*!
03421  * @name Constants and macros for entire USB_USBFRMADJUST register
03422  */
03423 /*@{*/
03424 #define HW_USB_USBFRMADJUST_ADDR(x) ((x) + 0x114U)
03425 
03426 #define HW_USB_USBFRMADJUST(x)   (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR(x))
03427 #define HW_USB_USBFRMADJUST_RD(x) (ADDRESS_READ(hw_usb_usbfrmadjust_t, HW_USB_USBFRMADJUST_ADDR(x)))
03428 #define HW_USB_USBFRMADJUST_WR(x, v) (ADDRESS_WRITE(hw_usb_usbfrmadjust_t, HW_USB_USBFRMADJUST_ADDR(x), v))
03429 #define HW_USB_USBFRMADJUST_SET(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) |  (v)))
03430 #define HW_USB_USBFRMADJUST_CLR(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) & ~(v)))
03431 #define HW_USB_USBFRMADJUST_TOG(x, v) (HW_USB_USBFRMADJUST_WR(x, HW_USB_USBFRMADJUST_RD(x) ^  (v)))
03432 /*@}*/
03433 
03434 /*
03435  * Constants & macros for individual USB_USBFRMADJUST bitfields
03436  */
03437 
03438 /*!
03439  * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW)
03440  *
03441  * In Host mode, the frame adjustment is a twos complement number that adjusts
03442  * the period of each USB frame in 12-MHz clock periods. A SOF is normally
03443  * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this
03444  * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock.
03445  * Changes to the ADJ bit take effect at the next start of the next frame.
03446  */
03447 /*@{*/
03448 #define BP_USB_USBFRMADJUST_ADJ (0U)       /*!< Bit position for USB_USBFRMADJUST_ADJ. */
03449 #define BM_USB_USBFRMADJUST_ADJ (0xFFU)    /*!< Bit mask for USB_USBFRMADJUST_ADJ. */
03450 #define BS_USB_USBFRMADJUST_ADJ (8U)       /*!< Bit field size in bits for USB_USBFRMADJUST_ADJ. */
03451 
03452 /*! @brief Read current value of the USB_USBFRMADJUST_ADJ field. */
03453 #define BR_USB_USBFRMADJUST_ADJ(x) (HW_USB_USBFRMADJUST(x).U)
03454 
03455 /*! @brief Format value for bitfield USB_USBFRMADJUST_ADJ. */
03456 #define BF_USB_USBFRMADJUST_ADJ(v) ((uint8_t)((uint8_t)(v) << BP_USB_USBFRMADJUST_ADJ) & BM_USB_USBFRMADJUST_ADJ)
03457 
03458 /*! @brief Set the ADJ field to a new value. */
03459 #define BW_USB_USBFRMADJUST_ADJ(x, v) (HW_USB_USBFRMADJUST_WR(x, v))
03460 /*@}*/
03461 
03462 /*******************************************************************************
03463  * HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
03464  ******************************************************************************/
03465 
03466 /*!
03467  * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
03468  *
03469  * Reset value: 0x00U
03470  *
03471  * Signals in this register control the crystal-less USB clock mode in which the
03472  * internal IRC48M oscillator is tuned to match the clock extracted from the
03473  * incoming USB data stream. The IRC48M internal oscillator module must be enabled
03474  * in register USB_CLK_RECOVER_IRC_EN for this mode.
03475  */
03476 typedef union _hw_usb_clk_recover_ctrl
03477 {
03478     uint8_t U;
03479     struct _hw_usb_clk_recover_ctrl_bitfields
03480     {
03481         uint8_t RESERVED0 : 5;         /*!< [4:0]  */
03482         uint8_t RESTART_IFRTRIM_EN : 1; /*!< [5] Restart from IFR trim value
03483                                         * */
03484         uint8_t RESET_RESUME_ROUGH_EN : 1; /*!< [6] Reset/resume to rough
03485                                         * phase enable */
03486         uint8_t CLOCK_RECOVER_EN : 1;  /*!< [7] Crystal-less USB enable */
03487     } B;
03488 } hw_usb_clk_recover_ctrl_t;
03489 
03490 /*!
03491  * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
03492  */
03493 /*@{*/
03494 #define HW_USB_CLK_RECOVER_CTRL_ADDR(x) ((x) + 0x140U)
03495 
03496 #define HW_USB_CLK_RECOVER_CTRL(x) (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR(x))
03497 #define HW_USB_CLK_RECOVER_CTRL_RD(x) (ADDRESS_READ(hw_usb_clk_recover_ctrl_t, HW_USB_CLK_RECOVER_CTRL_ADDR(x)))
03498 #define HW_USB_CLK_RECOVER_CTRL_WR(x, v) (ADDRESS_WRITE(hw_usb_clk_recover_ctrl_t, HW_USB_CLK_RECOVER_CTRL_ADDR(x), v))
03499 #define HW_USB_CLK_RECOVER_CTRL_SET(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) |  (v)))
03500 #define HW_USB_CLK_RECOVER_CTRL_CLR(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) & ~(v)))
03501 #define HW_USB_CLK_RECOVER_CTRL_TOG(x, v) (HW_USB_CLK_RECOVER_CTRL_WR(x, HW_USB_CLK_RECOVER_CTRL_RD(x) ^  (v)))
03502 /*@}*/
03503 
03504 /*
03505  * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
03506  */
03507 
03508 /*!
03509  * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
03510  *
03511  * IRC48 has a default trim fine value whose default value is factory trimmed
03512  * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
03513  * and keeps updating the trim fine value accordingly
03514  *
03515  * Values:
03516  * - 0 - Trim fine adjustment always works based on the previous updated trim
03517  *     fine value (default)
03518  * - 1 - Trim fine restarts from the IFR trim value whenever
03519  *     bus_reset/bus_resume is detected or module enable is desasserted
03520  */
03521 /*@{*/
03522 #define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
03523 #define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
03524 #define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
03525 
03526 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
03527 #define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)))
03528 
03529 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN. */
03530 #define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)
03531 
03532 /*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
03533 #define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN), v))
03534 /*@}*/
03535 
03536 /*!
03537  * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
03538  *
03539  * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
03540  * It has two phases after user enables clock_recover_en bit, rough phase and
03541  * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
03542  * value is different during these two phases. The step in rough phase is larger
03543  * than that in tracking phase. Switch back to rough stage whenever USB bus reset
03544  * or bus resume occurs.
03545  *
03546  * Values:
03547  * - 0 - Always works in tracking phase after the 1st time rough to track
03548  *     transition (default)
03549  * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
03550  */
03551 /*@{*/
03552 #define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) /*!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
03553 #define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
03554 #define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
03555 
03556 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
03557 #define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)))
03558 
03559 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN. */
03560 #define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)
03561 
03562 /*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
03563 #define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN), v))
03564 /*@}*/
03565 
03566 /*!
03567  * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
03568  *
03569  * This bit must be enabled if user wants to use the crystal-less USB mode for
03570  * the Full Speed USB controller and transceiver. This bit should not be set for
03571  * USB host mode or OTG.
03572  *
03573  * Values:
03574  * - 0 - Disable clock recovery block (default)
03575  * - 1 - Enable clock recovery block
03576  */
03577 /*@{*/
03578 #define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) /*!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
03579 #define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) /*!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
03580 #define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
03581 
03582 /*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
03583 #define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)))
03584 
03585 /*! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN. */
03586 #define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)
03587 
03588 /*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
03589 #define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_CTRL_ADDR(x), BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN), v))
03590 /*@}*/
03591 
03592 /*******************************************************************************
03593  * HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
03594  ******************************************************************************/
03595 
03596 /*!
03597  * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
03598  *
03599  * Reset value: 0x01U
03600  *
03601  * Controls basic operation of the on-chip IRC48M module used to produce nominal
03602  * 48MHz clocks for USB crystal-less operation and other functions. See
03603  * additional information about the IRC48M operation in the Clock Distribution chapter.
03604  */
03605 typedef union _hw_usb_clk_recover_irc_en
03606 {
03607     uint8_t U;
03608     struct _hw_usb_clk_recover_irc_en_bitfields
03609     {
03610         uint8_t REG_EN : 1;            /*!< [0] IRC48M regulator enable */
03611         uint8_t IRC_EN : 1;            /*!< [1] IRC48M enable */
03612         uint8_t RESERVED0 : 6;         /*!< [7:2]  */
03613     } B;
03614 } hw_usb_clk_recover_irc_en_t;
03615 
03616 /*!
03617  * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
03618  */
03619 /*@{*/
03620 #define HW_USB_CLK_RECOVER_IRC_EN_ADDR(x) ((x) + 0x144U)
03621 
03622 #define HW_USB_CLK_RECOVER_IRC_EN(x) (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR(x))
03623 #define HW_USB_CLK_RECOVER_IRC_EN_RD(x) (ADDRESS_READ(hw_usb_clk_recover_irc_en_t, HW_USB_CLK_RECOVER_IRC_EN_ADDR(x)))
03624 #define HW_USB_CLK_RECOVER_IRC_EN_WR(x, v) (ADDRESS_WRITE(hw_usb_clk_recover_irc_en_t, HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), v))
03625 #define HW_USB_CLK_RECOVER_IRC_EN_SET(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) |  (v)))
03626 #define HW_USB_CLK_RECOVER_IRC_EN_CLR(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) & ~(v)))
03627 #define HW_USB_CLK_RECOVER_IRC_EN_TOG(x, v) (HW_USB_CLK_RECOVER_IRC_EN_WR(x, HW_USB_CLK_RECOVER_IRC_EN_RD(x) ^  (v)))
03628 /*@}*/
03629 
03630 /*
03631  * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
03632  */
03633 
03634 /*!
03635  * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
03636  *
03637  * This bit is used to enable the local analog regulator for IRC48Mhz module.
03638  * This bit must be set if user wants to use the crystal-less USB clock
03639  * configuration.
03640  *
03641  * Values:
03642  * - 0 - IRC48M local regulator is disabled
03643  * - 1 - IRC48M local regulator is enabled (default)
03644  */
03645 /*@{*/
03646 #define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN. */
03647 #define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN. */
03648 #define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN. */
03649 
03650 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
03651 #define BR_USB_CLK_RECOVER_IRC_EN_REG_EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN)))
03652 
03653 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN. */
03654 #define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN)
03655 
03656 /*! @brief Set the REG_EN field to a new value. */
03657 #define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_REG_EN), v))
03658 /*@}*/
03659 
03660 /*!
03661  * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
03662  *
03663  * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
03664  * crystal-less USB. It can only be used for FS USB device mode operation. This
03665  * bit must be set before using the crystal-less USB clock configuration.
03666  *
03667  * Values:
03668  * - 0 - Disable the IRC48M module (default)
03669  * - 1 - Enable the IRC48M module
03670  */
03671 /*@{*/
03672 #define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
03673 #define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) /*!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
03674 #define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN. */
03675 
03676 /*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
03677 #define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN)))
03678 
03679 /*! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN. */
03680 #define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN)
03681 
03682 /*! @brief Set the IRC_EN field to a new value. */
03683 #define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR(x), BP_USB_CLK_RECOVER_IRC_EN_IRC_EN), v))
03684 /*@}*/
03685 
03686 /*******************************************************************************
03687  * HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
03688  ******************************************************************************/
03689 
03690 /*!
03691  * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
03692  *
03693  * Reset value: 0x00U
03694  *
03695  * A Write operation with value high at 1'b1 on any combination of individual
03696  * bits will clear those bits.
03697  */
03698 typedef union _hw_usb_clk_recover_int_status
03699 {
03700     uint8_t U;
03701     struct _hw_usb_clk_recover_int_status_bitfields
03702     {
03703         uint8_t RESERVED0 : 4;         /*!< [3:0]  */
03704         uint8_t OVF_ERROR : 1;         /*!< [4]  */
03705         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
03706     } B;
03707 } hw_usb_clk_recover_int_status_t;
03708 
03709 /*!
03710  * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
03711  */
03712 /*@{*/
03713 #define HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x) ((x) + 0x15CU)
03714 
03715 #define HW_USB_CLK_RECOVER_INT_STATUS(x) (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x))
03716 #define HW_USB_CLK_RECOVER_INT_STATUS_RD(x) (ADDRESS_READ(hw_usb_clk_recover_int_status_t, HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x)))
03717 #define HW_USB_CLK_RECOVER_INT_STATUS_WR(x, v) (ADDRESS_WRITE(hw_usb_clk_recover_int_status_t, HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), v))
03718 #define HW_USB_CLK_RECOVER_INT_STATUS_SET(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) |  (v)))
03719 #define HW_USB_CLK_RECOVER_INT_STATUS_CLR(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) & ~(v)))
03720 #define HW_USB_CLK_RECOVER_INT_STATUS_TOG(x, v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(x, HW_USB_CLK_RECOVER_INT_STATUS_RD(x) ^  (v)))
03721 /*@}*/
03722 
03723 /*
03724  * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
03725  */
03726 
03727 /*!
03728  * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
03729  *
03730  * Indicates that the USB clock recovery algorithm has detected that the
03731  * frequency trim adjustment needed for the IRC48M output clock is outside the available
03732  * TRIM_FINE adjustment range for the IRC48M module.
03733  *
03734  * Values:
03735  * - 0 - No interrupt is reported
03736  * - 1 - Unmasked interrupt has been generated
03737  */
03738 /*@{*/
03739 #define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) /*!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
03740 #define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) /*!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
03741 #define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) /*!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
03742 
03743 /*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
03744 #define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)))
03745 
03746 /*! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR. */
03747 #define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) ((uint8_t)((uint8_t)(v) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)
03748 
03749 /*! @brief Set the OVF_ERROR field to a new value. */
03750 #define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR(x), BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR), v))
03751 /*@}*/
03752 
03753 /*******************************************************************************
03754  * hw_usb_t - module struct
03755  ******************************************************************************/
03756 /*!
03757  * @brief All USB module registers.
03758  */
03759 #pragma pack(1)
03760 typedef struct _hw_usb
03761 {
03762     __I hw_usb_perid_t PERID ;              /*!< [0x0] Peripheral ID register */
03763     uint8_t _reserved0[3];
03764     __I hw_usb_idcomp_t IDCOMP ;            /*!< [0x4] Peripheral ID Complement register */
03765     uint8_t _reserved1[3];
03766     __I hw_usb_rev_t REV ;                  /*!< [0x8] Peripheral Revision register */
03767     uint8_t _reserved2[3];
03768     __I hw_usb_addinfo_t ADDINFO ;          /*!< [0xC] Peripheral Additional Info register */
03769     uint8_t _reserved3[3];
03770     __IO hw_usb_otgistat_t OTGISTAT ;       /*!< [0x10] OTG Interrupt Status register */
03771     uint8_t _reserved4[3];
03772     __IO hw_usb_otgicr_t OTGICR ;           /*!< [0x14] OTG Interrupt Control register */
03773     uint8_t _reserved5[3];
03774     __IO hw_usb_otgstat_t OTGSTAT ;         /*!< [0x18] OTG Status register */
03775     uint8_t _reserved6[3];
03776     __IO hw_usb_otgctl_t OTGCTL ;           /*!< [0x1C] OTG Control register */
03777     uint8_t _reserved7[99];
03778     __IO hw_usb_istat_t ISTAT ;             /*!< [0x80] Interrupt Status register */
03779     uint8_t _reserved8[3];
03780     __IO hw_usb_inten_t INTEN ;             /*!< [0x84] Interrupt Enable register */
03781     uint8_t _reserved9[3];
03782     __IO hw_usb_errstat_t ERRSTAT ;         /*!< [0x88] Error Interrupt Status register */
03783     uint8_t _reserved10[3];
03784     __IO hw_usb_erren_t ERREN ;             /*!< [0x8C] Error Interrupt Enable register */
03785     uint8_t _reserved11[3];
03786     __I hw_usb_stat_t STAT ;                /*!< [0x90] Status register */
03787     uint8_t _reserved12[3];
03788     __IO hw_usb_ctl_t CTL ;                 /*!< [0x94] Control register */
03789     uint8_t _reserved13[3];
03790     __IO hw_usb_addr_t ADDR ;               /*!< [0x98] Address register */
03791     uint8_t _reserved14[3];
03792     __IO hw_usb_bdtpage1_t BDTPAGE1 ;       /*!< [0x9C] BDT Page register 1 */
03793     uint8_t _reserved15[3];
03794     __IO hw_usb_frmnuml_t FRMNUML ;         /*!< [0xA0] Frame Number register Low */
03795     uint8_t _reserved16[3];
03796     __IO hw_usb_frmnumh_t FRMNUMH ;         /*!< [0xA4] Frame Number register High */
03797     uint8_t _reserved17[3];
03798     __IO hw_usb_token_t TOKEN ;             /*!< [0xA8] Token register */
03799     uint8_t _reserved18[3];
03800     __IO hw_usb_softhld_t SOFTHLD ;         /*!< [0xAC] SOF Threshold register */
03801     uint8_t _reserved19[3];
03802     __IO hw_usb_bdtpage2_t BDTPAGE2 ;       /*!< [0xB0] BDT Page Register 2 */
03803     uint8_t _reserved20[3];
03804     __IO hw_usb_bdtpage3_t BDTPAGE3 ;       /*!< [0xB4] BDT Page Register 3 */
03805     uint8_t _reserved21[11];
03806     struct {
03807         __IO hw_usb_endptn_t ENDPTn ;       /*!< [0xC0] Endpoint Control register */
03808         uint8_t _reserved0[3];
03809     } ENDPOINT[16];
03810     __IO hw_usb_usbctrl_t USBCTRL ;         /*!< [0x100] USB Control register */
03811     uint8_t _reserved22[3];
03812     __I hw_usb_observe_t OBSERVE ;          /*!< [0x104] USB OTG Observe register */
03813     uint8_t _reserved23[3];
03814     __IO hw_usb_control_t CONTROL ;         /*!< [0x108] USB OTG Control register */
03815     uint8_t _reserved24[3];
03816     __IO hw_usb_usbtrc0_t USBTRC0 ;         /*!< [0x10C] USB Transceiver Control register 0 */
03817     uint8_t _reserved25[7];
03818     __IO hw_usb_usbfrmadjust_t USBFRMADJUST ; /*!< [0x114] Frame Adjust Register */
03819     uint8_t _reserved26[43];
03820     __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL ; /*!< [0x140] USB Clock recovery control */
03821     uint8_t _reserved27[3];
03822     __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN ; /*!< [0x144] IRC48M oscillator enable register */
03823     uint8_t _reserved28[23];
03824     __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS ; /*!< [0x15C] Clock recovery separated interrupt status */
03825 } hw_usb_t;
03826 #pragma pack()
03827 
03828 /*! @brief Macro to access all USB registers. */
03829 /*! @param x USB module instance base address. */
03830 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
03831  *     use the '&' operator, like <code>&HW_USB(USB0_BASE)</code>. */
03832 #define HW_USB(x)      (*(hw_usb_t *)(x))
03833 
03834 #endif /* __HW_USB_REGISTERS_H__ */
03835 /* EOF */