_hw_llwu_f3 Union Reference

HW_LLWU_F3 - LLWU Flag 3 register (RO) More...

#include <MK64F12_llwu.h>

Detailed Description

HW_LLWU_F3 - LLWU Flag 3 register (RO)

Reset value: 0x00U

LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. For internal peripherals that are capable of running in a low-leakage power mode, such as a real time clock module or CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. details for more information.

Definition at line 1496 of file MK64F12_llwu.h.