MK64F12_llwu.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_LLWU_REGISTERS_H__
00088 #define __HW_LLWU_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 LLWU
00095  *
00096  * Low leakage wakeup unit
00097  *
00098  * Registers defined in this header file:
00099  * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
00100  * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
00101  * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
00102  * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
00103  * - HW_LLWU_ME - LLWU Module Enable register
00104  * - HW_LLWU_F1 - LLWU Flag 1 register
00105  * - HW_LLWU_F2 - LLWU Flag 2 register
00106  * - HW_LLWU_F3 - LLWU Flag 3 register
00107  * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
00108  * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
00109  * - HW_LLWU_RST - LLWU Reset Enable register
00110  *
00111  * - hw_llwu_t - Struct containing all module registers.
00112  */
00113 
00114 #define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
00115 
00116 /*******************************************************************************
00117  * HW_LLWU_PE1 - LLWU Pin Enable 1 register
00118  ******************************************************************************/
00119 
00120 /*!
00121  * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
00122  *
00123  * Reset value: 0x00U
00124  *
00125  * LLWU_PE1 contains the field to enable and select the edge detect type for the
00126  * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
00127  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
00128  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
00129  * IntroductionInformation found here describes the registers of the Reset Control Module
00130  * (RCM). The RCM implements many of the reset functions for the chip. See the
00131  * chip's reset chapter for more information. details for more information.
00132  */
00133 typedef union _hw_llwu_pe1
00134 {
00135     uint8_t U;
00136     struct _hw_llwu_pe1_bitfields
00137     {
00138         uint8_t WUPE0 : 2;             /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */
00139         uint8_t WUPE1 : 2;             /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */
00140         uint8_t WUPE2 : 2;             /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */
00141         uint8_t WUPE3 : 2;             /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */
00142     } B;
00143 } hw_llwu_pe1_t;
00144 
00145 /*!
00146  * @name Constants and macros for entire LLWU_PE1 register
00147  */
00148 /*@{*/
00149 #define HW_LLWU_PE1_ADDR(x)      ((x) + 0x0U)
00150 
00151 #define HW_LLWU_PE1(x)           (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x))
00152 #define HW_LLWU_PE1_RD(x)        (ADDRESS_READ(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x)))
00153 #define HW_LLWU_PE1_WR(x, v)     (ADDRESS_WRITE(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x), v))
00154 #define HW_LLWU_PE1_SET(x, v)    (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) |  (v)))
00155 #define HW_LLWU_PE1_CLR(x, v)    (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
00156 #define HW_LLWU_PE1_TOG(x, v)    (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^  (v)))
00157 /*@}*/
00158 
00159 /*
00160  * Constants & macros for individual LLWU_PE1 bitfields
00161  */
00162 
00163 /*!
00164  * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
00165  *
00166  * Enables and configures the edge detection for the wakeup pin.
00167  *
00168  * Values:
00169  * - 00 - External input pin disabled as wakeup input
00170  * - 01 - External input pin enabled with rising edge detection
00171  * - 10 - External input pin enabled with falling edge detection
00172  * - 11 - External input pin enabled with any change detection
00173  */
00174 /*@{*/
00175 #define BP_LLWU_PE1_WUPE0    (0U)          /*!< Bit position for LLWU_PE1_WUPE0. */
00176 #define BM_LLWU_PE1_WUPE0    (0x03U)       /*!< Bit mask for LLWU_PE1_WUPE0. */
00177 #define BS_LLWU_PE1_WUPE0    (2U)          /*!< Bit field size in bits for LLWU_PE1_WUPE0. */
00178 
00179 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
00180 #define BR_LLWU_PE1_WUPE0(x) (UNION_READ(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x), U, B.WUPE0))
00181 
00182 /*! @brief Format value for bitfield LLWU_PE1_WUPE0. */
00183 #define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
00184 
00185 /*! @brief Set the WUPE0 field to a new value. */
00186 #define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
00187 /*@}*/
00188 
00189 /*!
00190  * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
00191  *
00192  * Enables and configures the edge detection for the wakeup pin.
00193  *
00194  * Values:
00195  * - 00 - External input pin disabled as wakeup input
00196  * - 01 - External input pin enabled with rising edge detection
00197  * - 10 - External input pin enabled with falling edge detection
00198  * - 11 - External input pin enabled with any change detection
00199  */
00200 /*@{*/
00201 #define BP_LLWU_PE1_WUPE1    (2U)          /*!< Bit position for LLWU_PE1_WUPE1. */
00202 #define BM_LLWU_PE1_WUPE1    (0x0CU)       /*!< Bit mask for LLWU_PE1_WUPE1. */
00203 #define BS_LLWU_PE1_WUPE1    (2U)          /*!< Bit field size in bits for LLWU_PE1_WUPE1. */
00204 
00205 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
00206 #define BR_LLWU_PE1_WUPE1(x) (UNION_READ(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x), U, B.WUPE1))
00207 
00208 /*! @brief Format value for bitfield LLWU_PE1_WUPE1. */
00209 #define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
00210 
00211 /*! @brief Set the WUPE1 field to a new value. */
00212 #define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
00213 /*@}*/
00214 
00215 /*!
00216  * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
00217  *
00218  * Enables and configures the edge detection for the wakeup pin.
00219  *
00220  * Values:
00221  * - 00 - External input pin disabled as wakeup input
00222  * - 01 - External input pin enabled with rising edge detection
00223  * - 10 - External input pin enabled with falling edge detection
00224  * - 11 - External input pin enabled with any change detection
00225  */
00226 /*@{*/
00227 #define BP_LLWU_PE1_WUPE2    (4U)          /*!< Bit position for LLWU_PE1_WUPE2. */
00228 #define BM_LLWU_PE1_WUPE2    (0x30U)       /*!< Bit mask for LLWU_PE1_WUPE2. */
00229 #define BS_LLWU_PE1_WUPE2    (2U)          /*!< Bit field size in bits for LLWU_PE1_WUPE2. */
00230 
00231 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
00232 #define BR_LLWU_PE1_WUPE2(x) (UNION_READ(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x), U, B.WUPE2))
00233 
00234 /*! @brief Format value for bitfield LLWU_PE1_WUPE2. */
00235 #define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
00236 
00237 /*! @brief Set the WUPE2 field to a new value. */
00238 #define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
00239 /*@}*/
00240 
00241 /*!
00242  * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
00243  *
00244  * Enables and configures the edge detection for the wakeup pin.
00245  *
00246  * Values:
00247  * - 00 - External input pin disabled as wakeup input
00248  * - 01 - External input pin enabled with rising edge detection
00249  * - 10 - External input pin enabled with falling edge detection
00250  * - 11 - External input pin enabled with any change detection
00251  */
00252 /*@{*/
00253 #define BP_LLWU_PE1_WUPE3    (6U)          /*!< Bit position for LLWU_PE1_WUPE3. */
00254 #define BM_LLWU_PE1_WUPE3    (0xC0U)       /*!< Bit mask for LLWU_PE1_WUPE3. */
00255 #define BS_LLWU_PE1_WUPE3    (2U)          /*!< Bit field size in bits for LLWU_PE1_WUPE3. */
00256 
00257 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
00258 #define BR_LLWU_PE1_WUPE3(x) (UNION_READ(hw_llwu_pe1_t, HW_LLWU_PE1_ADDR(x), U, B.WUPE3))
00259 
00260 /*! @brief Format value for bitfield LLWU_PE1_WUPE3. */
00261 #define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
00262 
00263 /*! @brief Set the WUPE3 field to a new value. */
00264 #define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
00265 /*@}*/
00266 
00267 /*******************************************************************************
00268  * HW_LLWU_PE2 - LLWU Pin Enable 2 register
00269  ******************************************************************************/
00270 
00271 /*!
00272  * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
00273  *
00274  * Reset value: 0x00U
00275  *
00276  * LLWU_PE2 contains the field to enable and select the edge detect type for the
00277  * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
00278  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
00279  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
00280  * IntroductionInformation found here describes the registers of the Reset Control Module
00281  * (RCM). The RCM implements many of the reset functions for the chip. See the
00282  * chip's reset chapter for more information. details for more information.
00283  */
00284 typedef union _hw_llwu_pe2
00285 {
00286     uint8_t U;
00287     struct _hw_llwu_pe2_bitfields
00288     {
00289         uint8_t WUPE4 : 2;             /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */
00290         uint8_t WUPE5 : 2;             /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */
00291         uint8_t WUPE6 : 2;             /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */
00292         uint8_t WUPE7 : 2;             /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */
00293     } B;
00294 } hw_llwu_pe2_t;
00295 
00296 /*!
00297  * @name Constants and macros for entire LLWU_PE2 register
00298  */
00299 /*@{*/
00300 #define HW_LLWU_PE2_ADDR(x)      ((x) + 0x1U)
00301 
00302 #define HW_LLWU_PE2(x)           (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x))
00303 #define HW_LLWU_PE2_RD(x)        (ADDRESS_READ(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x)))
00304 #define HW_LLWU_PE2_WR(x, v)     (ADDRESS_WRITE(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x), v))
00305 #define HW_LLWU_PE2_SET(x, v)    (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) |  (v)))
00306 #define HW_LLWU_PE2_CLR(x, v)    (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
00307 #define HW_LLWU_PE2_TOG(x, v)    (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^  (v)))
00308 /*@}*/
00309 
00310 /*
00311  * Constants & macros for individual LLWU_PE2 bitfields
00312  */
00313 
00314 /*!
00315  * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
00316  *
00317  * Enables and configures the edge detection for the wakeup pin.
00318  *
00319  * Values:
00320  * - 00 - External input pin disabled as wakeup input
00321  * - 01 - External input pin enabled with rising edge detection
00322  * - 10 - External input pin enabled with falling edge detection
00323  * - 11 - External input pin enabled with any change detection
00324  */
00325 /*@{*/
00326 #define BP_LLWU_PE2_WUPE4    (0U)          /*!< Bit position for LLWU_PE2_WUPE4. */
00327 #define BM_LLWU_PE2_WUPE4    (0x03U)       /*!< Bit mask for LLWU_PE2_WUPE4. */
00328 #define BS_LLWU_PE2_WUPE4    (2U)          /*!< Bit field size in bits for LLWU_PE2_WUPE4. */
00329 
00330 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
00331 #define BR_LLWU_PE2_WUPE4(x) (UNION_READ(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x), U, B.WUPE4))
00332 
00333 /*! @brief Format value for bitfield LLWU_PE2_WUPE4. */
00334 #define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
00335 
00336 /*! @brief Set the WUPE4 field to a new value. */
00337 #define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
00338 /*@}*/
00339 
00340 /*!
00341  * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
00342  *
00343  * Enables and configures the edge detection for the wakeup pin.
00344  *
00345  * Values:
00346  * - 00 - External input pin disabled as wakeup input
00347  * - 01 - External input pin enabled with rising edge detection
00348  * - 10 - External input pin enabled with falling edge detection
00349  * - 11 - External input pin enabled with any change detection
00350  */
00351 /*@{*/
00352 #define BP_LLWU_PE2_WUPE5    (2U)          /*!< Bit position for LLWU_PE2_WUPE5. */
00353 #define BM_LLWU_PE2_WUPE5    (0x0CU)       /*!< Bit mask for LLWU_PE2_WUPE5. */
00354 #define BS_LLWU_PE2_WUPE5    (2U)          /*!< Bit field size in bits for LLWU_PE2_WUPE5. */
00355 
00356 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
00357 #define BR_LLWU_PE2_WUPE5(x) (UNION_READ(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x), U, B.WUPE5))
00358 
00359 /*! @brief Format value for bitfield LLWU_PE2_WUPE5. */
00360 #define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
00361 
00362 /*! @brief Set the WUPE5 field to a new value. */
00363 #define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
00364 /*@}*/
00365 
00366 /*!
00367  * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
00368  *
00369  * Enables and configures the edge detection for the wakeup pin.
00370  *
00371  * Values:
00372  * - 00 - External input pin disabled as wakeup input
00373  * - 01 - External input pin enabled with rising edge detection
00374  * - 10 - External input pin enabled with falling edge detection
00375  * - 11 - External input pin enabled with any change detection
00376  */
00377 /*@{*/
00378 #define BP_LLWU_PE2_WUPE6    (4U)          /*!< Bit position for LLWU_PE2_WUPE6. */
00379 #define BM_LLWU_PE2_WUPE6    (0x30U)       /*!< Bit mask for LLWU_PE2_WUPE6. */
00380 #define BS_LLWU_PE2_WUPE6    (2U)          /*!< Bit field size in bits for LLWU_PE2_WUPE6. */
00381 
00382 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
00383 #define BR_LLWU_PE2_WUPE6(x) (UNION_READ(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x), U, B.WUPE6))
00384 
00385 /*! @brief Format value for bitfield LLWU_PE2_WUPE6. */
00386 #define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
00387 
00388 /*! @brief Set the WUPE6 field to a new value. */
00389 #define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
00390 /*@}*/
00391 
00392 /*!
00393  * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
00394  *
00395  * Enables and configures the edge detection for the wakeup pin.
00396  *
00397  * Values:
00398  * - 00 - External input pin disabled as wakeup input
00399  * - 01 - External input pin enabled with rising edge detection
00400  * - 10 - External input pin enabled with falling edge detection
00401  * - 11 - External input pin enabled with any change detection
00402  */
00403 /*@{*/
00404 #define BP_LLWU_PE2_WUPE7    (6U)          /*!< Bit position for LLWU_PE2_WUPE7. */
00405 #define BM_LLWU_PE2_WUPE7    (0xC0U)       /*!< Bit mask for LLWU_PE2_WUPE7. */
00406 #define BS_LLWU_PE2_WUPE7    (2U)          /*!< Bit field size in bits for LLWU_PE2_WUPE7. */
00407 
00408 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
00409 #define BR_LLWU_PE2_WUPE7(x) (UNION_READ(hw_llwu_pe2_t, HW_LLWU_PE2_ADDR(x), U, B.WUPE7))
00410 
00411 /*! @brief Format value for bitfield LLWU_PE2_WUPE7. */
00412 #define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
00413 
00414 /*! @brief Set the WUPE7 field to a new value. */
00415 #define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
00416 /*@}*/
00417 
00418 /*******************************************************************************
00419  * HW_LLWU_PE3 - LLWU Pin Enable 3 register
00420  ******************************************************************************/
00421 
00422 /*!
00423  * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
00424  *
00425  * Reset value: 0x00U
00426  *
00427  * LLWU_PE3 contains the field to enable and select the edge detect type for the
00428  * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
00429  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
00430  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
00431  * IntroductionInformation found here describes the registers of the Reset Control Module
00432  * (RCM). The RCM implements many of the reset functions for the chip. See the
00433  * chip's reset chapter for more information. details for more information.
00434  */
00435 typedef union _hw_llwu_pe3
00436 {
00437     uint8_t U;
00438     struct _hw_llwu_pe3_bitfields
00439     {
00440         uint8_t WUPE8 : 2;             /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */
00441         uint8_t WUPE9 : 2;             /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */
00442         uint8_t WUPE10 : 2;            /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */
00443         uint8_t WUPE11 : 2;            /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */
00444     } B;
00445 } hw_llwu_pe3_t;
00446 
00447 /*!
00448  * @name Constants and macros for entire LLWU_PE3 register
00449  */
00450 /*@{*/
00451 #define HW_LLWU_PE3_ADDR(x)      ((x) + 0x2U)
00452 
00453 #define HW_LLWU_PE3(x)           (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x))
00454 #define HW_LLWU_PE3_RD(x)        (ADDRESS_READ(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x)))
00455 #define HW_LLWU_PE3_WR(x, v)     (ADDRESS_WRITE(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x), v))
00456 #define HW_LLWU_PE3_SET(x, v)    (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) |  (v)))
00457 #define HW_LLWU_PE3_CLR(x, v)    (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
00458 #define HW_LLWU_PE3_TOG(x, v)    (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^  (v)))
00459 /*@}*/
00460 
00461 /*
00462  * Constants & macros for individual LLWU_PE3 bitfields
00463  */
00464 
00465 /*!
00466  * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
00467  *
00468  * Enables and configures the edge detection for the wakeup pin.
00469  *
00470  * Values:
00471  * - 00 - External input pin disabled as wakeup input
00472  * - 01 - External input pin enabled with rising edge detection
00473  * - 10 - External input pin enabled with falling edge detection
00474  * - 11 - External input pin enabled with any change detection
00475  */
00476 /*@{*/
00477 #define BP_LLWU_PE3_WUPE8    (0U)          /*!< Bit position for LLWU_PE3_WUPE8. */
00478 #define BM_LLWU_PE3_WUPE8    (0x03U)       /*!< Bit mask for LLWU_PE3_WUPE8. */
00479 #define BS_LLWU_PE3_WUPE8    (2U)          /*!< Bit field size in bits for LLWU_PE3_WUPE8. */
00480 
00481 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
00482 #define BR_LLWU_PE3_WUPE8(x) (UNION_READ(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x), U, B.WUPE8))
00483 
00484 /*! @brief Format value for bitfield LLWU_PE3_WUPE8. */
00485 #define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
00486 
00487 /*! @brief Set the WUPE8 field to a new value. */
00488 #define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
00489 /*@}*/
00490 
00491 /*!
00492  * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
00493  *
00494  * Enables and configures the edge detection for the wakeup pin.
00495  *
00496  * Values:
00497  * - 00 - External input pin disabled as wakeup input
00498  * - 01 - External input pin enabled with rising edge detection
00499  * - 10 - External input pin enabled with falling edge detection
00500  * - 11 - External input pin enabled with any change detection
00501  */
00502 /*@{*/
00503 #define BP_LLWU_PE3_WUPE9    (2U)          /*!< Bit position for LLWU_PE3_WUPE9. */
00504 #define BM_LLWU_PE3_WUPE9    (0x0CU)       /*!< Bit mask for LLWU_PE3_WUPE9. */
00505 #define BS_LLWU_PE3_WUPE9    (2U)          /*!< Bit field size in bits for LLWU_PE3_WUPE9. */
00506 
00507 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
00508 #define BR_LLWU_PE3_WUPE9(x) (UNION_READ(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x), U, B.WUPE9))
00509 
00510 /*! @brief Format value for bitfield LLWU_PE3_WUPE9. */
00511 #define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
00512 
00513 /*! @brief Set the WUPE9 field to a new value. */
00514 #define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
00515 /*@}*/
00516 
00517 /*!
00518  * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
00519  *
00520  * Enables and configures the edge detection for the wakeup pin.
00521  *
00522  * Values:
00523  * - 00 - External input pin disabled as wakeup input
00524  * - 01 - External input pin enabled with rising edge detection
00525  * - 10 - External input pin enabled with falling edge detection
00526  * - 11 - External input pin enabled with any change detection
00527  */
00528 /*@{*/
00529 #define BP_LLWU_PE3_WUPE10   (4U)          /*!< Bit position for LLWU_PE3_WUPE10. */
00530 #define BM_LLWU_PE3_WUPE10   (0x30U)       /*!< Bit mask for LLWU_PE3_WUPE10. */
00531 #define BS_LLWU_PE3_WUPE10   (2U)          /*!< Bit field size in bits for LLWU_PE3_WUPE10. */
00532 
00533 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
00534 #define BR_LLWU_PE3_WUPE10(x) (UNION_READ(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x), U, B.WUPE10))
00535 
00536 /*! @brief Format value for bitfield LLWU_PE3_WUPE10. */
00537 #define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
00538 
00539 /*! @brief Set the WUPE10 field to a new value. */
00540 #define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
00541 /*@}*/
00542 
00543 /*!
00544  * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
00545  *
00546  * Enables and configures the edge detection for the wakeup pin.
00547  *
00548  * Values:
00549  * - 00 - External input pin disabled as wakeup input
00550  * - 01 - External input pin enabled with rising edge detection
00551  * - 10 - External input pin enabled with falling edge detection
00552  * - 11 - External input pin enabled with any change detection
00553  */
00554 /*@{*/
00555 #define BP_LLWU_PE3_WUPE11   (6U)          /*!< Bit position for LLWU_PE3_WUPE11. */
00556 #define BM_LLWU_PE3_WUPE11   (0xC0U)       /*!< Bit mask for LLWU_PE3_WUPE11. */
00557 #define BS_LLWU_PE3_WUPE11   (2U)          /*!< Bit field size in bits for LLWU_PE3_WUPE11. */
00558 
00559 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
00560 #define BR_LLWU_PE3_WUPE11(x) (UNION_READ(hw_llwu_pe3_t, HW_LLWU_PE3_ADDR(x), U, B.WUPE11))
00561 
00562 /*! @brief Format value for bitfield LLWU_PE3_WUPE11. */
00563 #define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
00564 
00565 /*! @brief Set the WUPE11 field to a new value. */
00566 #define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
00567 /*@}*/
00568 
00569 /*******************************************************************************
00570  * HW_LLWU_PE4 - LLWU Pin Enable 4 register
00571  ******************************************************************************/
00572 
00573 /*!
00574  * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
00575  *
00576  * Reset value: 0x00U
00577  *
00578  * LLWU_PE4 contains the field to enable and select the edge detect type for the
00579  * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
00580  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
00581  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
00582  * IntroductionInformation found here describes the registers of the Reset Control
00583  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
00584  * chip's reset chapter for more information. details for more information.
00585  */
00586 typedef union _hw_llwu_pe4
00587 {
00588     uint8_t U;
00589     struct _hw_llwu_pe4_bitfields
00590     {
00591         uint8_t WUPE12 : 2;            /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */
00592         uint8_t WUPE13 : 2;            /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */
00593         uint8_t WUPE14 : 2;            /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */
00594         uint8_t WUPE15 : 2;            /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */
00595     } B;
00596 } hw_llwu_pe4_t;
00597 
00598 /*!
00599  * @name Constants and macros for entire LLWU_PE4 register
00600  */
00601 /*@{*/
00602 #define HW_LLWU_PE4_ADDR(x)      ((x) + 0x3U)
00603 
00604 #define HW_LLWU_PE4(x)           (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x))
00605 #define HW_LLWU_PE4_RD(x)        (ADDRESS_READ(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x)))
00606 #define HW_LLWU_PE4_WR(x, v)     (ADDRESS_WRITE(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x), v))
00607 #define HW_LLWU_PE4_SET(x, v)    (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) |  (v)))
00608 #define HW_LLWU_PE4_CLR(x, v)    (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
00609 #define HW_LLWU_PE4_TOG(x, v)    (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^  (v)))
00610 /*@}*/
00611 
00612 /*
00613  * Constants & macros for individual LLWU_PE4 bitfields
00614  */
00615 
00616 /*!
00617  * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
00618  *
00619  * Enables and configures the edge detection for the wakeup pin.
00620  *
00621  * Values:
00622  * - 00 - External input pin disabled as wakeup input
00623  * - 01 - External input pin enabled with rising edge detection
00624  * - 10 - External input pin enabled with falling edge detection
00625  * - 11 - External input pin enabled with any change detection
00626  */
00627 /*@{*/
00628 #define BP_LLWU_PE4_WUPE12   (0U)          /*!< Bit position for LLWU_PE4_WUPE12. */
00629 #define BM_LLWU_PE4_WUPE12   (0x03U)       /*!< Bit mask for LLWU_PE4_WUPE12. */
00630 #define BS_LLWU_PE4_WUPE12   (2U)          /*!< Bit field size in bits for LLWU_PE4_WUPE12. */
00631 
00632 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
00633 #define BR_LLWU_PE4_WUPE12(x) (UNION_READ(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x), U, B.WUPE12))
00634 
00635 /*! @brief Format value for bitfield LLWU_PE4_WUPE12. */
00636 #define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
00637 
00638 /*! @brief Set the WUPE12 field to a new value. */
00639 #define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
00640 /*@}*/
00641 
00642 /*!
00643  * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
00644  *
00645  * Enables and configures the edge detection for the wakeup pin.
00646  *
00647  * Values:
00648  * - 00 - External input pin disabled as wakeup input
00649  * - 01 - External input pin enabled with rising edge detection
00650  * - 10 - External input pin enabled with falling edge detection
00651  * - 11 - External input pin enabled with any change detection
00652  */
00653 /*@{*/
00654 #define BP_LLWU_PE4_WUPE13   (2U)          /*!< Bit position for LLWU_PE4_WUPE13. */
00655 #define BM_LLWU_PE4_WUPE13   (0x0CU)       /*!< Bit mask for LLWU_PE4_WUPE13. */
00656 #define BS_LLWU_PE4_WUPE13   (2U)          /*!< Bit field size in bits for LLWU_PE4_WUPE13. */
00657 
00658 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
00659 #define BR_LLWU_PE4_WUPE13(x) (UNION_READ(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x), U, B.WUPE13))
00660 
00661 /*! @brief Format value for bitfield LLWU_PE4_WUPE13. */
00662 #define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
00663 
00664 /*! @brief Set the WUPE13 field to a new value. */
00665 #define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
00666 /*@}*/
00667 
00668 /*!
00669  * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
00670  *
00671  * Enables and configures the edge detection for the wakeup pin.
00672  *
00673  * Values:
00674  * - 00 - External input pin disabled as wakeup input
00675  * - 01 - External input pin enabled with rising edge detection
00676  * - 10 - External input pin enabled with falling edge detection
00677  * - 11 - External input pin enabled with any change detection
00678  */
00679 /*@{*/
00680 #define BP_LLWU_PE4_WUPE14   (4U)          /*!< Bit position for LLWU_PE4_WUPE14. */
00681 #define BM_LLWU_PE4_WUPE14   (0x30U)       /*!< Bit mask for LLWU_PE4_WUPE14. */
00682 #define BS_LLWU_PE4_WUPE14   (2U)          /*!< Bit field size in bits for LLWU_PE4_WUPE14. */
00683 
00684 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
00685 #define BR_LLWU_PE4_WUPE14(x) (UNION_READ(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x), U, B.WUPE14))
00686 
00687 /*! @brief Format value for bitfield LLWU_PE4_WUPE14. */
00688 #define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
00689 
00690 /*! @brief Set the WUPE14 field to a new value. */
00691 #define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
00692 /*@}*/
00693 
00694 /*!
00695  * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
00696  *
00697  * Enables and configures the edge detection for the wakeup pin.
00698  *
00699  * Values:
00700  * - 00 - External input pin disabled as wakeup input
00701  * - 01 - External input pin enabled with rising edge detection
00702  * - 10 - External input pin enabled with falling edge detection
00703  * - 11 - External input pin enabled with any change detection
00704  */
00705 /*@{*/
00706 #define BP_LLWU_PE4_WUPE15   (6U)          /*!< Bit position for LLWU_PE4_WUPE15. */
00707 #define BM_LLWU_PE4_WUPE15   (0xC0U)       /*!< Bit mask for LLWU_PE4_WUPE15. */
00708 #define BS_LLWU_PE4_WUPE15   (2U)          /*!< Bit field size in bits for LLWU_PE4_WUPE15. */
00709 
00710 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
00711 #define BR_LLWU_PE4_WUPE15(x) (UNION_READ(hw_llwu_pe4_t, HW_LLWU_PE4_ADDR(x), U, B.WUPE15))
00712 
00713 /*! @brief Format value for bitfield LLWU_PE4_WUPE15. */
00714 #define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
00715 
00716 /*! @brief Set the WUPE15 field to a new value. */
00717 #define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
00718 /*@}*/
00719 
00720 /*******************************************************************************
00721  * HW_LLWU_ME - LLWU Module Enable register
00722  ******************************************************************************/
00723 
00724 /*!
00725  * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
00726  *
00727  * Reset value: 0x00U
00728  *
00729  * LLWU_ME contains the bits to enable the internal module flag as a wakeup
00730  * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
00731  * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
00732  * reset types that do not trigger Chip Reset not VLLS. See the
00733  * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
00734  * RCM implements many of the reset functions for the chip. See the chip's reset
00735  * chapter for more information. details for more information.
00736  */
00737 typedef union _hw_llwu_me
00738 {
00739     uint8_t U;
00740     struct _hw_llwu_me_bitfields
00741     {
00742         uint8_t WUME0 : 1;             /*!< [0] Wakeup Module Enable For Module 0 */
00743         uint8_t WUME1 : 1;             /*!< [1] Wakeup Module Enable for Module 1 */
00744         uint8_t WUME2 : 1;             /*!< [2] Wakeup Module Enable For Module 2 */
00745         uint8_t WUME3 : 1;             /*!< [3] Wakeup Module Enable For Module 3 */
00746         uint8_t WUME4 : 1;             /*!< [4] Wakeup Module Enable For Module 4 */
00747         uint8_t WUME5 : 1;             /*!< [5] Wakeup Module Enable For Module 5 */
00748         uint8_t WUME6 : 1;             /*!< [6] Wakeup Module Enable For Module 6 */
00749         uint8_t WUME7 : 1;             /*!< [7] Wakeup Module Enable For Module 7 */
00750     } B;
00751 } hw_llwu_me_t;
00752 
00753 /*!
00754  * @name Constants and macros for entire LLWU_ME register
00755  */
00756 /*@{*/
00757 #define HW_LLWU_ME_ADDR(x)       ((x) + 0x4U)
00758 
00759 #define HW_LLWU_ME(x)            (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x))
00760 #define HW_LLWU_ME_RD(x)         (ADDRESS_READ(hw_llwu_me_t, HW_LLWU_ME_ADDR(x)))
00761 #define HW_LLWU_ME_WR(x, v)      (ADDRESS_WRITE(hw_llwu_me_t, HW_LLWU_ME_ADDR(x), v))
00762 #define HW_LLWU_ME_SET(x, v)     (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) |  (v)))
00763 #define HW_LLWU_ME_CLR(x, v)     (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
00764 #define HW_LLWU_ME_TOG(x, v)     (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^  (v)))
00765 /*@}*/
00766 
00767 /*
00768  * Constants & macros for individual LLWU_ME bitfields
00769  */
00770 
00771 /*!
00772  * @name Register LLWU_ME, field WUME0[0] (RW)
00773  *
00774  * Enables an internal module as a wakeup source input.
00775  *
00776  * Values:
00777  * - 0 - Internal module flag not used as wakeup source
00778  * - 1 - Internal module flag used as wakeup source
00779  */
00780 /*@{*/
00781 #define BP_LLWU_ME_WUME0     (0U)          /*!< Bit position for LLWU_ME_WUME0. */
00782 #define BM_LLWU_ME_WUME0     (0x01U)       /*!< Bit mask for LLWU_ME_WUME0. */
00783 #define BS_LLWU_ME_WUME0     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME0. */
00784 
00785 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
00786 #define BR_LLWU_ME_WUME0(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0)))
00787 
00788 /*! @brief Format value for bitfield LLWU_ME_WUME0. */
00789 #define BF_LLWU_ME_WUME0(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
00790 
00791 /*! @brief Set the WUME0 field to a new value. */
00792 #define BW_LLWU_ME_WUME0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0), v))
00793 /*@}*/
00794 
00795 /*!
00796  * @name Register LLWU_ME, field WUME1[1] (RW)
00797  *
00798  * Enables an internal module as a wakeup source input.
00799  *
00800  * Values:
00801  * - 0 - Internal module flag not used as wakeup source
00802  * - 1 - Internal module flag used as wakeup source
00803  */
00804 /*@{*/
00805 #define BP_LLWU_ME_WUME1     (1U)          /*!< Bit position for LLWU_ME_WUME1. */
00806 #define BM_LLWU_ME_WUME1     (0x02U)       /*!< Bit mask for LLWU_ME_WUME1. */
00807 #define BS_LLWU_ME_WUME1     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME1. */
00808 
00809 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
00810 #define BR_LLWU_ME_WUME1(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1)))
00811 
00812 /*! @brief Format value for bitfield LLWU_ME_WUME1. */
00813 #define BF_LLWU_ME_WUME1(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
00814 
00815 /*! @brief Set the WUME1 field to a new value. */
00816 #define BW_LLWU_ME_WUME1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1), v))
00817 /*@}*/
00818 
00819 /*!
00820  * @name Register LLWU_ME, field WUME2[2] (RW)
00821  *
00822  * Enables an internal module as a wakeup source input.
00823  *
00824  * Values:
00825  * - 0 - Internal module flag not used as wakeup source
00826  * - 1 - Internal module flag used as wakeup source
00827  */
00828 /*@{*/
00829 #define BP_LLWU_ME_WUME2     (2U)          /*!< Bit position for LLWU_ME_WUME2. */
00830 #define BM_LLWU_ME_WUME2     (0x04U)       /*!< Bit mask for LLWU_ME_WUME2. */
00831 #define BS_LLWU_ME_WUME2     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME2. */
00832 
00833 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
00834 #define BR_LLWU_ME_WUME2(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2)))
00835 
00836 /*! @brief Format value for bitfield LLWU_ME_WUME2. */
00837 #define BF_LLWU_ME_WUME2(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
00838 
00839 /*! @brief Set the WUME2 field to a new value. */
00840 #define BW_LLWU_ME_WUME2(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2), v))
00841 /*@}*/
00842 
00843 /*!
00844  * @name Register LLWU_ME, field WUME3[3] (RW)
00845  *
00846  * Enables an internal module as a wakeup source input.
00847  *
00848  * Values:
00849  * - 0 - Internal module flag not used as wakeup source
00850  * - 1 - Internal module flag used as wakeup source
00851  */
00852 /*@{*/
00853 #define BP_LLWU_ME_WUME3     (3U)          /*!< Bit position for LLWU_ME_WUME3. */
00854 #define BM_LLWU_ME_WUME3     (0x08U)       /*!< Bit mask for LLWU_ME_WUME3. */
00855 #define BS_LLWU_ME_WUME3     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME3. */
00856 
00857 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
00858 #define BR_LLWU_ME_WUME3(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3)))
00859 
00860 /*! @brief Format value for bitfield LLWU_ME_WUME3. */
00861 #define BF_LLWU_ME_WUME3(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
00862 
00863 /*! @brief Set the WUME3 field to a new value. */
00864 #define BW_LLWU_ME_WUME3(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3), v))
00865 /*@}*/
00866 
00867 /*!
00868  * @name Register LLWU_ME, field WUME4[4] (RW)
00869  *
00870  * Enables an internal module as a wakeup source input.
00871  *
00872  * Values:
00873  * - 0 - Internal module flag not used as wakeup source
00874  * - 1 - Internal module flag used as wakeup source
00875  */
00876 /*@{*/
00877 #define BP_LLWU_ME_WUME4     (4U)          /*!< Bit position for LLWU_ME_WUME4. */
00878 #define BM_LLWU_ME_WUME4     (0x10U)       /*!< Bit mask for LLWU_ME_WUME4. */
00879 #define BS_LLWU_ME_WUME4     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME4. */
00880 
00881 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
00882 #define BR_LLWU_ME_WUME4(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4)))
00883 
00884 /*! @brief Format value for bitfield LLWU_ME_WUME4. */
00885 #define BF_LLWU_ME_WUME4(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
00886 
00887 /*! @brief Set the WUME4 field to a new value. */
00888 #define BW_LLWU_ME_WUME4(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4), v))
00889 /*@}*/
00890 
00891 /*!
00892  * @name Register LLWU_ME, field WUME5[5] (RW)
00893  *
00894  * Enables an internal module as a wakeup source input.
00895  *
00896  * Values:
00897  * - 0 - Internal module flag not used as wakeup source
00898  * - 1 - Internal module flag used as wakeup source
00899  */
00900 /*@{*/
00901 #define BP_LLWU_ME_WUME5     (5U)          /*!< Bit position for LLWU_ME_WUME5. */
00902 #define BM_LLWU_ME_WUME5     (0x20U)       /*!< Bit mask for LLWU_ME_WUME5. */
00903 #define BS_LLWU_ME_WUME5     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME5. */
00904 
00905 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
00906 #define BR_LLWU_ME_WUME5(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5)))
00907 
00908 /*! @brief Format value for bitfield LLWU_ME_WUME5. */
00909 #define BF_LLWU_ME_WUME5(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
00910 
00911 /*! @brief Set the WUME5 field to a new value. */
00912 #define BW_LLWU_ME_WUME5(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5), v))
00913 /*@}*/
00914 
00915 /*!
00916  * @name Register LLWU_ME, field WUME6[6] (RW)
00917  *
00918  * Enables an internal module as a wakeup source input.
00919  *
00920  * Values:
00921  * - 0 - Internal module flag not used as wakeup source
00922  * - 1 - Internal module flag used as wakeup source
00923  */
00924 /*@{*/
00925 #define BP_LLWU_ME_WUME6     (6U)          /*!< Bit position for LLWU_ME_WUME6. */
00926 #define BM_LLWU_ME_WUME6     (0x40U)       /*!< Bit mask for LLWU_ME_WUME6. */
00927 #define BS_LLWU_ME_WUME6     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME6. */
00928 
00929 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
00930 #define BR_LLWU_ME_WUME6(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6)))
00931 
00932 /*! @brief Format value for bitfield LLWU_ME_WUME6. */
00933 #define BF_LLWU_ME_WUME6(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
00934 
00935 /*! @brief Set the WUME6 field to a new value. */
00936 #define BW_LLWU_ME_WUME6(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6), v))
00937 /*@}*/
00938 
00939 /*!
00940  * @name Register LLWU_ME, field WUME7[7] (RW)
00941  *
00942  * Enables an internal module as a wakeup source input.
00943  *
00944  * Values:
00945  * - 0 - Internal module flag not used as wakeup source
00946  * - 1 - Internal module flag used as wakeup source
00947  */
00948 /*@{*/
00949 #define BP_LLWU_ME_WUME7     (7U)          /*!< Bit position for LLWU_ME_WUME7. */
00950 #define BM_LLWU_ME_WUME7     (0x80U)       /*!< Bit mask for LLWU_ME_WUME7. */
00951 #define BS_LLWU_ME_WUME7     (1U)          /*!< Bit field size in bits for LLWU_ME_WUME7. */
00952 
00953 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
00954 #define BR_LLWU_ME_WUME7(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7)))
00955 
00956 /*! @brief Format value for bitfield LLWU_ME_WUME7. */
00957 #define BF_LLWU_ME_WUME7(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
00958 
00959 /*! @brief Set the WUME7 field to a new value. */
00960 #define BW_LLWU_ME_WUME7(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7), v))
00961 /*@}*/
00962 
00963 /*******************************************************************************
00964  * HW_LLWU_F1 - LLWU Flag 1 register
00965  ******************************************************************************/
00966 
00967 /*!
00968  * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
00969  *
00970  * Reset value: 0x00U
00971  *
00972  * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
00973  * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
00974  * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
00975  * external wakeup flags are read-only and clearing a flag is accomplished by a write
00976  * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
00977  * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
00978  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
00979  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
00980  * IntroductionInformation found here describes the registers of the Reset Control
00981  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
00982  * chip's reset chapter for more information. details for more information.
00983  */
00984 typedef union _hw_llwu_f1
00985 {
00986     uint8_t U;
00987     struct _hw_llwu_f1_bitfields
00988     {
00989         uint8_t WUF0 : 1;              /*!< [0] Wakeup Flag For LLWU_P0 */
00990         uint8_t WUF1 : 1;              /*!< [1] Wakeup Flag For LLWU_P1 */
00991         uint8_t WUF2 : 1;              /*!< [2] Wakeup Flag For LLWU_P2 */
00992         uint8_t WUF3 : 1;              /*!< [3] Wakeup Flag For LLWU_P3 */
00993         uint8_t WUF4 : 1;              /*!< [4] Wakeup Flag For LLWU_P4 */
00994         uint8_t WUF5 : 1;              /*!< [5] Wakeup Flag For LLWU_P5 */
00995         uint8_t WUF6 : 1;              /*!< [6] Wakeup Flag For LLWU_P6 */
00996         uint8_t WUF7 : 1;              /*!< [7] Wakeup Flag For LLWU_P7 */
00997     } B;
00998 } hw_llwu_f1_t;
00999 
01000 /*!
01001  * @name Constants and macros for entire LLWU_F1 register
01002  */
01003 /*@{*/
01004 #define HW_LLWU_F1_ADDR(x)       ((x) + 0x5U)
01005 
01006 #define HW_LLWU_F1(x)            (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x))
01007 #define HW_LLWU_F1_RD(x)         (ADDRESS_READ(hw_llwu_f1_t, HW_LLWU_F1_ADDR(x)))
01008 #define HW_LLWU_F1_WR(x, v)      (ADDRESS_WRITE(hw_llwu_f1_t, HW_LLWU_F1_ADDR(x), v))
01009 #define HW_LLWU_F1_SET(x, v)     (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) |  (v)))
01010 #define HW_LLWU_F1_CLR(x, v)     (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
01011 #define HW_LLWU_F1_TOG(x, v)     (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^  (v)))
01012 /*@}*/
01013 
01014 /*
01015  * Constants & macros for individual LLWU_F1 bitfields
01016  */
01017 
01018 /*!
01019  * @name Register LLWU_F1, field WUF0[0] (W1C)
01020  *
01021  * Indicates that an enabled external wake-up pin was a source of exiting a
01022  * low-leakage power mode. To clear the flag, write a 1 to WUF0.
01023  *
01024  * Values:
01025  * - 0 - LLWU_P0 input was not a wakeup source
01026  * - 1 - LLWU_P0 input was a wakeup source
01027  */
01028 /*@{*/
01029 #define BP_LLWU_F1_WUF0      (0U)          /*!< Bit position for LLWU_F1_WUF0. */
01030 #define BM_LLWU_F1_WUF0      (0x01U)       /*!< Bit mask for LLWU_F1_WUF0. */
01031 #define BS_LLWU_F1_WUF0      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF0. */
01032 
01033 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
01034 #define BR_LLWU_F1_WUF0(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0)))
01035 
01036 /*! @brief Format value for bitfield LLWU_F1_WUF0. */
01037 #define BF_LLWU_F1_WUF0(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
01038 
01039 /*! @brief Set the WUF0 field to a new value. */
01040 #define BW_LLWU_F1_WUF0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0), v))
01041 /*@}*/
01042 
01043 /*!
01044  * @name Register LLWU_F1, field WUF1[1] (W1C)
01045  *
01046  * Indicates that an enabled external wakeup pin was a source of exiting a
01047  * low-leakage power mode. To clear the flag, write a 1 to WUF1.
01048  *
01049  * Values:
01050  * - 0 - LLWU_P1 input was not a wakeup source
01051  * - 1 - LLWU_P1 input was a wakeup source
01052  */
01053 /*@{*/
01054 #define BP_LLWU_F1_WUF1      (1U)          /*!< Bit position for LLWU_F1_WUF1. */
01055 #define BM_LLWU_F1_WUF1      (0x02U)       /*!< Bit mask for LLWU_F1_WUF1. */
01056 #define BS_LLWU_F1_WUF1      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF1. */
01057 
01058 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
01059 #define BR_LLWU_F1_WUF1(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1)))
01060 
01061 /*! @brief Format value for bitfield LLWU_F1_WUF1. */
01062 #define BF_LLWU_F1_WUF1(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
01063 
01064 /*! @brief Set the WUF1 field to a new value. */
01065 #define BW_LLWU_F1_WUF1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1), v))
01066 /*@}*/
01067 
01068 /*!
01069  * @name Register LLWU_F1, field WUF2[2] (W1C)
01070  *
01071  * Indicates that an enabled external wakeup pin was a source of exiting a
01072  * low-leakage power mode. To clear the flag, write a 1 to WUF2.
01073  *
01074  * Values:
01075  * - 0 - LLWU_P2 input was not a wakeup source
01076  * - 1 - LLWU_P2 input was a wakeup source
01077  */
01078 /*@{*/
01079 #define BP_LLWU_F1_WUF2      (2U)          /*!< Bit position for LLWU_F1_WUF2. */
01080 #define BM_LLWU_F1_WUF2      (0x04U)       /*!< Bit mask for LLWU_F1_WUF2. */
01081 #define BS_LLWU_F1_WUF2      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF2. */
01082 
01083 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
01084 #define BR_LLWU_F1_WUF2(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2)))
01085 
01086 /*! @brief Format value for bitfield LLWU_F1_WUF2. */
01087 #define BF_LLWU_F1_WUF2(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
01088 
01089 /*! @brief Set the WUF2 field to a new value. */
01090 #define BW_LLWU_F1_WUF2(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2), v))
01091 /*@}*/
01092 
01093 /*!
01094  * @name Register LLWU_F1, field WUF3[3] (W1C)
01095  *
01096  * Indicates that an enabled external wakeup pin was a source of exiting a
01097  * low-leakage power mode. To clear the flag, write a 1 to WUF3.
01098  *
01099  * Values:
01100  * - 0 - LLWU_P3 input was not a wake-up source
01101  * - 1 - LLWU_P3 input was a wake-up source
01102  */
01103 /*@{*/
01104 #define BP_LLWU_F1_WUF3      (3U)          /*!< Bit position for LLWU_F1_WUF3. */
01105 #define BM_LLWU_F1_WUF3      (0x08U)       /*!< Bit mask for LLWU_F1_WUF3. */
01106 #define BS_LLWU_F1_WUF3      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF3. */
01107 
01108 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
01109 #define BR_LLWU_F1_WUF3(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3)))
01110 
01111 /*! @brief Format value for bitfield LLWU_F1_WUF3. */
01112 #define BF_LLWU_F1_WUF3(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
01113 
01114 /*! @brief Set the WUF3 field to a new value. */
01115 #define BW_LLWU_F1_WUF3(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3), v))
01116 /*@}*/
01117 
01118 /*!
01119  * @name Register LLWU_F1, field WUF4[4] (W1C)
01120  *
01121  * Indicates that an enabled external wake-up pin was a source of exiting a
01122  * low-leakage power mode. To clear the flag, write a 1 to WUF4.
01123  *
01124  * Values:
01125  * - 0 - LLWU_P4 input was not a wakeup source
01126  * - 1 - LLWU_P4 input was a wakeup source
01127  */
01128 /*@{*/
01129 #define BP_LLWU_F1_WUF4      (4U)          /*!< Bit position for LLWU_F1_WUF4. */
01130 #define BM_LLWU_F1_WUF4      (0x10U)       /*!< Bit mask for LLWU_F1_WUF4. */
01131 #define BS_LLWU_F1_WUF4      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF4. */
01132 
01133 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
01134 #define BR_LLWU_F1_WUF4(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4)))
01135 
01136 /*! @brief Format value for bitfield LLWU_F1_WUF4. */
01137 #define BF_LLWU_F1_WUF4(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
01138 
01139 /*! @brief Set the WUF4 field to a new value. */
01140 #define BW_LLWU_F1_WUF4(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4), v))
01141 /*@}*/
01142 
01143 /*!
01144  * @name Register LLWU_F1, field WUF5[5] (W1C)
01145  *
01146  * Indicates that an enabled external wakeup pin was a source of exiting a
01147  * low-leakage power mode. To clear the flag, write a 1 to WUF5.
01148  *
01149  * Values:
01150  * - 0 - LLWU_P5 input was not a wakeup source
01151  * - 1 - LLWU_P5 input was a wakeup source
01152  */
01153 /*@{*/
01154 #define BP_LLWU_F1_WUF5      (5U)          /*!< Bit position for LLWU_F1_WUF5. */
01155 #define BM_LLWU_F1_WUF5      (0x20U)       /*!< Bit mask for LLWU_F1_WUF5. */
01156 #define BS_LLWU_F1_WUF5      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF5. */
01157 
01158 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
01159 #define BR_LLWU_F1_WUF5(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5)))
01160 
01161 /*! @brief Format value for bitfield LLWU_F1_WUF5. */
01162 #define BF_LLWU_F1_WUF5(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
01163 
01164 /*! @brief Set the WUF5 field to a new value. */
01165 #define BW_LLWU_F1_WUF5(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5), v))
01166 /*@}*/
01167 
01168 /*!
01169  * @name Register LLWU_F1, field WUF6[6] (W1C)
01170  *
01171  * Indicates that an enabled external wakeup pin was a source of exiting a
01172  * low-leakage power mode. To clear the flag, write a 1 to WUF6.
01173  *
01174  * Values:
01175  * - 0 - LLWU_P6 input was not a wakeup source
01176  * - 1 - LLWU_P6 input was a wakeup source
01177  */
01178 /*@{*/
01179 #define BP_LLWU_F1_WUF6      (6U)          /*!< Bit position for LLWU_F1_WUF6. */
01180 #define BM_LLWU_F1_WUF6      (0x40U)       /*!< Bit mask for LLWU_F1_WUF6. */
01181 #define BS_LLWU_F1_WUF6      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF6. */
01182 
01183 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
01184 #define BR_LLWU_F1_WUF6(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6)))
01185 
01186 /*! @brief Format value for bitfield LLWU_F1_WUF6. */
01187 #define BF_LLWU_F1_WUF6(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
01188 
01189 /*! @brief Set the WUF6 field to a new value. */
01190 #define BW_LLWU_F1_WUF6(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6), v))
01191 /*@}*/
01192 
01193 /*!
01194  * @name Register LLWU_F1, field WUF7[7] (W1C)
01195  *
01196  * Indicates that an enabled external wakeup pin was a source of exiting a
01197  * low-leakage power mode. To clear the flag, write a 1 to WUF7.
01198  *
01199  * Values:
01200  * - 0 - LLWU_P7 input was not a wakeup source
01201  * - 1 - LLWU_P7 input was a wakeup source
01202  */
01203 /*@{*/
01204 #define BP_LLWU_F1_WUF7      (7U)          /*!< Bit position for LLWU_F1_WUF7. */
01205 #define BM_LLWU_F1_WUF7      (0x80U)       /*!< Bit mask for LLWU_F1_WUF7. */
01206 #define BS_LLWU_F1_WUF7      (1U)          /*!< Bit field size in bits for LLWU_F1_WUF7. */
01207 
01208 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
01209 #define BR_LLWU_F1_WUF7(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7)))
01210 
01211 /*! @brief Format value for bitfield LLWU_F1_WUF7. */
01212 #define BF_LLWU_F1_WUF7(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
01213 
01214 /*! @brief Set the WUF7 field to a new value. */
01215 #define BW_LLWU_F1_WUF7(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7), v))
01216 /*@}*/
01217 
01218 /*******************************************************************************
01219  * HW_LLWU_F2 - LLWU Flag 2 register
01220  ******************************************************************************/
01221 
01222 /*!
01223  * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
01224  *
01225  * Reset value: 0x00U
01226  *
01227  * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
01228  * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
01229  * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
01230  * external wakeup flags are read-only and clearing a flag is accomplished by a write
01231  * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
01232  * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
01233  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
01234  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
01235  * IntroductionInformation found here describes the registers of the Reset Control
01236  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
01237  * chip's reset chapter for more information. details for more information.
01238  */
01239 typedef union _hw_llwu_f2
01240 {
01241     uint8_t U;
01242     struct _hw_llwu_f2_bitfields
01243     {
01244         uint8_t WUF8 : 1;              /*!< [0] Wakeup Flag For LLWU_P8 */
01245         uint8_t WUF9 : 1;              /*!< [1] Wakeup Flag For LLWU_P9 */
01246         uint8_t WUF10 : 1;             /*!< [2] Wakeup Flag For LLWU_P10 */
01247         uint8_t WUF11 : 1;             /*!< [3] Wakeup Flag For LLWU_P11 */
01248         uint8_t WUF12 : 1;             /*!< [4] Wakeup Flag For LLWU_P12 */
01249         uint8_t WUF13 : 1;             /*!< [5] Wakeup Flag For LLWU_P13 */
01250         uint8_t WUF14 : 1;             /*!< [6] Wakeup Flag For LLWU_P14 */
01251         uint8_t WUF15 : 1;             /*!< [7] Wakeup Flag For LLWU_P15 */
01252     } B;
01253 } hw_llwu_f2_t;
01254 
01255 /*!
01256  * @name Constants and macros for entire LLWU_F2 register
01257  */
01258 /*@{*/
01259 #define HW_LLWU_F2_ADDR(x)       ((x) + 0x6U)
01260 
01261 #define HW_LLWU_F2(x)            (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x))
01262 #define HW_LLWU_F2_RD(x)         (ADDRESS_READ(hw_llwu_f2_t, HW_LLWU_F2_ADDR(x)))
01263 #define HW_LLWU_F2_WR(x, v)      (ADDRESS_WRITE(hw_llwu_f2_t, HW_LLWU_F2_ADDR(x), v))
01264 #define HW_LLWU_F2_SET(x, v)     (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) |  (v)))
01265 #define HW_LLWU_F2_CLR(x, v)     (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
01266 #define HW_LLWU_F2_TOG(x, v)     (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^  (v)))
01267 /*@}*/
01268 
01269 /*
01270  * Constants & macros for individual LLWU_F2 bitfields
01271  */
01272 
01273 /*!
01274  * @name Register LLWU_F2, field WUF8[0] (W1C)
01275  *
01276  * Indicates that an enabled external wakeup pin was a source of exiting a
01277  * low-leakage power mode. To clear the flag, write a 1 to WUF8.
01278  *
01279  * Values:
01280  * - 0 - LLWU_P8 input was not a wakeup source
01281  * - 1 - LLWU_P8 input was a wakeup source
01282  */
01283 /*@{*/
01284 #define BP_LLWU_F2_WUF8      (0U)          /*!< Bit position for LLWU_F2_WUF8. */
01285 #define BM_LLWU_F2_WUF8      (0x01U)       /*!< Bit mask for LLWU_F2_WUF8. */
01286 #define BS_LLWU_F2_WUF8      (1U)          /*!< Bit field size in bits for LLWU_F2_WUF8. */
01287 
01288 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
01289 #define BR_LLWU_F2_WUF8(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8)))
01290 
01291 /*! @brief Format value for bitfield LLWU_F2_WUF8. */
01292 #define BF_LLWU_F2_WUF8(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
01293 
01294 /*! @brief Set the WUF8 field to a new value. */
01295 #define BW_LLWU_F2_WUF8(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8), v))
01296 /*@}*/
01297 
01298 /*!
01299  * @name Register LLWU_F2, field WUF9[1] (W1C)
01300  *
01301  * Indicates that an enabled external wakeup pin was a source of exiting a
01302  * low-leakage power mode. To clear the flag, write a 1 to WUF9.
01303  *
01304  * Values:
01305  * - 0 - LLWU_P9 input was not a wakeup source
01306  * - 1 - LLWU_P9 input was a wakeup source
01307  */
01308 /*@{*/
01309 #define BP_LLWU_F2_WUF9      (1U)          /*!< Bit position for LLWU_F2_WUF9. */
01310 #define BM_LLWU_F2_WUF9      (0x02U)       /*!< Bit mask for LLWU_F2_WUF9. */
01311 #define BS_LLWU_F2_WUF9      (1U)          /*!< Bit field size in bits for LLWU_F2_WUF9. */
01312 
01313 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
01314 #define BR_LLWU_F2_WUF9(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9)))
01315 
01316 /*! @brief Format value for bitfield LLWU_F2_WUF9. */
01317 #define BF_LLWU_F2_WUF9(v)   ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
01318 
01319 /*! @brief Set the WUF9 field to a new value. */
01320 #define BW_LLWU_F2_WUF9(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9), v))
01321 /*@}*/
01322 
01323 /*!
01324  * @name Register LLWU_F2, field WUF10[2] (W1C)
01325  *
01326  * Indicates that an enabled external wakeup pin was a source of exiting a
01327  * low-leakage power mode. To clear the flag, write a 1 to WUF10.
01328  *
01329  * Values:
01330  * - 0 - LLWU_P10 input was not a wakeup source
01331  * - 1 - LLWU_P10 input was a wakeup source
01332  */
01333 /*@{*/
01334 #define BP_LLWU_F2_WUF10     (2U)          /*!< Bit position for LLWU_F2_WUF10. */
01335 #define BM_LLWU_F2_WUF10     (0x04U)       /*!< Bit mask for LLWU_F2_WUF10. */
01336 #define BS_LLWU_F2_WUF10     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF10. */
01337 
01338 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
01339 #define BR_LLWU_F2_WUF10(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10)))
01340 
01341 /*! @brief Format value for bitfield LLWU_F2_WUF10. */
01342 #define BF_LLWU_F2_WUF10(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
01343 
01344 /*! @brief Set the WUF10 field to a new value. */
01345 #define BW_LLWU_F2_WUF10(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10), v))
01346 /*@}*/
01347 
01348 /*!
01349  * @name Register LLWU_F2, field WUF11[3] (W1C)
01350  *
01351  * Indicates that an enabled external wakeup pin was a source of exiting a
01352  * low-leakage power mode. To clear the flag, write a 1 to WUF11.
01353  *
01354  * Values:
01355  * - 0 - LLWU_P11 input was not a wakeup source
01356  * - 1 - LLWU_P11 input was a wakeup source
01357  */
01358 /*@{*/
01359 #define BP_LLWU_F2_WUF11     (3U)          /*!< Bit position for LLWU_F2_WUF11. */
01360 #define BM_LLWU_F2_WUF11     (0x08U)       /*!< Bit mask for LLWU_F2_WUF11. */
01361 #define BS_LLWU_F2_WUF11     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF11. */
01362 
01363 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
01364 #define BR_LLWU_F2_WUF11(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11)))
01365 
01366 /*! @brief Format value for bitfield LLWU_F2_WUF11. */
01367 #define BF_LLWU_F2_WUF11(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
01368 
01369 /*! @brief Set the WUF11 field to a new value. */
01370 #define BW_LLWU_F2_WUF11(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11), v))
01371 /*@}*/
01372 
01373 /*!
01374  * @name Register LLWU_F2, field WUF12[4] (W1C)
01375  *
01376  * Indicates that an enabled external wakeup pin was a source of exiting a
01377  * low-leakage power mode. To clear the flag, write a 1 to WUF12.
01378  *
01379  * Values:
01380  * - 0 - LLWU_P12 input was not a wakeup source
01381  * - 1 - LLWU_P12 input was a wakeup source
01382  */
01383 /*@{*/
01384 #define BP_LLWU_F2_WUF12     (4U)          /*!< Bit position for LLWU_F2_WUF12. */
01385 #define BM_LLWU_F2_WUF12     (0x10U)       /*!< Bit mask for LLWU_F2_WUF12. */
01386 #define BS_LLWU_F2_WUF12     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF12. */
01387 
01388 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
01389 #define BR_LLWU_F2_WUF12(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12)))
01390 
01391 /*! @brief Format value for bitfield LLWU_F2_WUF12. */
01392 #define BF_LLWU_F2_WUF12(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
01393 
01394 /*! @brief Set the WUF12 field to a new value. */
01395 #define BW_LLWU_F2_WUF12(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12), v))
01396 /*@}*/
01397 
01398 /*!
01399  * @name Register LLWU_F2, field WUF13[5] (W1C)
01400  *
01401  * Indicates that an enabled external wakeup pin was a source of exiting a
01402  * low-leakage power mode. To clear the flag, write a 1 to WUF13.
01403  *
01404  * Values:
01405  * - 0 - LLWU_P13 input was not a wakeup source
01406  * - 1 - LLWU_P13 input was a wakeup source
01407  */
01408 /*@{*/
01409 #define BP_LLWU_F2_WUF13     (5U)          /*!< Bit position for LLWU_F2_WUF13. */
01410 #define BM_LLWU_F2_WUF13     (0x20U)       /*!< Bit mask for LLWU_F2_WUF13. */
01411 #define BS_LLWU_F2_WUF13     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF13. */
01412 
01413 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
01414 #define BR_LLWU_F2_WUF13(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13)))
01415 
01416 /*! @brief Format value for bitfield LLWU_F2_WUF13. */
01417 #define BF_LLWU_F2_WUF13(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
01418 
01419 /*! @brief Set the WUF13 field to a new value. */
01420 #define BW_LLWU_F2_WUF13(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13), v))
01421 /*@}*/
01422 
01423 /*!
01424  * @name Register LLWU_F2, field WUF14[6] (W1C)
01425  *
01426  * Indicates that an enabled external wakeup pin was a source of exiting a
01427  * low-leakage power mode. To clear the flag, write a 1 to WUF14.
01428  *
01429  * Values:
01430  * - 0 - LLWU_P14 input was not a wakeup source
01431  * - 1 - LLWU_P14 input was a wakeup source
01432  */
01433 /*@{*/
01434 #define BP_LLWU_F2_WUF14     (6U)          /*!< Bit position for LLWU_F2_WUF14. */
01435 #define BM_LLWU_F2_WUF14     (0x40U)       /*!< Bit mask for LLWU_F2_WUF14. */
01436 #define BS_LLWU_F2_WUF14     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF14. */
01437 
01438 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
01439 #define BR_LLWU_F2_WUF14(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14)))
01440 
01441 /*! @brief Format value for bitfield LLWU_F2_WUF14. */
01442 #define BF_LLWU_F2_WUF14(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
01443 
01444 /*! @brief Set the WUF14 field to a new value. */
01445 #define BW_LLWU_F2_WUF14(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14), v))
01446 /*@}*/
01447 
01448 /*!
01449  * @name Register LLWU_F2, field WUF15[7] (W1C)
01450  *
01451  * Indicates that an enabled external wakeup pin was a source of exiting a
01452  * low-leakage power mode. To clear the flag, write a 1 to WUF15.
01453  *
01454  * Values:
01455  * - 0 - LLWU_P15 input was not a wakeup source
01456  * - 1 - LLWU_P15 input was a wakeup source
01457  */
01458 /*@{*/
01459 #define BP_LLWU_F2_WUF15     (7U)          /*!< Bit position for LLWU_F2_WUF15. */
01460 #define BM_LLWU_F2_WUF15     (0x80U)       /*!< Bit mask for LLWU_F2_WUF15. */
01461 #define BS_LLWU_F2_WUF15     (1U)          /*!< Bit field size in bits for LLWU_F2_WUF15. */
01462 
01463 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
01464 #define BR_LLWU_F2_WUF15(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15)))
01465 
01466 /*! @brief Format value for bitfield LLWU_F2_WUF15. */
01467 #define BF_LLWU_F2_WUF15(v)  ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
01468 
01469 /*! @brief Set the WUF15 field to a new value. */
01470 #define BW_LLWU_F2_WUF15(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15), v))
01471 /*@}*/
01472 
01473 /*******************************************************************************
01474  * HW_LLWU_F3 - LLWU Flag 3 register
01475  ******************************************************************************/
01476 
01477 /*!
01478  * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
01479  *
01480  * Reset value: 0x00U
01481  *
01482  * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
01483  * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
01484  * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
01485  * For internal peripherals that are capable of running in a low-leakage power
01486  * mode, such as a real time clock module or CMP module, the flag from the
01487  * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
01488  * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
01489  * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
01490  * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
01491  * the IntroductionInformation found here describes the registers of the Reset
01492  * Control Module (RCM). The RCM implements many of the reset functions for the
01493  * chip. See the chip's reset chapter for more information. details for more
01494  * information.
01495  */
01496 typedef union _hw_llwu_f3
01497 {
01498     uint8_t U;
01499     struct _hw_llwu_f3_bitfields
01500     {
01501         uint8_t MWUF0 : 1;             /*!< [0] Wakeup flag For module 0 */
01502         uint8_t MWUF1 : 1;             /*!< [1] Wakeup flag For module 1 */
01503         uint8_t MWUF2 : 1;             /*!< [2] Wakeup flag For module 2 */
01504         uint8_t MWUF3 : 1;             /*!< [3] Wakeup flag For module 3 */
01505         uint8_t MWUF4 : 1;             /*!< [4] Wakeup flag For module 4 */
01506         uint8_t MWUF5 : 1;             /*!< [5] Wakeup flag For module 5 */
01507         uint8_t MWUF6 : 1;             /*!< [6] Wakeup flag For module 6 */
01508         uint8_t MWUF7 : 1;             /*!< [7] Wakeup flag For module 7 */
01509     } B;
01510 } hw_llwu_f3_t;
01511 
01512 /*!
01513  * @name Constants and macros for entire LLWU_F3 register
01514  */
01515 /*@{*/
01516 #define HW_LLWU_F3_ADDR(x)       ((x) + 0x7U)
01517 
01518 #define HW_LLWU_F3(x)            (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x))
01519 #define HW_LLWU_F3_RD(x)         (ADDRESS_READ(hw_llwu_f3_t, HW_LLWU_F3_ADDR(x)))
01520 /*@}*/
01521 
01522 /*
01523  * Constants & macros for individual LLWU_F3 bitfields
01524  */
01525 
01526 /*!
01527  * @name Register LLWU_F3, field MWUF0[0] (RO)
01528  *
01529  * Indicates that an enabled internal peripheral was a source of exiting a
01530  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01531  * clearing mechanism.
01532  *
01533  * Values:
01534  * - 0 - Module 0 input was not a wakeup source
01535  * - 1 - Module 0 input was a wakeup source
01536  */
01537 /*@{*/
01538 #define BP_LLWU_F3_MWUF0     (0U)          /*!< Bit position for LLWU_F3_MWUF0. */
01539 #define BM_LLWU_F3_MWUF0     (0x01U)       /*!< Bit mask for LLWU_F3_MWUF0. */
01540 #define BS_LLWU_F3_MWUF0     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF0. */
01541 
01542 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
01543 #define BR_LLWU_F3_MWUF0(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0)))
01544 /*@}*/
01545 
01546 /*!
01547  * @name Register LLWU_F3, field MWUF1[1] (RO)
01548  *
01549  * Indicates that an enabled internal peripheral was a source of exiting a
01550  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01551  * clearing mechanism.
01552  *
01553  * Values:
01554  * - 0 - Module 1 input was not a wakeup source
01555  * - 1 - Module 1 input was a wakeup source
01556  */
01557 /*@{*/
01558 #define BP_LLWU_F3_MWUF1     (1U)          /*!< Bit position for LLWU_F3_MWUF1. */
01559 #define BM_LLWU_F3_MWUF1     (0x02U)       /*!< Bit mask for LLWU_F3_MWUF1. */
01560 #define BS_LLWU_F3_MWUF1     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF1. */
01561 
01562 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
01563 #define BR_LLWU_F3_MWUF1(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1)))
01564 /*@}*/
01565 
01566 /*!
01567  * @name Register LLWU_F3, field MWUF2[2] (RO)
01568  *
01569  * Indicates that an enabled internal peripheral was a source of exiting a
01570  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01571  * clearing mechanism.
01572  *
01573  * Values:
01574  * - 0 - Module 2 input was not a wakeup source
01575  * - 1 - Module 2 input was a wakeup source
01576  */
01577 /*@{*/
01578 #define BP_LLWU_F3_MWUF2     (2U)          /*!< Bit position for LLWU_F3_MWUF2. */
01579 #define BM_LLWU_F3_MWUF2     (0x04U)       /*!< Bit mask for LLWU_F3_MWUF2. */
01580 #define BS_LLWU_F3_MWUF2     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF2. */
01581 
01582 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
01583 #define BR_LLWU_F3_MWUF2(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2)))
01584 /*@}*/
01585 
01586 /*!
01587  * @name Register LLWU_F3, field MWUF3[3] (RO)
01588  *
01589  * Indicates that an enabled internal peripheral was a source of exiting a
01590  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01591  * clearing mechanism.
01592  *
01593  * Values:
01594  * - 0 - Module 3 input was not a wakeup source
01595  * - 1 - Module 3 input was a wakeup source
01596  */
01597 /*@{*/
01598 #define BP_LLWU_F3_MWUF3     (3U)          /*!< Bit position for LLWU_F3_MWUF3. */
01599 #define BM_LLWU_F3_MWUF3     (0x08U)       /*!< Bit mask for LLWU_F3_MWUF3. */
01600 #define BS_LLWU_F3_MWUF3     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF3. */
01601 
01602 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
01603 #define BR_LLWU_F3_MWUF3(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3)))
01604 /*@}*/
01605 
01606 /*!
01607  * @name Register LLWU_F3, field MWUF4[4] (RO)
01608  *
01609  * Indicates that an enabled internal peripheral was a source of exiting a
01610  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01611  * clearing mechanism.
01612  *
01613  * Values:
01614  * - 0 - Module 4 input was not a wakeup source
01615  * - 1 - Module 4 input was a wakeup source
01616  */
01617 /*@{*/
01618 #define BP_LLWU_F3_MWUF4     (4U)          /*!< Bit position for LLWU_F3_MWUF4. */
01619 #define BM_LLWU_F3_MWUF4     (0x10U)       /*!< Bit mask for LLWU_F3_MWUF4. */
01620 #define BS_LLWU_F3_MWUF4     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF4. */
01621 
01622 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
01623 #define BR_LLWU_F3_MWUF4(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4)))
01624 /*@}*/
01625 
01626 /*!
01627  * @name Register LLWU_F3, field MWUF5[5] (RO)
01628  *
01629  * Indicates that an enabled internal peripheral was a source of exiting a
01630  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01631  * clearing mechanism.
01632  *
01633  * Values:
01634  * - 0 - Module 5 input was not a wakeup source
01635  * - 1 - Module 5 input was a wakeup source
01636  */
01637 /*@{*/
01638 #define BP_LLWU_F3_MWUF5     (5U)          /*!< Bit position for LLWU_F3_MWUF5. */
01639 #define BM_LLWU_F3_MWUF5     (0x20U)       /*!< Bit mask for LLWU_F3_MWUF5. */
01640 #define BS_LLWU_F3_MWUF5     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF5. */
01641 
01642 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
01643 #define BR_LLWU_F3_MWUF5(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5)))
01644 /*@}*/
01645 
01646 /*!
01647  * @name Register LLWU_F3, field MWUF6[6] (RO)
01648  *
01649  * Indicates that an enabled internal peripheral was a source of exiting a
01650  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01651  * clearing mechanism.
01652  *
01653  * Values:
01654  * - 0 - Module 6 input was not a wakeup source
01655  * - 1 - Module 6 input was a wakeup source
01656  */
01657 /*@{*/
01658 #define BP_LLWU_F3_MWUF6     (6U)          /*!< Bit position for LLWU_F3_MWUF6. */
01659 #define BM_LLWU_F3_MWUF6     (0x40U)       /*!< Bit mask for LLWU_F3_MWUF6. */
01660 #define BS_LLWU_F3_MWUF6     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF6. */
01661 
01662 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
01663 #define BR_LLWU_F3_MWUF6(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6)))
01664 /*@}*/
01665 
01666 /*!
01667  * @name Register LLWU_F3, field MWUF7[7] (RO)
01668  *
01669  * Indicates that an enabled internal peripheral was a source of exiting a
01670  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
01671  * clearing mechanism.
01672  *
01673  * Values:
01674  * - 0 - Module 7 input was not a wakeup source
01675  * - 1 - Module 7 input was a wakeup source
01676  */
01677 /*@{*/
01678 #define BP_LLWU_F3_MWUF7     (7U)          /*!< Bit position for LLWU_F3_MWUF7. */
01679 #define BM_LLWU_F3_MWUF7     (0x80U)       /*!< Bit mask for LLWU_F3_MWUF7. */
01680 #define BS_LLWU_F3_MWUF7     (1U)          /*!< Bit field size in bits for LLWU_F3_MWUF7. */
01681 
01682 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
01683 #define BR_LLWU_F3_MWUF7(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7)))
01684 /*@}*/
01685 
01686 /*******************************************************************************
01687  * HW_LLWU_FILT1 - LLWU Pin Filter 1 register
01688  ******************************************************************************/
01689 
01690 /*!
01691  * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
01692  *
01693  * Reset value: 0x00U
01694  *
01695  * LLWU_FILT1 is a control and status register that is used to enable/disable
01696  * the digital filter 1 features for an external pin. This register is reset on
01697  * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
01698  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
01699  * IntroductionInformation found here describes the registers of the Reset Control
01700  * Module (RCM). The RCM implements many of the reset functions for the chip. See
01701  * the chip's reset chapter for more information. details for more information.
01702  */
01703 typedef union _hw_llwu_filt1
01704 {
01705     uint8_t U;
01706     struct _hw_llwu_filt1_bitfields
01707     {
01708         uint8_t FILTSEL : 4;           /*!< [3:0] Filter Pin Select */
01709         uint8_t RESERVED0 : 1;         /*!< [4]  */
01710         uint8_t FILTE : 2;             /*!< [6:5] Digital Filter On External Pin */
01711         uint8_t FILTF : 1;             /*!< [7] Filter Detect Flag */
01712     } B;
01713 } hw_llwu_filt1_t;
01714 
01715 /*!
01716  * @name Constants and macros for entire LLWU_FILT1 register
01717  */
01718 /*@{*/
01719 #define HW_LLWU_FILT1_ADDR(x)    ((x) + 0x8U)
01720 
01721 #define HW_LLWU_FILT1(x)         (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x))
01722 #define HW_LLWU_FILT1_RD(x)      (ADDRESS_READ(hw_llwu_filt1_t, HW_LLWU_FILT1_ADDR(x)))
01723 #define HW_LLWU_FILT1_WR(x, v)   (ADDRESS_WRITE(hw_llwu_filt1_t, HW_LLWU_FILT1_ADDR(x), v))
01724 #define HW_LLWU_FILT1_SET(x, v)  (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) |  (v)))
01725 #define HW_LLWU_FILT1_CLR(x, v)  (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
01726 #define HW_LLWU_FILT1_TOG(x, v)  (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^  (v)))
01727 /*@}*/
01728 
01729 /*
01730  * Constants & macros for individual LLWU_FILT1 bitfields
01731  */
01732 
01733 /*!
01734  * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
01735  *
01736  * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
01737  *
01738  * Values:
01739  * - 0000 - Select LLWU_P0 for filter
01740  * - 1111 - Select LLWU_P15 for filter
01741  */
01742 /*@{*/
01743 #define BP_LLWU_FILT1_FILTSEL (0U)         /*!< Bit position for LLWU_FILT1_FILTSEL. */
01744 #define BM_LLWU_FILT1_FILTSEL (0x0FU)      /*!< Bit mask for LLWU_FILT1_FILTSEL. */
01745 #define BS_LLWU_FILT1_FILTSEL (4U)         /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */
01746 
01747 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
01748 #define BR_LLWU_FILT1_FILTSEL(x) (UNION_READ(hw_llwu_filt1_t, HW_LLWU_FILT1_ADDR(x), U, B.FILTSEL))
01749 
01750 /*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */
01751 #define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
01752 
01753 /*! @brief Set the FILTSEL field to a new value. */
01754 #define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
01755 /*@}*/
01756 
01757 /*!
01758  * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
01759  *
01760  * Controls the digital filter options for the external pin detect.
01761  *
01762  * Values:
01763  * - 00 - Filter disabled
01764  * - 01 - Filter posedge detect enabled
01765  * - 10 - Filter negedge detect enabled
01766  * - 11 - Filter any edge detect enabled
01767  */
01768 /*@{*/
01769 #define BP_LLWU_FILT1_FILTE  (5U)          /*!< Bit position for LLWU_FILT1_FILTE. */
01770 #define BM_LLWU_FILT1_FILTE  (0x60U)       /*!< Bit mask for LLWU_FILT1_FILTE. */
01771 #define BS_LLWU_FILT1_FILTE  (2U)          /*!< Bit field size in bits for LLWU_FILT1_FILTE. */
01772 
01773 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
01774 #define BR_LLWU_FILT1_FILTE(x) (UNION_READ(hw_llwu_filt1_t, HW_LLWU_FILT1_ADDR(x), U, B.FILTE))
01775 
01776 /*! @brief Format value for bitfield LLWU_FILT1_FILTE. */
01777 #define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
01778 
01779 /*! @brief Set the FILTE field to a new value. */
01780 #define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
01781 /*@}*/
01782 
01783 /*!
01784  * @name Register LLWU_FILT1, field FILTF[7] (W1C)
01785  *
01786  * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
01787  * source of exiting a low-leakage power mode. To clear the flag write a one to
01788  * FILTF.
01789  *
01790  * Values:
01791  * - 0 - Pin Filter 1 was not a wakeup source
01792  * - 1 - Pin Filter 1 was a wakeup source
01793  */
01794 /*@{*/
01795 #define BP_LLWU_FILT1_FILTF  (7U)          /*!< Bit position for LLWU_FILT1_FILTF. */
01796 #define BM_LLWU_FILT1_FILTF  (0x80U)       /*!< Bit mask for LLWU_FILT1_FILTF. */
01797 #define BS_LLWU_FILT1_FILTF  (1U)          /*!< Bit field size in bits for LLWU_FILT1_FILTF. */
01798 
01799 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
01800 #define BR_LLWU_FILT1_FILTF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF)))
01801 
01802 /*! @brief Format value for bitfield LLWU_FILT1_FILTF. */
01803 #define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
01804 
01805 /*! @brief Set the FILTF field to a new value. */
01806 #define BW_LLWU_FILT1_FILTF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF), v))
01807 /*@}*/
01808 
01809 /*******************************************************************************
01810  * HW_LLWU_FILT2 - LLWU Pin Filter 2 register
01811  ******************************************************************************/
01812 
01813 /*!
01814  * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
01815  *
01816  * Reset value: 0x00U
01817  *
01818  * LLWU_FILT2 is a control and status register that is used to enable/disable
01819  * the digital filter 2 features for an external pin. This register is reset on
01820  * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
01821  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
01822  * IntroductionInformation found here describes the registers of the Reset Control
01823  * Module (RCM). The RCM implements many of the reset functions for the chip. See
01824  * the chip's reset chapter for more information. details for more information.
01825  */
01826 typedef union _hw_llwu_filt2
01827 {
01828     uint8_t U;
01829     struct _hw_llwu_filt2_bitfields
01830     {
01831         uint8_t FILTSEL : 4;           /*!< [3:0] Filter Pin Select */
01832         uint8_t RESERVED0 : 1;         /*!< [4]  */
01833         uint8_t FILTE : 2;             /*!< [6:5] Digital Filter On External Pin */
01834         uint8_t FILTF : 1;             /*!< [7] Filter Detect Flag */
01835     } B;
01836 } hw_llwu_filt2_t;
01837 
01838 /*!
01839  * @name Constants and macros for entire LLWU_FILT2 register
01840  */
01841 /*@{*/
01842 #define HW_LLWU_FILT2_ADDR(x)    ((x) + 0x9U)
01843 
01844 #define HW_LLWU_FILT2(x)         (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x))
01845 #define HW_LLWU_FILT2_RD(x)      (ADDRESS_READ(hw_llwu_filt2_t, HW_LLWU_FILT2_ADDR(x)))
01846 #define HW_LLWU_FILT2_WR(x, v)   (ADDRESS_WRITE(hw_llwu_filt2_t, HW_LLWU_FILT2_ADDR(x), v))
01847 #define HW_LLWU_FILT2_SET(x, v)  (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) |  (v)))
01848 #define HW_LLWU_FILT2_CLR(x, v)  (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
01849 #define HW_LLWU_FILT2_TOG(x, v)  (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^  (v)))
01850 /*@}*/
01851 
01852 /*
01853  * Constants & macros for individual LLWU_FILT2 bitfields
01854  */
01855 
01856 /*!
01857  * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
01858  *
01859  * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
01860  *
01861  * Values:
01862  * - 0000 - Select LLWU_P0 for filter
01863  * - 1111 - Select LLWU_P15 for filter
01864  */
01865 /*@{*/
01866 #define BP_LLWU_FILT2_FILTSEL (0U)         /*!< Bit position for LLWU_FILT2_FILTSEL. */
01867 #define BM_LLWU_FILT2_FILTSEL (0x0FU)      /*!< Bit mask for LLWU_FILT2_FILTSEL. */
01868 #define BS_LLWU_FILT2_FILTSEL (4U)         /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */
01869 
01870 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
01871 #define BR_LLWU_FILT2_FILTSEL(x) (UNION_READ(hw_llwu_filt2_t, HW_LLWU_FILT2_ADDR(x), U, B.FILTSEL))
01872 
01873 /*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */
01874 #define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
01875 
01876 /*! @brief Set the FILTSEL field to a new value. */
01877 #define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
01878 /*@}*/
01879 
01880 /*!
01881  * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
01882  *
01883  * Controls the digital filter options for the external pin detect.
01884  *
01885  * Values:
01886  * - 00 - Filter disabled
01887  * - 01 - Filter posedge detect enabled
01888  * - 10 - Filter negedge detect enabled
01889  * - 11 - Filter any edge detect enabled
01890  */
01891 /*@{*/
01892 #define BP_LLWU_FILT2_FILTE  (5U)          /*!< Bit position for LLWU_FILT2_FILTE. */
01893 #define BM_LLWU_FILT2_FILTE  (0x60U)       /*!< Bit mask for LLWU_FILT2_FILTE. */
01894 #define BS_LLWU_FILT2_FILTE  (2U)          /*!< Bit field size in bits for LLWU_FILT2_FILTE. */
01895 
01896 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
01897 #define BR_LLWU_FILT2_FILTE(x) (UNION_READ(hw_llwu_filt2_t, HW_LLWU_FILT2_ADDR(x), U, B.FILTE))
01898 
01899 /*! @brief Format value for bitfield LLWU_FILT2_FILTE. */
01900 #define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
01901 
01902 /*! @brief Set the FILTE field to a new value. */
01903 #define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
01904 /*@}*/
01905 
01906 /*!
01907  * @name Register LLWU_FILT2, field FILTF[7] (W1C)
01908  *
01909  * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
01910  * source of exiting a low-leakage power mode. To clear the flag write a one to
01911  * FILTF.
01912  *
01913  * Values:
01914  * - 0 - Pin Filter 2 was not a wakeup source
01915  * - 1 - Pin Filter 2 was a wakeup source
01916  */
01917 /*@{*/
01918 #define BP_LLWU_FILT2_FILTF  (7U)          /*!< Bit position for LLWU_FILT2_FILTF. */
01919 #define BM_LLWU_FILT2_FILTF  (0x80U)       /*!< Bit mask for LLWU_FILT2_FILTF. */
01920 #define BS_LLWU_FILT2_FILTF  (1U)          /*!< Bit field size in bits for LLWU_FILT2_FILTF. */
01921 
01922 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
01923 #define BR_LLWU_FILT2_FILTF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF)))
01924 
01925 /*! @brief Format value for bitfield LLWU_FILT2_FILTF. */
01926 #define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
01927 
01928 /*! @brief Set the FILTF field to a new value. */
01929 #define BW_LLWU_FILT2_FILTF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF), v))
01930 /*@}*/
01931 
01932 /*******************************************************************************
01933  * HW_LLWU_RST - LLWU Reset Enable register
01934  ******************************************************************************/
01935 
01936 /*!
01937  * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
01938  *
01939  * Reset value: 0x02U
01940  *
01941  * LLWU_RST is a control register that is used to enable/disable the digital
01942  * filter for the external pin detect and RESET pin. This register is reset on Chip
01943  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
01944  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
01945  * IntroductionInformation found here describes the registers of the Reset Control
01946  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
01947  * chip's reset chapter for more information. details for more information.
01948  */
01949 typedef union _hw_llwu_rst
01950 {
01951     uint8_t U;
01952     struct _hw_llwu_rst_bitfields
01953     {
01954         uint8_t RSTFILT : 1;           /*!< [0] Digital Filter On RESET Pin */
01955         uint8_t LLRSTE : 1;            /*!< [1] Low-Leakage Mode RESET Enable */
01956         uint8_t RESERVED0 : 6;         /*!< [7:2]  */
01957     } B;
01958 } hw_llwu_rst_t;
01959 
01960 /*!
01961  * @name Constants and macros for entire LLWU_RST register
01962  */
01963 /*@{*/
01964 #define HW_LLWU_RST_ADDR(x)      ((x) + 0xAU)
01965 
01966 #define HW_LLWU_RST(x)           (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR(x))
01967 #define HW_LLWU_RST_RD(x)        (ADDRESS_READ(hw_llwu_rst_t, HW_LLWU_RST_ADDR(x)))
01968 #define HW_LLWU_RST_WR(x, v)     (ADDRESS_WRITE(hw_llwu_rst_t, HW_LLWU_RST_ADDR(x), v))
01969 #define HW_LLWU_RST_SET(x, v)    (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) |  (v)))
01970 #define HW_LLWU_RST_CLR(x, v)    (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) & ~(v)))
01971 #define HW_LLWU_RST_TOG(x, v)    (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) ^  (v)))
01972 /*@}*/
01973 
01974 /*
01975  * Constants & macros for individual LLWU_RST bitfields
01976  */
01977 
01978 /*!
01979  * @name Register LLWU_RST, field RSTFILT[0] (RW)
01980  *
01981  * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
01982  * VLLS1 modes.
01983  *
01984  * Values:
01985  * - 0 - Filter not enabled
01986  * - 1 - Filter enabled
01987  */
01988 /*@{*/
01989 #define BP_LLWU_RST_RSTFILT  (0U)          /*!< Bit position for LLWU_RST_RSTFILT. */
01990 #define BM_LLWU_RST_RSTFILT  (0x01U)       /*!< Bit mask for LLWU_RST_RSTFILT. */
01991 #define BS_LLWU_RST_RSTFILT  (1U)          /*!< Bit field size in bits for LLWU_RST_RSTFILT. */
01992 
01993 /*! @brief Read current value of the LLWU_RST_RSTFILT field. */
01994 #define BR_LLWU_RST_RSTFILT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT)))
01995 
01996 /*! @brief Format value for bitfield LLWU_RST_RSTFILT. */
01997 #define BF_LLWU_RST_RSTFILT(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_RSTFILT) & BM_LLWU_RST_RSTFILT)
01998 
01999 /*! @brief Set the RSTFILT field to a new value. */
02000 #define BW_LLWU_RST_RSTFILT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT), v))
02001 /*@}*/
02002 
02003 /*!
02004  * @name Register LLWU_RST, field LLRSTE[1] (RW)
02005  *
02006  * This bit must be set to allow the device to be reset while in a low-leakage
02007  * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
02008  * also be enabled in the explicit port mux control.
02009  *
02010  * Values:
02011  * - 0 - RESET pin not enabled as a leakage mode exit source
02012  * - 1 - RESET pin enabled as a low leakage mode exit source
02013  */
02014 /*@{*/
02015 #define BP_LLWU_RST_LLRSTE   (1U)          /*!< Bit position for LLWU_RST_LLRSTE. */
02016 #define BM_LLWU_RST_LLRSTE   (0x02U)       /*!< Bit mask for LLWU_RST_LLRSTE. */
02017 #define BS_LLWU_RST_LLRSTE   (1U)          /*!< Bit field size in bits for LLWU_RST_LLRSTE. */
02018 
02019 /*! @brief Read current value of the LLWU_RST_LLRSTE field. */
02020 #define BR_LLWU_RST_LLRSTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE)))
02021 
02022 /*! @brief Format value for bitfield LLWU_RST_LLRSTE. */
02023 #define BF_LLWU_RST_LLRSTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_LLRSTE) & BM_LLWU_RST_LLRSTE)
02024 
02025 /*! @brief Set the LLRSTE field to a new value. */
02026 #define BW_LLWU_RST_LLRSTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE), v))
02027 /*@}*/
02028 
02029 /*******************************************************************************
02030  * hw_llwu_t - module struct
02031  ******************************************************************************/
02032 /*!
02033  * @brief All LLWU module registers.
02034  */
02035 #pragma pack(1)
02036 typedef struct _hw_llwu
02037 {
02038     __IO hw_llwu_pe1_t PE1 ;                /*!< [0x0] LLWU Pin Enable 1 register */
02039     __IO hw_llwu_pe2_t PE2 ;                /*!< [0x1] LLWU Pin Enable 2 register */
02040     __IO hw_llwu_pe3_t PE3 ;                /*!< [0x2] LLWU Pin Enable 3 register */
02041     __IO hw_llwu_pe4_t PE4 ;                /*!< [0x3] LLWU Pin Enable 4 register */
02042     __IO hw_llwu_me_t ME ;                  /*!< [0x4] LLWU Module Enable register */
02043     __IO hw_llwu_f1_t F1 ;                  /*!< [0x5] LLWU Flag 1 register */
02044     __IO hw_llwu_f2_t F2 ;                  /*!< [0x6] LLWU Flag 2 register */
02045     __I hw_llwu_f3_t F3 ;                   /*!< [0x7] LLWU Flag 3 register */
02046     __IO hw_llwu_filt1_t FILT1 ;            /*!< [0x8] LLWU Pin Filter 1 register */
02047     __IO hw_llwu_filt2_t FILT2 ;            /*!< [0x9] LLWU Pin Filter 2 register */
02048     __IO hw_llwu_rst_t RST ;                /*!< [0xA] LLWU Reset Enable register */
02049 } hw_llwu_t;
02050 #pragma pack()
02051 
02052 /*! @brief Macro to access all LLWU registers. */
02053 /*! @param x LLWU module instance base address. */
02054 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
02055  *     use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
02056 #define HW_LLWU(x)     (*(hw_llwu_t *)(x))
02057 
02058 #endif /* __HW_LLWU_REGISTERS_H__ */
02059 /* EOF */