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_hw_i2s_mdr Union Reference
HW_I2S_MDR - SAI MCLK Divide Register (RW) More...
#include <MK64F12_i2s.h>
Detailed Description
HW_I2S_MDR - SAI MCLK Divide Register (RW)
Reset value: 0x00000000U
The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the MDR can be changed when the MCLK divider clock is enabled, additional writes to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK divided clock is disabled do not set MCR[DUF].
Definition at line 2985 of file MK64F12_i2s.h.
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