MK64F12_i2s.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_I2S_REGISTERS_H__
00088 #define __HW_I2S_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 I2S
00095  *
00096  * Inter-IC Sound / Synchronous Audio Interface
00097  *
00098  * Registers defined in this header file:
00099  * - HW_I2S_TCSR - SAI Transmit Control Register
00100  * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
00101  * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
00102  * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
00103  * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
00104  * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
00105  * - HW_I2S_TDRn - SAI Transmit Data Register
00106  * - HW_I2S_TFRn - SAI Transmit FIFO Register
00107  * - HW_I2S_TMR - SAI Transmit Mask Register
00108  * - HW_I2S_RCSR - SAI Receive Control Register
00109  * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
00110  * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
00111  * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
00112  * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
00113  * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
00114  * - HW_I2S_RDRn - SAI Receive Data Register
00115  * - HW_I2S_RFRn - SAI Receive FIFO Register
00116  * - HW_I2S_RMR - SAI Receive Mask Register
00117  * - HW_I2S_MCR - SAI MCLK Control Register
00118  * - HW_I2S_MDR - SAI MCLK Divide Register
00119  *
00120  * - hw_i2s_t - Struct containing all module registers.
00121  */
00122 
00123 #define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
00124 
00125 /*******************************************************************************
00126  * HW_I2S_TCSR - SAI Transmit Control Register
00127  ******************************************************************************/
00128 
00129 /*!
00130  * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
00131  *
00132  * Reset value: 0x00000000U
00133  */
00134 typedef union _hw_i2s_tcsr
00135 {
00136     uint32_t U;
00137     struct _hw_i2s_tcsr_bitfields
00138     {
00139         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
00140         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
00141         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
00142         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
00143         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
00144         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
00145         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
00146         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
00147         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
00148         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
00149         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
00150         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
00151         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
00152         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
00153         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
00154         uint32_t SR : 1;               /*!< [24] Software Reset */
00155         uint32_t FR : 1;               /*!< [25] FIFO Reset */
00156         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
00157         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
00158         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
00159         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
00160         uint32_t TE : 1;               /*!< [31] Transmitter Enable */
00161     } B;
00162 } hw_i2s_tcsr_t;
00163 
00164 /*!
00165  * @name Constants and macros for entire I2S_TCSR register
00166  */
00167 /*@{*/
00168 #define HW_I2S_TCSR_ADDR(x)      ((x) + 0x0U)
00169 
00170 #define HW_I2S_TCSR(x)           (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
00171 #define HW_I2S_TCSR_RD(x)        (ADDRESS_READ(hw_i2s_tcsr_t, HW_I2S_TCSR_ADDR(x)))
00172 #define HW_I2S_TCSR_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcsr_t, HW_I2S_TCSR_ADDR(x), v))
00173 #define HW_I2S_TCSR_SET(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) |  (v)))
00174 #define HW_I2S_TCSR_CLR(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
00175 #define HW_I2S_TCSR_TOG(x, v)    (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^  (v)))
00176 /*@}*/
00177 
00178 /*
00179  * Constants & macros for individual I2S_TCSR bitfields
00180  */
00181 
00182 /*!
00183  * @name Register I2S_TCSR, field FRDE[0] (RW)
00184  *
00185  * Enables/disables DMA requests.
00186  *
00187  * Values:
00188  * - 0 - Disables the DMA request.
00189  * - 1 - Enables the DMA request.
00190  */
00191 /*@{*/
00192 #define BP_I2S_TCSR_FRDE     (0U)          /*!< Bit position for I2S_TCSR_FRDE. */
00193 #define BM_I2S_TCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */
00194 #define BS_I2S_TCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRDE. */
00195 
00196 /*! @brief Read current value of the I2S_TCSR_FRDE field. */
00197 #define BR_I2S_TCSR_FRDE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE)))
00198 
00199 /*! @brief Format value for bitfield I2S_TCSR_FRDE. */
00200 #define BF_I2S_TCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
00201 
00202 /*! @brief Set the FRDE field to a new value. */
00203 #define BW_I2S_TCSR_FRDE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE), v))
00204 /*@}*/
00205 
00206 /*!
00207  * @name Register I2S_TCSR, field FWDE[1] (RW)
00208  *
00209  * Enables/disables DMA requests.
00210  *
00211  * Values:
00212  * - 0 - Disables the DMA request.
00213  * - 1 - Enables the DMA request.
00214  */
00215 /*@{*/
00216 #define BP_I2S_TCSR_FWDE     (1U)          /*!< Bit position for I2S_TCSR_FWDE. */
00217 #define BM_I2S_TCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */
00218 #define BS_I2S_TCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWDE. */
00219 
00220 /*! @brief Read current value of the I2S_TCSR_FWDE field. */
00221 #define BR_I2S_TCSR_FWDE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE)))
00222 
00223 /*! @brief Format value for bitfield I2S_TCSR_FWDE. */
00224 #define BF_I2S_TCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
00225 
00226 /*! @brief Set the FWDE field to a new value. */
00227 #define BW_I2S_TCSR_FWDE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE), v))
00228 /*@}*/
00229 
00230 /*!
00231  * @name Register I2S_TCSR, field FRIE[8] (RW)
00232  *
00233  * Enables/disables FIFO request interrupts.
00234  *
00235  * Values:
00236  * - 0 - Disables the interrupt.
00237  * - 1 - Enables the interrupt.
00238  */
00239 /*@{*/
00240 #define BP_I2S_TCSR_FRIE     (8U)          /*!< Bit position for I2S_TCSR_FRIE. */
00241 #define BM_I2S_TCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */
00242 #define BS_I2S_TCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FRIE. */
00243 
00244 /*! @brief Read current value of the I2S_TCSR_FRIE field. */
00245 #define BR_I2S_TCSR_FRIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE)))
00246 
00247 /*! @brief Format value for bitfield I2S_TCSR_FRIE. */
00248 #define BF_I2S_TCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
00249 
00250 /*! @brief Set the FRIE field to a new value. */
00251 #define BW_I2S_TCSR_FRIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE), v))
00252 /*@}*/
00253 
00254 /*!
00255  * @name Register I2S_TCSR, field FWIE[9] (RW)
00256  *
00257  * Enables/disables FIFO warning interrupts.
00258  *
00259  * Values:
00260  * - 0 - Disables the interrupt.
00261  * - 1 - Enables the interrupt.
00262  */
00263 /*@{*/
00264 #define BP_I2S_TCSR_FWIE     (9U)          /*!< Bit position for I2S_TCSR_FWIE. */
00265 #define BM_I2S_TCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */
00266 #define BS_I2S_TCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FWIE. */
00267 
00268 /*! @brief Read current value of the I2S_TCSR_FWIE field. */
00269 #define BR_I2S_TCSR_FWIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE)))
00270 
00271 /*! @brief Format value for bitfield I2S_TCSR_FWIE. */
00272 #define BF_I2S_TCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
00273 
00274 /*! @brief Set the FWIE field to a new value. */
00275 #define BW_I2S_TCSR_FWIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE), v))
00276 /*@}*/
00277 
00278 /*!
00279  * @name Register I2S_TCSR, field FEIE[10] (RW)
00280  *
00281  * Enables/disables FIFO error interrupts.
00282  *
00283  * Values:
00284  * - 0 - Disables the interrupt.
00285  * - 1 - Enables the interrupt.
00286  */
00287 /*@{*/
00288 #define BP_I2S_TCSR_FEIE     (10U)         /*!< Bit position for I2S_TCSR_FEIE. */
00289 #define BM_I2S_TCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */
00290 #define BS_I2S_TCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_FEIE. */
00291 
00292 /*! @brief Read current value of the I2S_TCSR_FEIE field. */
00293 #define BR_I2S_TCSR_FEIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE)))
00294 
00295 /*! @brief Format value for bitfield I2S_TCSR_FEIE. */
00296 #define BF_I2S_TCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
00297 
00298 /*! @brief Set the FEIE field to a new value. */
00299 #define BW_I2S_TCSR_FEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE), v))
00300 /*@}*/
00301 
00302 /*!
00303  * @name Register I2S_TCSR, field SEIE[11] (RW)
00304  *
00305  * Enables/disables sync error interrupts.
00306  *
00307  * Values:
00308  * - 0 - Disables interrupt.
00309  * - 1 - Enables interrupt.
00310  */
00311 /*@{*/
00312 #define BP_I2S_TCSR_SEIE     (11U)         /*!< Bit position for I2S_TCSR_SEIE. */
00313 #define BM_I2S_TCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */
00314 #define BS_I2S_TCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_SEIE. */
00315 
00316 /*! @brief Read current value of the I2S_TCSR_SEIE field. */
00317 #define BR_I2S_TCSR_SEIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE)))
00318 
00319 /*! @brief Format value for bitfield I2S_TCSR_SEIE. */
00320 #define BF_I2S_TCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
00321 
00322 /*! @brief Set the SEIE field to a new value. */
00323 #define BW_I2S_TCSR_SEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE), v))
00324 /*@}*/
00325 
00326 /*!
00327  * @name Register I2S_TCSR, field WSIE[12] (RW)
00328  *
00329  * Enables/disables word start interrupts.
00330  *
00331  * Values:
00332  * - 0 - Disables interrupt.
00333  * - 1 - Enables interrupt.
00334  */
00335 /*@{*/
00336 #define BP_I2S_TCSR_WSIE     (12U)         /*!< Bit position for I2S_TCSR_WSIE. */
00337 #define BM_I2S_TCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */
00338 #define BS_I2S_TCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_TCSR_WSIE. */
00339 
00340 /*! @brief Read current value of the I2S_TCSR_WSIE field. */
00341 #define BR_I2S_TCSR_WSIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE)))
00342 
00343 /*! @brief Format value for bitfield I2S_TCSR_WSIE. */
00344 #define BF_I2S_TCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
00345 
00346 /*! @brief Set the WSIE field to a new value. */
00347 #define BW_I2S_TCSR_WSIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE), v))
00348 /*@}*/
00349 
00350 /*!
00351  * @name Register I2S_TCSR, field FRF[16] (RO)
00352  *
00353  * Indicates that the number of words in an enabled transmit channel FIFO is
00354  * less than or equal to the transmit FIFO watermark.
00355  *
00356  * Values:
00357  * - 0 - Transmit FIFO watermark has not been reached.
00358  * - 1 - Transmit FIFO watermark has been reached.
00359  */
00360 /*@{*/
00361 #define BP_I2S_TCSR_FRF      (16U)         /*!< Bit position for I2S_TCSR_FRF. */
00362 #define BM_I2S_TCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */
00363 #define BS_I2S_TCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FRF. */
00364 
00365 /*! @brief Read current value of the I2S_TCSR_FRF field. */
00366 #define BR_I2S_TCSR_FRF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF)))
00367 /*@}*/
00368 
00369 /*!
00370  * @name Register I2S_TCSR, field FWF[17] (RO)
00371  *
00372  * Indicates that an enabled transmit FIFO is empty.
00373  *
00374  * Values:
00375  * - 0 - No enabled transmit FIFO is empty.
00376  * - 1 - Enabled transmit FIFO is empty.
00377  */
00378 /*@{*/
00379 #define BP_I2S_TCSR_FWF      (17U)         /*!< Bit position for I2S_TCSR_FWF. */
00380 #define BM_I2S_TCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */
00381 #define BS_I2S_TCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FWF. */
00382 
00383 /*! @brief Read current value of the I2S_TCSR_FWF field. */
00384 #define BR_I2S_TCSR_FWF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF)))
00385 /*@}*/
00386 
00387 /*!
00388  * @name Register I2S_TCSR, field FEF[18] (W1C)
00389  *
00390  * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
00391  * field to clear this flag.
00392  *
00393  * Values:
00394  * - 0 - Transmit underrun not detected.
00395  * - 1 - Transmit underrun detected.
00396  */
00397 /*@{*/
00398 #define BP_I2S_TCSR_FEF      (18U)         /*!< Bit position for I2S_TCSR_FEF. */
00399 #define BM_I2S_TCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */
00400 #define BS_I2S_TCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_FEF. */
00401 
00402 /*! @brief Read current value of the I2S_TCSR_FEF field. */
00403 #define BR_I2S_TCSR_FEF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF)))
00404 
00405 /*! @brief Format value for bitfield I2S_TCSR_FEF. */
00406 #define BF_I2S_TCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
00407 
00408 /*! @brief Set the FEF field to a new value. */
00409 #define BW_I2S_TCSR_FEF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF), v))
00410 /*@}*/
00411 
00412 /*!
00413  * @name Register I2S_TCSR, field SEF[19] (W1C)
00414  *
00415  * Indicates that an error in the externally-generated frame sync has been
00416  * detected. Write a logic 1 to this field to clear this flag.
00417  *
00418  * Values:
00419  * - 0 - Sync error not detected.
00420  * - 1 - Frame sync error detected.
00421  */
00422 /*@{*/
00423 #define BP_I2S_TCSR_SEF      (19U)         /*!< Bit position for I2S_TCSR_SEF. */
00424 #define BM_I2S_TCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */
00425 #define BS_I2S_TCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_TCSR_SEF. */
00426 
00427 /*! @brief Read current value of the I2S_TCSR_SEF field. */
00428 #define BR_I2S_TCSR_SEF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF)))
00429 
00430 /*! @brief Format value for bitfield I2S_TCSR_SEF. */
00431 #define BF_I2S_TCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
00432 
00433 /*! @brief Set the SEF field to a new value. */
00434 #define BW_I2S_TCSR_SEF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF), v))
00435 /*@}*/
00436 
00437 /*!
00438  * @name Register I2S_TCSR, field WSF[20] (W1C)
00439  *
00440  * Indicates that the start of the configured word has been detected. Write a
00441  * logic 1 to this field to clear this flag.
00442  *
00443  * Values:
00444  * - 0 - Start of word not detected.
00445  * - 1 - Start of word detected.
00446  */
00447 /*@{*/
00448 #define BP_I2S_TCSR_WSF      (20U)         /*!< Bit position for I2S_TCSR_WSF. */
00449 #define BM_I2S_TCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */
00450 #define BS_I2S_TCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_TCSR_WSF. */
00451 
00452 /*! @brief Read current value of the I2S_TCSR_WSF field. */
00453 #define BR_I2S_TCSR_WSF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF)))
00454 
00455 /*! @brief Format value for bitfield I2S_TCSR_WSF. */
00456 #define BF_I2S_TCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
00457 
00458 /*! @brief Set the WSF field to a new value. */
00459 #define BW_I2S_TCSR_WSF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF), v))
00460 /*@}*/
00461 
00462 /*!
00463  * @name Register I2S_TCSR, field SR[24] (RW)
00464  *
00465  * When set, resets the internal transmitter logic including the FIFO pointers.
00466  * Software-visible registers are not affected, except for the status registers.
00467  *
00468  * Values:
00469  * - 0 - No effect.
00470  * - 1 - Software reset.
00471  */
00472 /*@{*/
00473 #define BP_I2S_TCSR_SR       (24U)         /*!< Bit position for I2S_TCSR_SR. */
00474 #define BM_I2S_TCSR_SR       (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */
00475 #define BS_I2S_TCSR_SR       (1U)          /*!< Bit field size in bits for I2S_TCSR_SR. */
00476 
00477 /*! @brief Read current value of the I2S_TCSR_SR field. */
00478 #define BR_I2S_TCSR_SR(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR)))
00479 
00480 /*! @brief Format value for bitfield I2S_TCSR_SR. */
00481 #define BF_I2S_TCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
00482 
00483 /*! @brief Set the SR field to a new value. */
00484 #define BW_I2S_TCSR_SR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR), v))
00485 /*@}*/
00486 
00487 /*!
00488  * @name Register I2S_TCSR, field FR[25] (WORZ)
00489  *
00490  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
00491  * pointers should only be reset when the transmitter is disabled or the FIFO error
00492  * flag is set.
00493  *
00494  * Values:
00495  * - 0 - No effect.
00496  * - 1 - FIFO reset.
00497  */
00498 /*@{*/
00499 #define BP_I2S_TCSR_FR       (25U)         /*!< Bit position for I2S_TCSR_FR. */
00500 #define BM_I2S_TCSR_FR       (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */
00501 #define BS_I2S_TCSR_FR       (1U)          /*!< Bit field size in bits for I2S_TCSR_FR. */
00502 
00503 /*! @brief Format value for bitfield I2S_TCSR_FR. */
00504 #define BF_I2S_TCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
00505 
00506 /*! @brief Set the FR field to a new value. */
00507 #define BW_I2S_TCSR_FR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR), v))
00508 /*@}*/
00509 
00510 /*!
00511  * @name Register I2S_TCSR, field BCE[28] (RW)
00512  *
00513  * Enables the transmit bit clock, separately from the TE. This field is
00514  * automatically set whenever TE is set. When software clears this field, the transmit
00515  * bit clock remains enabled, and this bit remains set, until the end of the
00516  * current frame.
00517  *
00518  * Values:
00519  * - 0 - Transmit bit clock is disabled.
00520  * - 1 - Transmit bit clock is enabled.
00521  */
00522 /*@{*/
00523 #define BP_I2S_TCSR_BCE      (28U)         /*!< Bit position for I2S_TCSR_BCE. */
00524 #define BM_I2S_TCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */
00525 #define BS_I2S_TCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_TCSR_BCE. */
00526 
00527 /*! @brief Read current value of the I2S_TCSR_BCE field. */
00528 #define BR_I2S_TCSR_BCE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE)))
00529 
00530 /*! @brief Format value for bitfield I2S_TCSR_BCE. */
00531 #define BF_I2S_TCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
00532 
00533 /*! @brief Set the BCE field to a new value. */
00534 #define BW_I2S_TCSR_BCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE), v))
00535 /*@}*/
00536 
00537 /*!
00538  * @name Register I2S_TCSR, field DBGE[29] (RW)
00539  *
00540  * Enables/disables transmitter operation in Debug mode. The transmit bit clock
00541  * is not affected by debug mode.
00542  *
00543  * Values:
00544  * - 0 - Transmitter is disabled in Debug mode, after completing the current
00545  *     frame.
00546  * - 1 - Transmitter is enabled in Debug mode.
00547  */
00548 /*@{*/
00549 #define BP_I2S_TCSR_DBGE     (29U)         /*!< Bit position for I2S_TCSR_DBGE. */
00550 #define BM_I2S_TCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */
00551 #define BS_I2S_TCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_TCSR_DBGE. */
00552 
00553 /*! @brief Read current value of the I2S_TCSR_DBGE field. */
00554 #define BR_I2S_TCSR_DBGE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE)))
00555 
00556 /*! @brief Format value for bitfield I2S_TCSR_DBGE. */
00557 #define BF_I2S_TCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
00558 
00559 /*! @brief Set the DBGE field to a new value. */
00560 #define BW_I2S_TCSR_DBGE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE), v))
00561 /*@}*/
00562 
00563 /*!
00564  * @name Register I2S_TCSR, field STOPE[30] (RW)
00565  *
00566  * Configures transmitter operation in Stop mode. This field is ignored and the
00567  * transmitter is disabled in all low-leakage stop modes.
00568  *
00569  * Values:
00570  * - 0 - Transmitter disabled in Stop mode.
00571  * - 1 - Transmitter enabled in Stop mode.
00572  */
00573 /*@{*/
00574 #define BP_I2S_TCSR_STOPE    (30U)         /*!< Bit position for I2S_TCSR_STOPE. */
00575 #define BM_I2S_TCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */
00576 #define BS_I2S_TCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_TCSR_STOPE. */
00577 
00578 /*! @brief Read current value of the I2S_TCSR_STOPE field. */
00579 #define BR_I2S_TCSR_STOPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE)))
00580 
00581 /*! @brief Format value for bitfield I2S_TCSR_STOPE. */
00582 #define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
00583 
00584 /*! @brief Set the STOPE field to a new value. */
00585 #define BW_I2S_TCSR_STOPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE), v))
00586 /*@}*/
00587 
00588 /*!
00589  * @name Register I2S_TCSR, field TE[31] (RW)
00590  *
00591  * Enables/disables the transmitter. When software clears this field, the
00592  * transmitter remains enabled, and this bit remains set, until the end of the current
00593  * frame.
00594  *
00595  * Values:
00596  * - 0 - Transmitter is disabled.
00597  * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
00598  *     yet reached end of frame.
00599  */
00600 /*@{*/
00601 #define BP_I2S_TCSR_TE       (31U)         /*!< Bit position for I2S_TCSR_TE. */
00602 #define BM_I2S_TCSR_TE       (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */
00603 #define BS_I2S_TCSR_TE       (1U)          /*!< Bit field size in bits for I2S_TCSR_TE. */
00604 
00605 /*! @brief Read current value of the I2S_TCSR_TE field. */
00606 #define BR_I2S_TCSR_TE(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE)))
00607 
00608 /*! @brief Format value for bitfield I2S_TCSR_TE. */
00609 #define BF_I2S_TCSR_TE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
00610 
00611 /*! @brief Set the TE field to a new value. */
00612 #define BW_I2S_TCSR_TE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE), v))
00613 /*@}*/
00614 
00615 /*******************************************************************************
00616  * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
00617  ******************************************************************************/
00618 
00619 /*!
00620  * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
00621  *
00622  * Reset value: 0x00000000U
00623  */
00624 typedef union _hw_i2s_tcr1
00625 {
00626     uint32_t U;
00627     struct _hw_i2s_tcr1_bitfields
00628     {
00629         uint32_t TFW : 3;              /*!< [2:0] Transmit FIFO Watermark */
00630         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00631     } B;
00632 } hw_i2s_tcr1_t;
00633 
00634 /*!
00635  * @name Constants and macros for entire I2S_TCR1 register
00636  */
00637 /*@{*/
00638 #define HW_I2S_TCR1_ADDR(x)      ((x) + 0x4U)
00639 
00640 #define HW_I2S_TCR1(x)           (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
00641 #define HW_I2S_TCR1_RD(x)        (ADDRESS_READ(hw_i2s_tcr1_t, HW_I2S_TCR1_ADDR(x)))
00642 #define HW_I2S_TCR1_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcr1_t, HW_I2S_TCR1_ADDR(x), v))
00643 #define HW_I2S_TCR1_SET(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) |  (v)))
00644 #define HW_I2S_TCR1_CLR(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
00645 #define HW_I2S_TCR1_TOG(x, v)    (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^  (v)))
00646 /*@}*/
00647 
00648 /*
00649  * Constants & macros for individual I2S_TCR1 bitfields
00650  */
00651 
00652 /*!
00653  * @name Register I2S_TCR1, field TFW[2:0] (RW)
00654  *
00655  * Configures the watermark level for all enabled transmit channels.
00656  */
00657 /*@{*/
00658 #define BP_I2S_TCR1_TFW      (0U)          /*!< Bit position for I2S_TCR1_TFW. */
00659 #define BM_I2S_TCR1_TFW      (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */
00660 #define BS_I2S_TCR1_TFW      (3U)          /*!< Bit field size in bits for I2S_TCR1_TFW. */
00661 
00662 /*! @brief Read current value of the I2S_TCR1_TFW field. */
00663 #define BR_I2S_TCR1_TFW(x)   (UNION_READ(hw_i2s_tcr1_t, HW_I2S_TCR1_ADDR(x), U, B.TFW))
00664 
00665 /*! @brief Format value for bitfield I2S_TCR1_TFW. */
00666 #define BF_I2S_TCR1_TFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
00667 
00668 /*! @brief Set the TFW field to a new value. */
00669 #define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
00670 /*@}*/
00671 
00672 /*******************************************************************************
00673  * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
00674  ******************************************************************************/
00675 
00676 /*!
00677  * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
00678  *
00679  * Reset value: 0x00000000U
00680  *
00681  * This register must not be altered when TCSR[TE] is set.
00682  */
00683 typedef union _hw_i2s_tcr2
00684 {
00685     uint32_t U;
00686     struct _hw_i2s_tcr2_bitfields
00687     {
00688         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
00689         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
00690         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
00691         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
00692         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
00693         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
00694         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
00695         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
00696     } B;
00697 } hw_i2s_tcr2_t;
00698 
00699 /*!
00700  * @name Constants and macros for entire I2S_TCR2 register
00701  */
00702 /*@{*/
00703 #define HW_I2S_TCR2_ADDR(x)      ((x) + 0x8U)
00704 
00705 #define HW_I2S_TCR2(x)           (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
00706 #define HW_I2S_TCR2_RD(x)        (ADDRESS_READ(hw_i2s_tcr2_t, HW_I2S_TCR2_ADDR(x)))
00707 #define HW_I2S_TCR2_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcr2_t, HW_I2S_TCR2_ADDR(x), v))
00708 #define HW_I2S_TCR2_SET(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) |  (v)))
00709 #define HW_I2S_TCR2_CLR(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
00710 #define HW_I2S_TCR2_TOG(x, v)    (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^  (v)))
00711 /*@}*/
00712 
00713 /*
00714  * Constants & macros for individual I2S_TCR2 bitfields
00715  */
00716 
00717 /*!
00718  * @name Register I2S_TCR2, field DIV[7:0] (RW)
00719  *
00720  * Divides down the audio master clock to generate the bit clock when configured
00721  * for an internal bit clock. The division value is (DIV + 1) * 2.
00722  */
00723 /*@{*/
00724 #define BP_I2S_TCR2_DIV      (0U)          /*!< Bit position for I2S_TCR2_DIV. */
00725 #define BM_I2S_TCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */
00726 #define BS_I2S_TCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_TCR2_DIV. */
00727 
00728 /*! @brief Read current value of the I2S_TCR2_DIV field. */
00729 #define BR_I2S_TCR2_DIV(x)   (UNION_READ(hw_i2s_tcr2_t, HW_I2S_TCR2_ADDR(x), U, B.DIV))
00730 
00731 /*! @brief Format value for bitfield I2S_TCR2_DIV. */
00732 #define BF_I2S_TCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
00733 
00734 /*! @brief Set the DIV field to a new value. */
00735 #define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
00736 /*@}*/
00737 
00738 /*!
00739  * @name Register I2S_TCR2, field BCD[24] (RW)
00740  *
00741  * Configures the direction of the bit clock.
00742  *
00743  * Values:
00744  * - 0 - Bit clock is generated externally in Slave mode.
00745  * - 1 - Bit clock is generated internally in Master mode.
00746  */
00747 /*@{*/
00748 #define BP_I2S_TCR2_BCD      (24U)         /*!< Bit position for I2S_TCR2_BCD. */
00749 #define BM_I2S_TCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */
00750 #define BS_I2S_TCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCD. */
00751 
00752 /*! @brief Read current value of the I2S_TCR2_BCD field. */
00753 #define BR_I2S_TCR2_BCD(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD)))
00754 
00755 /*! @brief Format value for bitfield I2S_TCR2_BCD. */
00756 #define BF_I2S_TCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
00757 
00758 /*! @brief Set the BCD field to a new value. */
00759 #define BW_I2S_TCR2_BCD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD), v))
00760 /*@}*/
00761 
00762 /*!
00763  * @name Register I2S_TCR2, field BCP[25] (RW)
00764  *
00765  * Configures the polarity of the bit clock.
00766  *
00767  * Values:
00768  * - 0 - Bit clock is active high with drive outputs on rising edge and sample
00769  *     inputs on falling edge.
00770  * - 1 - Bit clock is active low with drive outputs on falling edge and sample
00771  *     inputs on rising edge.
00772  */
00773 /*@{*/
00774 #define BP_I2S_TCR2_BCP      (25U)         /*!< Bit position for I2S_TCR2_BCP. */
00775 #define BM_I2S_TCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */
00776 #define BS_I2S_TCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCP. */
00777 
00778 /*! @brief Read current value of the I2S_TCR2_BCP field. */
00779 #define BR_I2S_TCR2_BCP(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP)))
00780 
00781 /*! @brief Format value for bitfield I2S_TCR2_BCP. */
00782 #define BF_I2S_TCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
00783 
00784 /*! @brief Set the BCP field to a new value. */
00785 #define BW_I2S_TCR2_BCP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP), v))
00786 /*@}*/
00787 
00788 /*!
00789  * @name Register I2S_TCR2, field MSEL[27:26] (RW)
00790  *
00791  * Selects the audio Master Clock option used to generate an internally
00792  * generated bit clock. This field has no effect when configured for an externally
00793  * generated bit clock. Depending on the device, some Master Clock options might not be
00794  * available. See the chip configuration details for the availability and
00795  * chip-specific meaning of each option.
00796  *
00797  * Values:
00798  * - 00 - Bus Clock selected.
00799  * - 01 - Master Clock (MCLK) 1 option selected.
00800  * - 10 - Master Clock (MCLK) 2 option selected.
00801  * - 11 - Master Clock (MCLK) 3 option selected.
00802  */
00803 /*@{*/
00804 #define BP_I2S_TCR2_MSEL     (26U)         /*!< Bit position for I2S_TCR2_MSEL. */
00805 #define BM_I2S_TCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */
00806 #define BS_I2S_TCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_TCR2_MSEL. */
00807 
00808 /*! @brief Read current value of the I2S_TCR2_MSEL field. */
00809 #define BR_I2S_TCR2_MSEL(x)  (UNION_READ(hw_i2s_tcr2_t, HW_I2S_TCR2_ADDR(x), U, B.MSEL))
00810 
00811 /*! @brief Format value for bitfield I2S_TCR2_MSEL. */
00812 #define BF_I2S_TCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
00813 
00814 /*! @brief Set the MSEL field to a new value. */
00815 #define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
00816 /*@}*/
00817 
00818 /*!
00819  * @name Register I2S_TCR2, field BCI[28] (RW)
00820  *
00821  * When this field is set and using an internally generated bit clock in either
00822  * synchronous or asynchronous mode, the bit clock actually used by the
00823  * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
00824  * input as if the clock was externally generated). This has the effect of
00825  * decreasing the data input setup time, but increasing the data output valid time. The
00826  * slave mode timing from the datasheet should be used for the transmitter when
00827  * this bit is set. In synchronous mode, this bit allows the transmitter to use
00828  * the slave mode timing from the datasheet, while the receiver uses the master
00829  * mode timing. This field has no effect when configured for an externally generated
00830  * bit clock or when synchronous to another SAI peripheral .
00831  *
00832  * Values:
00833  * - 0 - No effect.
00834  * - 1 - Internal logic is clocked as if bit clock was externally generated.
00835  */
00836 /*@{*/
00837 #define BP_I2S_TCR2_BCI      (28U)         /*!< Bit position for I2S_TCR2_BCI. */
00838 #define BM_I2S_TCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */
00839 #define BS_I2S_TCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCI. */
00840 
00841 /*! @brief Read current value of the I2S_TCR2_BCI field. */
00842 #define BR_I2S_TCR2_BCI(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI)))
00843 
00844 /*! @brief Format value for bitfield I2S_TCR2_BCI. */
00845 #define BF_I2S_TCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
00846 
00847 /*! @brief Set the BCI field to a new value. */
00848 #define BW_I2S_TCR2_BCI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI), v))
00849 /*@}*/
00850 
00851 /*!
00852  * @name Register I2S_TCR2, field BCS[29] (RW)
00853  *
00854  * This field swaps the bit clock used by the transmitter. When the transmitter
00855  * is configured in asynchronous mode and this bit is set, the transmitter is
00856  * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
00857  * receiver to share the same bit clock, but the transmitter continues to use the
00858  * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
00859  * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
00860  * the same value. When both are set, the transmitter and receiver are both
00861  * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
00862  * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
00863  * peripheral.
00864  *
00865  * Values:
00866  * - 0 - Use the normal bit clock source.
00867  * - 1 - Swap the bit clock source.
00868  */
00869 /*@{*/
00870 #define BP_I2S_TCR2_BCS      (29U)         /*!< Bit position for I2S_TCR2_BCS. */
00871 #define BM_I2S_TCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */
00872 #define BS_I2S_TCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_TCR2_BCS. */
00873 
00874 /*! @brief Read current value of the I2S_TCR2_BCS field. */
00875 #define BR_I2S_TCR2_BCS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS)))
00876 
00877 /*! @brief Format value for bitfield I2S_TCR2_BCS. */
00878 #define BF_I2S_TCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
00879 
00880 /*! @brief Set the BCS field to a new value. */
00881 #define BW_I2S_TCR2_BCS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS), v))
00882 /*@}*/
00883 
00884 /*!
00885  * @name Register I2S_TCR2, field SYNC[31:30] (RW)
00886  *
00887  * Configures between asynchronous and synchronous modes of operation. When
00888  * configured for a synchronous mode of operation, the receiver or other SAI
00889  * peripheral must be configured for asynchronous operation.
00890  *
00891  * Values:
00892  * - 00 - Asynchronous mode.
00893  * - 01 - Synchronous with receiver.
00894  * - 10 - Synchronous with another SAI transmitter.
00895  * - 11 - Synchronous with another SAI receiver.
00896  */
00897 /*@{*/
00898 #define BP_I2S_TCR2_SYNC     (30U)         /*!< Bit position for I2S_TCR2_SYNC. */
00899 #define BM_I2S_TCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */
00900 #define BS_I2S_TCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_TCR2_SYNC. */
00901 
00902 /*! @brief Read current value of the I2S_TCR2_SYNC field. */
00903 #define BR_I2S_TCR2_SYNC(x)  (UNION_READ(hw_i2s_tcr2_t, HW_I2S_TCR2_ADDR(x), U, B.SYNC))
00904 
00905 /*! @brief Format value for bitfield I2S_TCR2_SYNC. */
00906 #define BF_I2S_TCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
00907 
00908 /*! @brief Set the SYNC field to a new value. */
00909 #define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
00910 /*@}*/
00911 
00912 /*******************************************************************************
00913  * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
00914  ******************************************************************************/
00915 
00916 /*!
00917  * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
00918  *
00919  * Reset value: 0x00000000U
00920  *
00921  * This register must not be altered when TCSR[TE] is set.
00922  */
00923 typedef union _hw_i2s_tcr3
00924 {
00925     uint32_t U;
00926     struct _hw_i2s_tcr3_bitfields
00927     {
00928         uint32_t WDFL : 5;             /*!< [4:0] Word Flag Configuration */
00929         uint32_t RESERVED0 : 11;       /*!< [15:5]  */
00930         uint32_t TCE : 2;              /*!< [17:16] Transmit Channel Enable */
00931         uint32_t RESERVED1 : 14;       /*!< [31:18]  */
00932     } B;
00933 } hw_i2s_tcr3_t;
00934 
00935 /*!
00936  * @name Constants and macros for entire I2S_TCR3 register
00937  */
00938 /*@{*/
00939 #define HW_I2S_TCR3_ADDR(x)      ((x) + 0xCU)
00940 
00941 #define HW_I2S_TCR3(x)           (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
00942 #define HW_I2S_TCR3_RD(x)        (ADDRESS_READ(hw_i2s_tcr3_t, HW_I2S_TCR3_ADDR(x)))
00943 #define HW_I2S_TCR3_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcr3_t, HW_I2S_TCR3_ADDR(x), v))
00944 #define HW_I2S_TCR3_SET(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) |  (v)))
00945 #define HW_I2S_TCR3_CLR(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
00946 #define HW_I2S_TCR3_TOG(x, v)    (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^  (v)))
00947 /*@}*/
00948 
00949 /*
00950  * Constants & macros for individual I2S_TCR3 bitfields
00951  */
00952 
00953 /*!
00954  * @name Register I2S_TCR3, field WDFL[4:0] (RW)
00955  *
00956  * Configures which word sets the start of word flag. The value written must be
00957  * one less than the word number. For example, writing 0 configures the first
00958  * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
00959  * start of word flag is never set.
00960  */
00961 /*@{*/
00962 #define BP_I2S_TCR3_WDFL     (0U)          /*!< Bit position for I2S_TCR3_WDFL. */
00963 #define BM_I2S_TCR3_WDFL     (0x0000001FU) /*!< Bit mask for I2S_TCR3_WDFL. */
00964 #define BS_I2S_TCR3_WDFL     (5U)          /*!< Bit field size in bits for I2S_TCR3_WDFL. */
00965 
00966 /*! @brief Read current value of the I2S_TCR3_WDFL field. */
00967 #define BR_I2S_TCR3_WDFL(x)  (UNION_READ(hw_i2s_tcr3_t, HW_I2S_TCR3_ADDR(x), U, B.WDFL))
00968 
00969 /*! @brief Format value for bitfield I2S_TCR3_WDFL. */
00970 #define BF_I2S_TCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
00971 
00972 /*! @brief Set the WDFL field to a new value. */
00973 #define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
00974 /*@}*/
00975 
00976 /*!
00977  * @name Register I2S_TCR3, field TCE[17:16] (RW)
00978  *
00979  * Enables the corresponding data channel for transmit operation. A channel must
00980  * be enabled before its FIFO is accessed.
00981  *
00982  * Values:
00983  * - 0 - Transmit data channel N is disabled.
00984  * - 1 - Transmit data channel N is enabled.
00985  */
00986 /*@{*/
00987 #define BP_I2S_TCR3_TCE      (16U)         /*!< Bit position for I2S_TCR3_TCE. */
00988 #define BM_I2S_TCR3_TCE      (0x00030000U) /*!< Bit mask for I2S_TCR3_TCE. */
00989 #define BS_I2S_TCR3_TCE      (2U)          /*!< Bit field size in bits for I2S_TCR3_TCE. */
00990 
00991 /*! @brief Read current value of the I2S_TCR3_TCE field. */
00992 #define BR_I2S_TCR3_TCE(x)   (UNION_READ(hw_i2s_tcr3_t, HW_I2S_TCR3_ADDR(x), U, B.TCE))
00993 
00994 /*! @brief Format value for bitfield I2S_TCR3_TCE. */
00995 #define BF_I2S_TCR3_TCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
00996 
00997 /*! @brief Set the TCE field to a new value. */
00998 #define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
00999 /*@}*/
01000 
01001 /*******************************************************************************
01002  * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
01003  ******************************************************************************/
01004 
01005 /*!
01006  * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
01007  *
01008  * Reset value: 0x00000000U
01009  *
01010  * This register must not be altered when TCSR[TE] is set.
01011  */
01012 typedef union _hw_i2s_tcr4
01013 {
01014     uint32_t U;
01015     struct _hw_i2s_tcr4_bitfields
01016     {
01017         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
01018         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
01019         uint32_t RESERVED0 : 1;        /*!< [2]  */
01020         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
01021         uint32_t MF : 1;               /*!< [4] MSB First */
01022         uint32_t RESERVED1 : 3;        /*!< [7:5]  */
01023         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
01024         uint32_t RESERVED2 : 3;        /*!< [15:13]  */
01025         uint32_t FRSZ : 5;             /*!< [20:16] Frame size */
01026         uint32_t RESERVED3 : 11;       /*!< [31:21]  */
01027     } B;
01028 } hw_i2s_tcr4_t;
01029 
01030 /*!
01031  * @name Constants and macros for entire I2S_TCR4 register
01032  */
01033 /*@{*/
01034 #define HW_I2S_TCR4_ADDR(x)      ((x) + 0x10U)
01035 
01036 #define HW_I2S_TCR4(x)           (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
01037 #define HW_I2S_TCR4_RD(x)        (ADDRESS_READ(hw_i2s_tcr4_t, HW_I2S_TCR4_ADDR(x)))
01038 #define HW_I2S_TCR4_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcr4_t, HW_I2S_TCR4_ADDR(x), v))
01039 #define HW_I2S_TCR4_SET(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) |  (v)))
01040 #define HW_I2S_TCR4_CLR(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
01041 #define HW_I2S_TCR4_TOG(x, v)    (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^  (v)))
01042 /*@}*/
01043 
01044 /*
01045  * Constants & macros for individual I2S_TCR4 bitfields
01046  */
01047 
01048 /*!
01049  * @name Register I2S_TCR4, field FSD[0] (RW)
01050  *
01051  * Configures the direction of the frame sync.
01052  *
01053  * Values:
01054  * - 0 - Frame sync is generated externally in Slave mode.
01055  * - 1 - Frame sync is generated internally in Master mode.
01056  */
01057 /*@{*/
01058 #define BP_I2S_TCR4_FSD      (0U)          /*!< Bit position for I2S_TCR4_FSD. */
01059 #define BM_I2S_TCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */
01060 #define BS_I2S_TCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSD. */
01061 
01062 /*! @brief Read current value of the I2S_TCR4_FSD field. */
01063 #define BR_I2S_TCR4_FSD(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD)))
01064 
01065 /*! @brief Format value for bitfield I2S_TCR4_FSD. */
01066 #define BF_I2S_TCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
01067 
01068 /*! @brief Set the FSD field to a new value. */
01069 #define BW_I2S_TCR4_FSD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD), v))
01070 /*@}*/
01071 
01072 /*!
01073  * @name Register I2S_TCR4, field FSP[1] (RW)
01074  *
01075  * Configures the polarity of the frame sync.
01076  *
01077  * Values:
01078  * - 0 - Frame sync is active high.
01079  * - 1 - Frame sync is active low.
01080  */
01081 /*@{*/
01082 #define BP_I2S_TCR4_FSP      (1U)          /*!< Bit position for I2S_TCR4_FSP. */
01083 #define BM_I2S_TCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */
01084 #define BS_I2S_TCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSP. */
01085 
01086 /*! @brief Read current value of the I2S_TCR4_FSP field. */
01087 #define BR_I2S_TCR4_FSP(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP)))
01088 
01089 /*! @brief Format value for bitfield I2S_TCR4_FSP. */
01090 #define BF_I2S_TCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
01091 
01092 /*! @brief Set the FSP field to a new value. */
01093 #define BW_I2S_TCR4_FSP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP), v))
01094 /*@}*/
01095 
01096 /*!
01097  * @name Register I2S_TCR4, field FSE[3] (RW)
01098  *
01099  * Values:
01100  * - 0 - Frame sync asserts with the first bit of the frame.
01101  * - 1 - Frame sync asserts one bit before the first bit of the frame.
01102  */
01103 /*@{*/
01104 #define BP_I2S_TCR4_FSE      (3U)          /*!< Bit position for I2S_TCR4_FSE. */
01105 #define BM_I2S_TCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */
01106 #define BS_I2S_TCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_TCR4_FSE. */
01107 
01108 /*! @brief Read current value of the I2S_TCR4_FSE field. */
01109 #define BR_I2S_TCR4_FSE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE)))
01110 
01111 /*! @brief Format value for bitfield I2S_TCR4_FSE. */
01112 #define BF_I2S_TCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
01113 
01114 /*! @brief Set the FSE field to a new value. */
01115 #define BW_I2S_TCR4_FSE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE), v))
01116 /*@}*/
01117 
01118 /*!
01119  * @name Register I2S_TCR4, field MF[4] (RW)
01120  *
01121  * Configures whether the LSB or the MSB is transmitted first.
01122  *
01123  * Values:
01124  * - 0 - LSB is transmitted first.
01125  * - 1 - MSB is transmitted first.
01126  */
01127 /*@{*/
01128 #define BP_I2S_TCR4_MF       (4U)          /*!< Bit position for I2S_TCR4_MF. */
01129 #define BM_I2S_TCR4_MF       (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */
01130 #define BS_I2S_TCR4_MF       (1U)          /*!< Bit field size in bits for I2S_TCR4_MF. */
01131 
01132 /*! @brief Read current value of the I2S_TCR4_MF field. */
01133 #define BR_I2S_TCR4_MF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF)))
01134 
01135 /*! @brief Format value for bitfield I2S_TCR4_MF. */
01136 #define BF_I2S_TCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
01137 
01138 /*! @brief Set the MF field to a new value. */
01139 #define BW_I2S_TCR4_MF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF), v))
01140 /*@}*/
01141 
01142 /*!
01143  * @name Register I2S_TCR4, field SYWD[12:8] (RW)
01144  *
01145  * Configures the length of the frame sync in number of bit clocks. The value
01146  * written must be one less than the number of bit clocks. For example, write 0 for
01147  * the frame sync to assert for one bit clock only. The sync width cannot be
01148  * configured longer than the first word of the frame.
01149  */
01150 /*@{*/
01151 #define BP_I2S_TCR4_SYWD     (8U)          /*!< Bit position for I2S_TCR4_SYWD. */
01152 #define BM_I2S_TCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */
01153 #define BS_I2S_TCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_TCR4_SYWD. */
01154 
01155 /*! @brief Read current value of the I2S_TCR4_SYWD field. */
01156 #define BR_I2S_TCR4_SYWD(x)  (UNION_READ(hw_i2s_tcr4_t, HW_I2S_TCR4_ADDR(x), U, B.SYWD))
01157 
01158 /*! @brief Format value for bitfield I2S_TCR4_SYWD. */
01159 #define BF_I2S_TCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
01160 
01161 /*! @brief Set the SYWD field to a new value. */
01162 #define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
01163 /*@}*/
01164 
01165 /*!
01166  * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
01167  *
01168  * Configures the number of words in each frame. The value written must be one
01169  * less than the number of words in the frame. For example, write 0 for one word
01170  * per frame. The maximum supported frame size is 32 words.
01171  */
01172 /*@{*/
01173 #define BP_I2S_TCR4_FRSZ     (16U)         /*!< Bit position for I2S_TCR4_FRSZ. */
01174 #define BM_I2S_TCR4_FRSZ     (0x001F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */
01175 #define BS_I2S_TCR4_FRSZ     (5U)          /*!< Bit field size in bits for I2S_TCR4_FRSZ. */
01176 
01177 /*! @brief Read current value of the I2S_TCR4_FRSZ field. */
01178 #define BR_I2S_TCR4_FRSZ(x)  (UNION_READ(hw_i2s_tcr4_t, HW_I2S_TCR4_ADDR(x), U, B.FRSZ))
01179 
01180 /*! @brief Format value for bitfield I2S_TCR4_FRSZ. */
01181 #define BF_I2S_TCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
01182 
01183 /*! @brief Set the FRSZ field to a new value. */
01184 #define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
01185 /*@}*/
01186 
01187 /*******************************************************************************
01188  * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
01189  ******************************************************************************/
01190 
01191 /*!
01192  * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
01193  *
01194  * Reset value: 0x00000000U
01195  *
01196  * This register must not be altered when TCSR[TE] is set.
01197  */
01198 typedef union _hw_i2s_tcr5
01199 {
01200     uint32_t U;
01201     struct _hw_i2s_tcr5_bitfields
01202     {
01203         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
01204         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
01205         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
01206         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
01207         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
01208         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
01209         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
01210     } B;
01211 } hw_i2s_tcr5_t;
01212 
01213 /*!
01214  * @name Constants and macros for entire I2S_TCR5 register
01215  */
01216 /*@{*/
01217 #define HW_I2S_TCR5_ADDR(x)      ((x) + 0x14U)
01218 
01219 #define HW_I2S_TCR5(x)           (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
01220 #define HW_I2S_TCR5_RD(x)        (ADDRESS_READ(hw_i2s_tcr5_t, HW_I2S_TCR5_ADDR(x)))
01221 #define HW_I2S_TCR5_WR(x, v)     (ADDRESS_WRITE(hw_i2s_tcr5_t, HW_I2S_TCR5_ADDR(x), v))
01222 #define HW_I2S_TCR5_SET(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) |  (v)))
01223 #define HW_I2S_TCR5_CLR(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
01224 #define HW_I2S_TCR5_TOG(x, v)    (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^  (v)))
01225 /*@}*/
01226 
01227 /*
01228  * Constants & macros for individual I2S_TCR5 bitfields
01229  */
01230 
01231 /*!
01232  * @name Register I2S_TCR5, field FBT[12:8] (RW)
01233  *
01234  * Configures the bit index for the first bit transmitted for each word in the
01235  * frame. If configured for MSB First, the index of the next bit transmitted is
01236  * one less than the current bit transmitted. If configured for LSB First, the
01237  * index of the next bit transmitted is one more than the current bit transmitted.
01238  * The value written must be greater than or equal to the word width when
01239  * configured for MSB First. The value written must be less than or equal to 31-word width
01240  * when configured for LSB First.
01241  */
01242 /*@{*/
01243 #define BP_I2S_TCR5_FBT      (8U)          /*!< Bit position for I2S_TCR5_FBT. */
01244 #define BM_I2S_TCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */
01245 #define BS_I2S_TCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_TCR5_FBT. */
01246 
01247 /*! @brief Read current value of the I2S_TCR5_FBT field. */
01248 #define BR_I2S_TCR5_FBT(x)   (UNION_READ(hw_i2s_tcr5_t, HW_I2S_TCR5_ADDR(x), U, B.FBT))
01249 
01250 /*! @brief Format value for bitfield I2S_TCR5_FBT. */
01251 #define BF_I2S_TCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
01252 
01253 /*! @brief Set the FBT field to a new value. */
01254 #define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
01255 /*@}*/
01256 
01257 /*!
01258  * @name Register I2S_TCR5, field W0W[20:16] (RW)
01259  *
01260  * Configures the number of bits in the first word in each frame. The value
01261  * written must be one less than the number of bits in the first word. Word width of
01262  * less than 8 bits is not supported if there is only one word per frame.
01263  */
01264 /*@{*/
01265 #define BP_I2S_TCR5_W0W      (16U)         /*!< Bit position for I2S_TCR5_W0W. */
01266 #define BM_I2S_TCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */
01267 #define BS_I2S_TCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_TCR5_W0W. */
01268 
01269 /*! @brief Read current value of the I2S_TCR5_W0W field. */
01270 #define BR_I2S_TCR5_W0W(x)   (UNION_READ(hw_i2s_tcr5_t, HW_I2S_TCR5_ADDR(x), U, B.W0W))
01271 
01272 /*! @brief Format value for bitfield I2S_TCR5_W0W. */
01273 #define BF_I2S_TCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
01274 
01275 /*! @brief Set the W0W field to a new value. */
01276 #define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
01277 /*@}*/
01278 
01279 /*!
01280  * @name Register I2S_TCR5, field WNW[28:24] (RW)
01281  *
01282  * Configures the number of bits in each word, for each word except the first in
01283  * the frame. The value written must be one less than the number of bits per
01284  * word. Word width of less than 8 bits is not supported.
01285  */
01286 /*@{*/
01287 #define BP_I2S_TCR5_WNW      (24U)         /*!< Bit position for I2S_TCR5_WNW. */
01288 #define BM_I2S_TCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */
01289 #define BS_I2S_TCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_TCR5_WNW. */
01290 
01291 /*! @brief Read current value of the I2S_TCR5_WNW field. */
01292 #define BR_I2S_TCR5_WNW(x)   (UNION_READ(hw_i2s_tcr5_t, HW_I2S_TCR5_ADDR(x), U, B.WNW))
01293 
01294 /*! @brief Format value for bitfield I2S_TCR5_WNW. */
01295 #define BF_I2S_TCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
01296 
01297 /*! @brief Set the WNW field to a new value. */
01298 #define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
01299 /*@}*/
01300 
01301 /*******************************************************************************
01302  * HW_I2S_TDRn - SAI Transmit Data Register
01303  ******************************************************************************/
01304 
01305 /*!
01306  * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
01307  *
01308  * Reset value: 0x00000000U
01309  */
01310 typedef union _hw_i2s_tdrn
01311 {
01312     uint32_t U;
01313     struct _hw_i2s_tdrn_bitfields
01314     {
01315         uint32_t TDR : 32;             /*!< [31:0] Transmit Data Register */
01316     } B;
01317 } hw_i2s_tdrn_t;
01318 
01319 /*!
01320  * @name Constants and macros for entire I2S_TDRn register
01321  */
01322 /*@{*/
01323 #define HW_I2S_TDRn_COUNT (2U)
01324 
01325 #define HW_I2S_TDRn_ADDR(x, n)   ((x) + 0x20U + (0x4U * (n)))
01326 
01327 #define HW_I2S_TDRn(x, n)        (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
01328 #define HW_I2S_TDRn_RD(x, n)     (ADDRESS_READ(hw_i2s_tdrn_t, HW_I2S_TDRn_ADDR(x, n)))
01329 #define HW_I2S_TDRn_WR(x, n, v)  (ADDRESS_WRITE(hw_i2s_tdrn_t, HW_I2S_TDRn_ADDR(x, n), v))
01330 /*@}*/
01331 
01332 /*
01333  * Constants & macros for individual I2S_TDRn bitfields
01334  */
01335 
01336 /*!
01337  * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
01338  *
01339  * The corresponding TCR3[TCE] bit must be set before accessing the channel's
01340  * transmit data register. Writes to this register when the transmit FIFO is not
01341  * full will push the data written into the transmit data FIFO. Writes to this
01342  * register when the transmit FIFO is full are ignored.
01343  */
01344 /*@{*/
01345 #define BP_I2S_TDRn_TDR      (0U)          /*!< Bit position for I2S_TDRn_TDR. */
01346 #define BM_I2S_TDRn_TDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */
01347 #define BS_I2S_TDRn_TDR      (32U)         /*!< Bit field size in bits for I2S_TDRn_TDR. */
01348 
01349 /*! @brief Format value for bitfield I2S_TDRn_TDR. */
01350 #define BF_I2S_TDRn_TDR(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
01351 
01352 /*! @brief Set the TDR field to a new value. */
01353 #define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
01354 /*@}*/
01355 
01356 /*******************************************************************************
01357  * HW_I2S_TFRn - SAI Transmit FIFO Register
01358  ******************************************************************************/
01359 
01360 /*!
01361  * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
01362  *
01363  * Reset value: 0x00000000U
01364  *
01365  * The MSB of the read and write pointers is used to distinguish between FIFO
01366  * full and empty conditions. If the read and write pointers are identical, then
01367  * the FIFO is empty. If the read and write pointers are identical except for the
01368  * MSB, then the FIFO is full.
01369  */
01370 typedef union _hw_i2s_tfrn
01371 {
01372     uint32_t U;
01373     struct _hw_i2s_tfrn_bitfields
01374     {
01375         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
01376         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
01377         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
01378         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
01379     } B;
01380 } hw_i2s_tfrn_t;
01381 
01382 /*!
01383  * @name Constants and macros for entire I2S_TFRn register
01384  */
01385 /*@{*/
01386 #define HW_I2S_TFRn_COUNT (2U)
01387 
01388 #define HW_I2S_TFRn_ADDR(x, n)   ((x) + 0x40U + (0x4U * (n)))
01389 
01390 #define HW_I2S_TFRn(x, n)        (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
01391 #define HW_I2S_TFRn_RD(x, n)     (ADDRESS_READ(hw_i2s_tfrn_t, HW_I2S_TFRn_ADDR(x, n)))
01392 /*@}*/
01393 
01394 /*
01395  * Constants & macros for individual I2S_TFRn bitfields
01396  */
01397 
01398 /*!
01399  * @name Register I2S_TFRn, field RFP[3:0] (RO)
01400  *
01401  * FIFO read pointer for transmit data channel.
01402  */
01403 /*@{*/
01404 #define BP_I2S_TFRn_RFP      (0U)          /*!< Bit position for I2S_TFRn_RFP. */
01405 #define BM_I2S_TFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */
01406 #define BS_I2S_TFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_RFP. */
01407 
01408 /*! @brief Read current value of the I2S_TFRn_RFP field. */
01409 #define BR_I2S_TFRn_RFP(x, n) (UNION_READ(hw_i2s_tfrn_t, HW_I2S_TFRn_ADDR(x, n), U, B.RFP))
01410 /*@}*/
01411 
01412 /*!
01413  * @name Register I2S_TFRn, field WFP[19:16] (RO)
01414  *
01415  * FIFO write pointer for transmit data channel.
01416  */
01417 /*@{*/
01418 #define BP_I2S_TFRn_WFP      (16U)         /*!< Bit position for I2S_TFRn_WFP. */
01419 #define BM_I2S_TFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */
01420 #define BS_I2S_TFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_TFRn_WFP. */
01421 
01422 /*! @brief Read current value of the I2S_TFRn_WFP field. */
01423 #define BR_I2S_TFRn_WFP(x, n) (UNION_READ(hw_i2s_tfrn_t, HW_I2S_TFRn_ADDR(x, n), U, B.WFP))
01424 /*@}*/
01425 
01426 /*******************************************************************************
01427  * HW_I2S_TMR - SAI Transmit Mask Register
01428  ******************************************************************************/
01429 
01430 /*!
01431  * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
01432  *
01433  * Reset value: 0x00000000U
01434  *
01435  * This register is double-buffered and updates: When TCSR[TE] is first set At
01436  * the end of each frame. This allows the masked words in each frame to change
01437  * from frame to frame.
01438  */
01439 typedef union _hw_i2s_tmr
01440 {
01441     uint32_t U;
01442     struct _hw_i2s_tmr_bitfields
01443     {
01444         uint32_t TWM : 32;             /*!< [31:0] Transmit Word Mask */
01445     } B;
01446 } hw_i2s_tmr_t;
01447 
01448 /*!
01449  * @name Constants and macros for entire I2S_TMR register
01450  */
01451 /*@{*/
01452 #define HW_I2S_TMR_ADDR(x)       ((x) + 0x60U)
01453 
01454 #define HW_I2S_TMR(x)            (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
01455 #define HW_I2S_TMR_RD(x)         (ADDRESS_READ(hw_i2s_tmr_t, HW_I2S_TMR_ADDR(x)))
01456 #define HW_I2S_TMR_WR(x, v)      (ADDRESS_WRITE(hw_i2s_tmr_t, HW_I2S_TMR_ADDR(x), v))
01457 #define HW_I2S_TMR_SET(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) |  (v)))
01458 #define HW_I2S_TMR_CLR(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
01459 #define HW_I2S_TMR_TOG(x, v)     (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^  (v)))
01460 /*@}*/
01461 
01462 /*
01463  * Constants & macros for individual I2S_TMR bitfields
01464  */
01465 
01466 /*!
01467  * @name Register I2S_TMR, field TWM[31:0] (RW)
01468  *
01469  * Configures whether the transmit word is masked (transmit data pin tristated
01470  * and transmit data not read from FIFO) for the corresponding word in the frame.
01471  *
01472  * Values:
01473  * - 0 - Word N is enabled.
01474  * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
01475  */
01476 /*@{*/
01477 #define BP_I2S_TMR_TWM       (0U)          /*!< Bit position for I2S_TMR_TWM. */
01478 #define BM_I2S_TMR_TWM       (0xFFFFFFFFU) /*!< Bit mask for I2S_TMR_TWM. */
01479 #define BS_I2S_TMR_TWM       (32U)         /*!< Bit field size in bits for I2S_TMR_TWM. */
01480 
01481 /*! @brief Read current value of the I2S_TMR_TWM field. */
01482 #define BR_I2S_TMR_TWM(x)    (HW_I2S_TMR(x).U)
01483 
01484 /*! @brief Format value for bitfield I2S_TMR_TWM. */
01485 #define BF_I2S_TMR_TWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
01486 
01487 /*! @brief Set the TWM field to a new value. */
01488 #define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
01489 /*@}*/
01490 
01491 /*******************************************************************************
01492  * HW_I2S_RCSR - SAI Receive Control Register
01493  ******************************************************************************/
01494 
01495 /*!
01496  * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
01497  *
01498  * Reset value: 0x00000000U
01499  */
01500 typedef union _hw_i2s_rcsr
01501 {
01502     uint32_t U;
01503     struct _hw_i2s_rcsr_bitfields
01504     {
01505         uint32_t FRDE : 1;             /*!< [0] FIFO Request DMA Enable */
01506         uint32_t FWDE : 1;             /*!< [1] FIFO Warning DMA Enable */
01507         uint32_t RESERVED0 : 6;        /*!< [7:2]  */
01508         uint32_t FRIE : 1;             /*!< [8] FIFO Request Interrupt Enable */
01509         uint32_t FWIE : 1;             /*!< [9] FIFO Warning Interrupt Enable */
01510         uint32_t FEIE : 1;             /*!< [10] FIFO Error Interrupt Enable */
01511         uint32_t SEIE : 1;             /*!< [11] Sync Error Interrupt Enable */
01512         uint32_t WSIE : 1;             /*!< [12] Word Start Interrupt Enable */
01513         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
01514         uint32_t FRF : 1;              /*!< [16] FIFO Request Flag */
01515         uint32_t FWF : 1;              /*!< [17] FIFO Warning Flag */
01516         uint32_t FEF : 1;              /*!< [18] FIFO Error Flag */
01517         uint32_t SEF : 1;              /*!< [19] Sync Error Flag */
01518         uint32_t WSF : 1;              /*!< [20] Word Start Flag */
01519         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
01520         uint32_t SR : 1;               /*!< [24] Software Reset */
01521         uint32_t FR : 1;               /*!< [25] FIFO Reset */
01522         uint32_t RESERVED3 : 2;        /*!< [27:26]  */
01523         uint32_t BCE : 1;              /*!< [28] Bit Clock Enable */
01524         uint32_t DBGE : 1;             /*!< [29] Debug Enable */
01525         uint32_t STOPE : 1;            /*!< [30] Stop Enable */
01526         uint32_t RE : 1;               /*!< [31] Receiver Enable */
01527     } B;
01528 } hw_i2s_rcsr_t;
01529 
01530 /*!
01531  * @name Constants and macros for entire I2S_RCSR register
01532  */
01533 /*@{*/
01534 #define HW_I2S_RCSR_ADDR(x)      ((x) + 0x80U)
01535 
01536 #define HW_I2S_RCSR(x)           (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
01537 #define HW_I2S_RCSR_RD(x)        (ADDRESS_READ(hw_i2s_rcsr_t, HW_I2S_RCSR_ADDR(x)))
01538 #define HW_I2S_RCSR_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcsr_t, HW_I2S_RCSR_ADDR(x), v))
01539 #define HW_I2S_RCSR_SET(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) |  (v)))
01540 #define HW_I2S_RCSR_CLR(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
01541 #define HW_I2S_RCSR_TOG(x, v)    (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^  (v)))
01542 /*@}*/
01543 
01544 /*
01545  * Constants & macros for individual I2S_RCSR bitfields
01546  */
01547 
01548 /*!
01549  * @name Register I2S_RCSR, field FRDE[0] (RW)
01550  *
01551  * Enables/disables DMA requests.
01552  *
01553  * Values:
01554  * - 0 - Disables the DMA request.
01555  * - 1 - Enables the DMA request.
01556  */
01557 /*@{*/
01558 #define BP_I2S_RCSR_FRDE     (0U)          /*!< Bit position for I2S_RCSR_FRDE. */
01559 #define BM_I2S_RCSR_FRDE     (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */
01560 #define BS_I2S_RCSR_FRDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRDE. */
01561 
01562 /*! @brief Read current value of the I2S_RCSR_FRDE field. */
01563 #define BR_I2S_RCSR_FRDE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE)))
01564 
01565 /*! @brief Format value for bitfield I2S_RCSR_FRDE. */
01566 #define BF_I2S_RCSR_FRDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
01567 
01568 /*! @brief Set the FRDE field to a new value. */
01569 #define BW_I2S_RCSR_FRDE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE), v))
01570 /*@}*/
01571 
01572 /*!
01573  * @name Register I2S_RCSR, field FWDE[1] (RW)
01574  *
01575  * Enables/disables DMA requests.
01576  *
01577  * Values:
01578  * - 0 - Disables the DMA request.
01579  * - 1 - Enables the DMA request.
01580  */
01581 /*@{*/
01582 #define BP_I2S_RCSR_FWDE     (1U)          /*!< Bit position for I2S_RCSR_FWDE. */
01583 #define BM_I2S_RCSR_FWDE     (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */
01584 #define BS_I2S_RCSR_FWDE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWDE. */
01585 
01586 /*! @brief Read current value of the I2S_RCSR_FWDE field. */
01587 #define BR_I2S_RCSR_FWDE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE)))
01588 
01589 /*! @brief Format value for bitfield I2S_RCSR_FWDE. */
01590 #define BF_I2S_RCSR_FWDE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
01591 
01592 /*! @brief Set the FWDE field to a new value. */
01593 #define BW_I2S_RCSR_FWDE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE), v))
01594 /*@}*/
01595 
01596 /*!
01597  * @name Register I2S_RCSR, field FRIE[8] (RW)
01598  *
01599  * Enables/disables FIFO request interrupts.
01600  *
01601  * Values:
01602  * - 0 - Disables the interrupt.
01603  * - 1 - Enables the interrupt.
01604  */
01605 /*@{*/
01606 #define BP_I2S_RCSR_FRIE     (8U)          /*!< Bit position for I2S_RCSR_FRIE. */
01607 #define BM_I2S_RCSR_FRIE     (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */
01608 #define BS_I2S_RCSR_FRIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FRIE. */
01609 
01610 /*! @brief Read current value of the I2S_RCSR_FRIE field. */
01611 #define BR_I2S_RCSR_FRIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE)))
01612 
01613 /*! @brief Format value for bitfield I2S_RCSR_FRIE. */
01614 #define BF_I2S_RCSR_FRIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
01615 
01616 /*! @brief Set the FRIE field to a new value. */
01617 #define BW_I2S_RCSR_FRIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE), v))
01618 /*@}*/
01619 
01620 /*!
01621  * @name Register I2S_RCSR, field FWIE[9] (RW)
01622  *
01623  * Enables/disables FIFO warning interrupts.
01624  *
01625  * Values:
01626  * - 0 - Disables the interrupt.
01627  * - 1 - Enables the interrupt.
01628  */
01629 /*@{*/
01630 #define BP_I2S_RCSR_FWIE     (9U)          /*!< Bit position for I2S_RCSR_FWIE. */
01631 #define BM_I2S_RCSR_FWIE     (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */
01632 #define BS_I2S_RCSR_FWIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FWIE. */
01633 
01634 /*! @brief Read current value of the I2S_RCSR_FWIE field. */
01635 #define BR_I2S_RCSR_FWIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE)))
01636 
01637 /*! @brief Format value for bitfield I2S_RCSR_FWIE. */
01638 #define BF_I2S_RCSR_FWIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
01639 
01640 /*! @brief Set the FWIE field to a new value. */
01641 #define BW_I2S_RCSR_FWIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE), v))
01642 /*@}*/
01643 
01644 /*!
01645  * @name Register I2S_RCSR, field FEIE[10] (RW)
01646  *
01647  * Enables/disables FIFO error interrupts.
01648  *
01649  * Values:
01650  * - 0 - Disables the interrupt.
01651  * - 1 - Enables the interrupt.
01652  */
01653 /*@{*/
01654 #define BP_I2S_RCSR_FEIE     (10U)         /*!< Bit position for I2S_RCSR_FEIE. */
01655 #define BM_I2S_RCSR_FEIE     (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */
01656 #define BS_I2S_RCSR_FEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_FEIE. */
01657 
01658 /*! @brief Read current value of the I2S_RCSR_FEIE field. */
01659 #define BR_I2S_RCSR_FEIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE)))
01660 
01661 /*! @brief Format value for bitfield I2S_RCSR_FEIE. */
01662 #define BF_I2S_RCSR_FEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
01663 
01664 /*! @brief Set the FEIE field to a new value. */
01665 #define BW_I2S_RCSR_FEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE), v))
01666 /*@}*/
01667 
01668 /*!
01669  * @name Register I2S_RCSR, field SEIE[11] (RW)
01670  *
01671  * Enables/disables sync error interrupts.
01672  *
01673  * Values:
01674  * - 0 - Disables interrupt.
01675  * - 1 - Enables interrupt.
01676  */
01677 /*@{*/
01678 #define BP_I2S_RCSR_SEIE     (11U)         /*!< Bit position for I2S_RCSR_SEIE. */
01679 #define BM_I2S_RCSR_SEIE     (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */
01680 #define BS_I2S_RCSR_SEIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_SEIE. */
01681 
01682 /*! @brief Read current value of the I2S_RCSR_SEIE field. */
01683 #define BR_I2S_RCSR_SEIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE)))
01684 
01685 /*! @brief Format value for bitfield I2S_RCSR_SEIE. */
01686 #define BF_I2S_RCSR_SEIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
01687 
01688 /*! @brief Set the SEIE field to a new value. */
01689 #define BW_I2S_RCSR_SEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE), v))
01690 /*@}*/
01691 
01692 /*!
01693  * @name Register I2S_RCSR, field WSIE[12] (RW)
01694  *
01695  * Enables/disables word start interrupts.
01696  *
01697  * Values:
01698  * - 0 - Disables interrupt.
01699  * - 1 - Enables interrupt.
01700  */
01701 /*@{*/
01702 #define BP_I2S_RCSR_WSIE     (12U)         /*!< Bit position for I2S_RCSR_WSIE. */
01703 #define BM_I2S_RCSR_WSIE     (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */
01704 #define BS_I2S_RCSR_WSIE     (1U)          /*!< Bit field size in bits for I2S_RCSR_WSIE. */
01705 
01706 /*! @brief Read current value of the I2S_RCSR_WSIE field. */
01707 #define BR_I2S_RCSR_WSIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE)))
01708 
01709 /*! @brief Format value for bitfield I2S_RCSR_WSIE. */
01710 #define BF_I2S_RCSR_WSIE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
01711 
01712 /*! @brief Set the WSIE field to a new value. */
01713 #define BW_I2S_RCSR_WSIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE), v))
01714 /*@}*/
01715 
01716 /*!
01717  * @name Register I2S_RCSR, field FRF[16] (RO)
01718  *
01719  * Indicates that the number of words in an enabled receive channel FIFO is
01720  * greater than the receive FIFO watermark.
01721  *
01722  * Values:
01723  * - 0 - Receive FIFO watermark not reached.
01724  * - 1 - Receive FIFO watermark has been reached.
01725  */
01726 /*@{*/
01727 #define BP_I2S_RCSR_FRF      (16U)         /*!< Bit position for I2S_RCSR_FRF. */
01728 #define BM_I2S_RCSR_FRF      (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */
01729 #define BS_I2S_RCSR_FRF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FRF. */
01730 
01731 /*! @brief Read current value of the I2S_RCSR_FRF field. */
01732 #define BR_I2S_RCSR_FRF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF)))
01733 /*@}*/
01734 
01735 /*!
01736  * @name Register I2S_RCSR, field FWF[17] (RO)
01737  *
01738  * Indicates that an enabled receive FIFO is full.
01739  *
01740  * Values:
01741  * - 0 - No enabled receive FIFO is full.
01742  * - 1 - Enabled receive FIFO is full.
01743  */
01744 /*@{*/
01745 #define BP_I2S_RCSR_FWF      (17U)         /*!< Bit position for I2S_RCSR_FWF. */
01746 #define BM_I2S_RCSR_FWF      (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */
01747 #define BS_I2S_RCSR_FWF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FWF. */
01748 
01749 /*! @brief Read current value of the I2S_RCSR_FWF field. */
01750 #define BR_I2S_RCSR_FWF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF)))
01751 /*@}*/
01752 
01753 /*!
01754  * @name Register I2S_RCSR, field FEF[18] (W1C)
01755  *
01756  * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
01757  * this field to clear this flag.
01758  *
01759  * Values:
01760  * - 0 - Receive overflow not detected.
01761  * - 1 - Receive overflow detected.
01762  */
01763 /*@{*/
01764 #define BP_I2S_RCSR_FEF      (18U)         /*!< Bit position for I2S_RCSR_FEF. */
01765 #define BM_I2S_RCSR_FEF      (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */
01766 #define BS_I2S_RCSR_FEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_FEF. */
01767 
01768 /*! @brief Read current value of the I2S_RCSR_FEF field. */
01769 #define BR_I2S_RCSR_FEF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF)))
01770 
01771 /*! @brief Format value for bitfield I2S_RCSR_FEF. */
01772 #define BF_I2S_RCSR_FEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
01773 
01774 /*! @brief Set the FEF field to a new value. */
01775 #define BW_I2S_RCSR_FEF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF), v))
01776 /*@}*/
01777 
01778 /*!
01779  * @name Register I2S_RCSR, field SEF[19] (W1C)
01780  *
01781  * Indicates that an error in the externally-generated frame sync has been
01782  * detected. Write a logic 1 to this field to clear this flag.
01783  *
01784  * Values:
01785  * - 0 - Sync error not detected.
01786  * - 1 - Frame sync error detected.
01787  */
01788 /*@{*/
01789 #define BP_I2S_RCSR_SEF      (19U)         /*!< Bit position for I2S_RCSR_SEF. */
01790 #define BM_I2S_RCSR_SEF      (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */
01791 #define BS_I2S_RCSR_SEF      (1U)          /*!< Bit field size in bits for I2S_RCSR_SEF. */
01792 
01793 /*! @brief Read current value of the I2S_RCSR_SEF field. */
01794 #define BR_I2S_RCSR_SEF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF)))
01795 
01796 /*! @brief Format value for bitfield I2S_RCSR_SEF. */
01797 #define BF_I2S_RCSR_SEF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
01798 
01799 /*! @brief Set the SEF field to a new value. */
01800 #define BW_I2S_RCSR_SEF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF), v))
01801 /*@}*/
01802 
01803 /*!
01804  * @name Register I2S_RCSR, field WSF[20] (W1C)
01805  *
01806  * Indicates that the start of the configured word has been detected. Write a
01807  * logic 1 to this field to clear this flag.
01808  *
01809  * Values:
01810  * - 0 - Start of word not detected.
01811  * - 1 - Start of word detected.
01812  */
01813 /*@{*/
01814 #define BP_I2S_RCSR_WSF      (20U)         /*!< Bit position for I2S_RCSR_WSF. */
01815 #define BM_I2S_RCSR_WSF      (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */
01816 #define BS_I2S_RCSR_WSF      (1U)          /*!< Bit field size in bits for I2S_RCSR_WSF. */
01817 
01818 /*! @brief Read current value of the I2S_RCSR_WSF field. */
01819 #define BR_I2S_RCSR_WSF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF)))
01820 
01821 /*! @brief Format value for bitfield I2S_RCSR_WSF. */
01822 #define BF_I2S_RCSR_WSF(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
01823 
01824 /*! @brief Set the WSF field to a new value. */
01825 #define BW_I2S_RCSR_WSF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF), v))
01826 /*@}*/
01827 
01828 /*!
01829  * @name Register I2S_RCSR, field SR[24] (RW)
01830  *
01831  * Resets the internal receiver logic including the FIFO pointers.
01832  * Software-visible registers are not affected, except for the status registers.
01833  *
01834  * Values:
01835  * - 0 - No effect.
01836  * - 1 - Software reset.
01837  */
01838 /*@{*/
01839 #define BP_I2S_RCSR_SR       (24U)         /*!< Bit position for I2S_RCSR_SR. */
01840 #define BM_I2S_RCSR_SR       (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */
01841 #define BS_I2S_RCSR_SR       (1U)          /*!< Bit field size in bits for I2S_RCSR_SR. */
01842 
01843 /*! @brief Read current value of the I2S_RCSR_SR field. */
01844 #define BR_I2S_RCSR_SR(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR)))
01845 
01846 /*! @brief Format value for bitfield I2S_RCSR_SR. */
01847 #define BF_I2S_RCSR_SR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
01848 
01849 /*! @brief Set the SR field to a new value. */
01850 #define BW_I2S_RCSR_SR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR), v))
01851 /*@}*/
01852 
01853 /*!
01854  * @name Register I2S_RCSR, field FR[25] (WORZ)
01855  *
01856  * Resets the FIFO pointers. Reading this field will always return zero. FIFO
01857  * pointers should only be reset when the receiver is disabled or the FIFO error
01858  * flag is set.
01859  *
01860  * Values:
01861  * - 0 - No effect.
01862  * - 1 - FIFO reset.
01863  */
01864 /*@{*/
01865 #define BP_I2S_RCSR_FR       (25U)         /*!< Bit position for I2S_RCSR_FR. */
01866 #define BM_I2S_RCSR_FR       (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */
01867 #define BS_I2S_RCSR_FR       (1U)          /*!< Bit field size in bits for I2S_RCSR_FR. */
01868 
01869 /*! @brief Format value for bitfield I2S_RCSR_FR. */
01870 #define BF_I2S_RCSR_FR(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
01871 
01872 /*! @brief Set the FR field to a new value. */
01873 #define BW_I2S_RCSR_FR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR), v))
01874 /*@}*/
01875 
01876 /*!
01877  * @name Register I2S_RCSR, field BCE[28] (RW)
01878  *
01879  * Enables the receive bit clock, separately from RE. This field is
01880  * automatically set whenever RE is set. When software clears this field, the receive bit
01881  * clock remains enabled, and this field remains set, until the end of the current
01882  * frame.
01883  *
01884  * Values:
01885  * - 0 - Receive bit clock is disabled.
01886  * - 1 - Receive bit clock is enabled.
01887  */
01888 /*@{*/
01889 #define BP_I2S_RCSR_BCE      (28U)         /*!< Bit position for I2S_RCSR_BCE. */
01890 #define BM_I2S_RCSR_BCE      (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */
01891 #define BS_I2S_RCSR_BCE      (1U)          /*!< Bit field size in bits for I2S_RCSR_BCE. */
01892 
01893 /*! @brief Read current value of the I2S_RCSR_BCE field. */
01894 #define BR_I2S_RCSR_BCE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE)))
01895 
01896 /*! @brief Format value for bitfield I2S_RCSR_BCE. */
01897 #define BF_I2S_RCSR_BCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
01898 
01899 /*! @brief Set the BCE field to a new value. */
01900 #define BW_I2S_RCSR_BCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE), v))
01901 /*@}*/
01902 
01903 /*!
01904  * @name Register I2S_RCSR, field DBGE[29] (RW)
01905  *
01906  * Enables/disables receiver operation in Debug mode. The receive bit clock is
01907  * not affected by Debug mode.
01908  *
01909  * Values:
01910  * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
01911  * - 1 - Receiver is enabled in Debug mode.
01912  */
01913 /*@{*/
01914 #define BP_I2S_RCSR_DBGE     (29U)         /*!< Bit position for I2S_RCSR_DBGE. */
01915 #define BM_I2S_RCSR_DBGE     (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */
01916 #define BS_I2S_RCSR_DBGE     (1U)          /*!< Bit field size in bits for I2S_RCSR_DBGE. */
01917 
01918 /*! @brief Read current value of the I2S_RCSR_DBGE field. */
01919 #define BR_I2S_RCSR_DBGE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE)))
01920 
01921 /*! @brief Format value for bitfield I2S_RCSR_DBGE. */
01922 #define BF_I2S_RCSR_DBGE(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
01923 
01924 /*! @brief Set the DBGE field to a new value. */
01925 #define BW_I2S_RCSR_DBGE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE), v))
01926 /*@}*/
01927 
01928 /*!
01929  * @name Register I2S_RCSR, field STOPE[30] (RW)
01930  *
01931  * Configures receiver operation in Stop mode. This bit is ignored and the
01932  * receiver is disabled in all low-leakage stop modes.
01933  *
01934  * Values:
01935  * - 0 - Receiver disabled in Stop mode.
01936  * - 1 - Receiver enabled in Stop mode.
01937  */
01938 /*@{*/
01939 #define BP_I2S_RCSR_STOPE    (30U)         /*!< Bit position for I2S_RCSR_STOPE. */
01940 #define BM_I2S_RCSR_STOPE    (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */
01941 #define BS_I2S_RCSR_STOPE    (1U)          /*!< Bit field size in bits for I2S_RCSR_STOPE. */
01942 
01943 /*! @brief Read current value of the I2S_RCSR_STOPE field. */
01944 #define BR_I2S_RCSR_STOPE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE)))
01945 
01946 /*! @brief Format value for bitfield I2S_RCSR_STOPE. */
01947 #define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
01948 
01949 /*! @brief Set the STOPE field to a new value. */
01950 #define BW_I2S_RCSR_STOPE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE), v))
01951 /*@}*/
01952 
01953 /*!
01954  * @name Register I2S_RCSR, field RE[31] (RW)
01955  *
01956  * Enables/disables the receiver. When software clears this field, the receiver
01957  * remains enabled, and this bit remains set, until the end of the current frame.
01958  *
01959  * Values:
01960  * - 0 - Receiver is disabled.
01961  * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
01962  *     reached end of frame.
01963  */
01964 /*@{*/
01965 #define BP_I2S_RCSR_RE       (31U)         /*!< Bit position for I2S_RCSR_RE. */
01966 #define BM_I2S_RCSR_RE       (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */
01967 #define BS_I2S_RCSR_RE       (1U)          /*!< Bit field size in bits for I2S_RCSR_RE. */
01968 
01969 /*! @brief Read current value of the I2S_RCSR_RE field. */
01970 #define BR_I2S_RCSR_RE(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE)))
01971 
01972 /*! @brief Format value for bitfield I2S_RCSR_RE. */
01973 #define BF_I2S_RCSR_RE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
01974 
01975 /*! @brief Set the RE field to a new value. */
01976 #define BW_I2S_RCSR_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE), v))
01977 /*@}*/
01978 
01979 /*******************************************************************************
01980  * HW_I2S_RCR1 - SAI Receive Configuration 1 Register
01981  ******************************************************************************/
01982 
01983 /*!
01984  * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
01985  *
01986  * Reset value: 0x00000000U
01987  */
01988 typedef union _hw_i2s_rcr1
01989 {
01990     uint32_t U;
01991     struct _hw_i2s_rcr1_bitfields
01992     {
01993         uint32_t RFW : 3;              /*!< [2:0] Receive FIFO Watermark */
01994         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
01995     } B;
01996 } hw_i2s_rcr1_t;
01997 
01998 /*!
01999  * @name Constants and macros for entire I2S_RCR1 register
02000  */
02001 /*@{*/
02002 #define HW_I2S_RCR1_ADDR(x)      ((x) + 0x84U)
02003 
02004 #define HW_I2S_RCR1(x)           (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
02005 #define HW_I2S_RCR1_RD(x)        (ADDRESS_READ(hw_i2s_rcr1_t, HW_I2S_RCR1_ADDR(x)))
02006 #define HW_I2S_RCR1_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcr1_t, HW_I2S_RCR1_ADDR(x), v))
02007 #define HW_I2S_RCR1_SET(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) |  (v)))
02008 #define HW_I2S_RCR1_CLR(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
02009 #define HW_I2S_RCR1_TOG(x, v)    (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^  (v)))
02010 /*@}*/
02011 
02012 /*
02013  * Constants & macros for individual I2S_RCR1 bitfields
02014  */
02015 
02016 /*!
02017  * @name Register I2S_RCR1, field RFW[2:0] (RW)
02018  *
02019  * Configures the watermark level for all enabled receiver channels.
02020  */
02021 /*@{*/
02022 #define BP_I2S_RCR1_RFW      (0U)          /*!< Bit position for I2S_RCR1_RFW. */
02023 #define BM_I2S_RCR1_RFW      (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */
02024 #define BS_I2S_RCR1_RFW      (3U)          /*!< Bit field size in bits for I2S_RCR1_RFW. */
02025 
02026 /*! @brief Read current value of the I2S_RCR1_RFW field. */
02027 #define BR_I2S_RCR1_RFW(x)   (UNION_READ(hw_i2s_rcr1_t, HW_I2S_RCR1_ADDR(x), U, B.RFW))
02028 
02029 /*! @brief Format value for bitfield I2S_RCR1_RFW. */
02030 #define BF_I2S_RCR1_RFW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
02031 
02032 /*! @brief Set the RFW field to a new value. */
02033 #define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
02034 /*@}*/
02035 
02036 /*******************************************************************************
02037  * HW_I2S_RCR2 - SAI Receive Configuration 2 Register
02038  ******************************************************************************/
02039 
02040 /*!
02041  * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
02042  *
02043  * Reset value: 0x00000000U
02044  *
02045  * This register must not be altered when RCSR[RE] is set.
02046  */
02047 typedef union _hw_i2s_rcr2
02048 {
02049     uint32_t U;
02050     struct _hw_i2s_rcr2_bitfields
02051     {
02052         uint32_t DIV : 8;              /*!< [7:0] Bit Clock Divide */
02053         uint32_t RESERVED0 : 16;       /*!< [23:8]  */
02054         uint32_t BCD : 1;              /*!< [24] Bit Clock Direction */
02055         uint32_t BCP : 1;              /*!< [25] Bit Clock Polarity */
02056         uint32_t MSEL : 2;             /*!< [27:26] MCLK Select */
02057         uint32_t BCI : 1;              /*!< [28] Bit Clock Input */
02058         uint32_t BCS : 1;              /*!< [29] Bit Clock Swap */
02059         uint32_t SYNC : 2;             /*!< [31:30] Synchronous Mode */
02060     } B;
02061 } hw_i2s_rcr2_t;
02062 
02063 /*!
02064  * @name Constants and macros for entire I2S_RCR2 register
02065  */
02066 /*@{*/
02067 #define HW_I2S_RCR2_ADDR(x)      ((x) + 0x88U)
02068 
02069 #define HW_I2S_RCR2(x)           (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
02070 #define HW_I2S_RCR2_RD(x)        (ADDRESS_READ(hw_i2s_rcr2_t, HW_I2S_RCR2_ADDR(x)))
02071 #define HW_I2S_RCR2_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcr2_t, HW_I2S_RCR2_ADDR(x), v))
02072 #define HW_I2S_RCR2_SET(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) |  (v)))
02073 #define HW_I2S_RCR2_CLR(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
02074 #define HW_I2S_RCR2_TOG(x, v)    (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^  (v)))
02075 /*@}*/
02076 
02077 /*
02078  * Constants & macros for individual I2S_RCR2 bitfields
02079  */
02080 
02081 /*!
02082  * @name Register I2S_RCR2, field DIV[7:0] (RW)
02083  *
02084  * Divides down the audio master clock to generate the bit clock when configured
02085  * for an internal bit clock. The division value is (DIV + 1) * 2.
02086  */
02087 /*@{*/
02088 #define BP_I2S_RCR2_DIV      (0U)          /*!< Bit position for I2S_RCR2_DIV. */
02089 #define BM_I2S_RCR2_DIV      (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */
02090 #define BS_I2S_RCR2_DIV      (8U)          /*!< Bit field size in bits for I2S_RCR2_DIV. */
02091 
02092 /*! @brief Read current value of the I2S_RCR2_DIV field. */
02093 #define BR_I2S_RCR2_DIV(x)   (UNION_READ(hw_i2s_rcr2_t, HW_I2S_RCR2_ADDR(x), U, B.DIV))
02094 
02095 /*! @brief Format value for bitfield I2S_RCR2_DIV. */
02096 #define BF_I2S_RCR2_DIV(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
02097 
02098 /*! @brief Set the DIV field to a new value. */
02099 #define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
02100 /*@}*/
02101 
02102 /*!
02103  * @name Register I2S_RCR2, field BCD[24] (RW)
02104  *
02105  * Configures the direction of the bit clock.
02106  *
02107  * Values:
02108  * - 0 - Bit clock is generated externally in Slave mode.
02109  * - 1 - Bit clock is generated internally in Master mode.
02110  */
02111 /*@{*/
02112 #define BP_I2S_RCR2_BCD      (24U)         /*!< Bit position for I2S_RCR2_BCD. */
02113 #define BM_I2S_RCR2_BCD      (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */
02114 #define BS_I2S_RCR2_BCD      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCD. */
02115 
02116 /*! @brief Read current value of the I2S_RCR2_BCD field. */
02117 #define BR_I2S_RCR2_BCD(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD)))
02118 
02119 /*! @brief Format value for bitfield I2S_RCR2_BCD. */
02120 #define BF_I2S_RCR2_BCD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
02121 
02122 /*! @brief Set the BCD field to a new value. */
02123 #define BW_I2S_RCR2_BCD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD), v))
02124 /*@}*/
02125 
02126 /*!
02127  * @name Register I2S_RCR2, field BCP[25] (RW)
02128  *
02129  * Configures the polarity of the bit clock.
02130  *
02131  * Values:
02132  * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
02133  *     inputs on falling edge.
02134  * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
02135  *     inputs on rising edge.
02136  */
02137 /*@{*/
02138 #define BP_I2S_RCR2_BCP      (25U)         /*!< Bit position for I2S_RCR2_BCP. */
02139 #define BM_I2S_RCR2_BCP      (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */
02140 #define BS_I2S_RCR2_BCP      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCP. */
02141 
02142 /*! @brief Read current value of the I2S_RCR2_BCP field. */
02143 #define BR_I2S_RCR2_BCP(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP)))
02144 
02145 /*! @brief Format value for bitfield I2S_RCR2_BCP. */
02146 #define BF_I2S_RCR2_BCP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
02147 
02148 /*! @brief Set the BCP field to a new value. */
02149 #define BW_I2S_RCR2_BCP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP), v))
02150 /*@}*/
02151 
02152 /*!
02153  * @name Register I2S_RCR2, field MSEL[27:26] (RW)
02154  *
02155  * Selects the audio Master Clock option used to generate an internally
02156  * generated bit clock. This field has no effect when configured for an externally
02157  * generated bit clock. Depending on the device, some Master Clock options might not be
02158  * available. See the chip configuration details for the availability and
02159  * chip-specific meaning of each option.
02160  *
02161  * Values:
02162  * - 00 - Bus Clock selected.
02163  * - 01 - Master Clock (MCLK) 1 option selected.
02164  * - 10 - Master Clock (MCLK) 2 option selected.
02165  * - 11 - Master Clock (MCLK) 3 option selected.
02166  */
02167 /*@{*/
02168 #define BP_I2S_RCR2_MSEL     (26U)         /*!< Bit position for I2S_RCR2_MSEL. */
02169 #define BM_I2S_RCR2_MSEL     (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */
02170 #define BS_I2S_RCR2_MSEL     (2U)          /*!< Bit field size in bits for I2S_RCR2_MSEL. */
02171 
02172 /*! @brief Read current value of the I2S_RCR2_MSEL field. */
02173 #define BR_I2S_RCR2_MSEL(x)  (UNION_READ(hw_i2s_rcr2_t, HW_I2S_RCR2_ADDR(x), U, B.MSEL))
02174 
02175 /*! @brief Format value for bitfield I2S_RCR2_MSEL. */
02176 #define BF_I2S_RCR2_MSEL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
02177 
02178 /*! @brief Set the MSEL field to a new value. */
02179 #define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
02180 /*@}*/
02181 
02182 /*!
02183  * @name Register I2S_RCR2, field BCI[28] (RW)
02184  *
02185  * When this field is set and using an internally generated bit clock in either
02186  * synchronous or asynchronous mode, the bit clock actually used by the receiver
02187  * is delayed by the pad output delay (the receiver is clocked by the pad input
02188  * as if the clock was externally generated). This has the effect of decreasing
02189  * the data input setup time, but increasing the data output valid time. The slave
02190  * mode timing from the datasheet should be used for the receiver when this bit
02191  * is set. In synchronous mode, this bit allows the receiver to use the slave mode
02192  * timing from the datasheet, while the transmitter uses the master mode timing.
02193  * This field has no effect when configured for an externally generated bit
02194  * clock or when synchronous to another SAI peripheral .
02195  *
02196  * Values:
02197  * - 0 - No effect.
02198  * - 1 - Internal logic is clocked as if bit clock was externally generated.
02199  */
02200 /*@{*/
02201 #define BP_I2S_RCR2_BCI      (28U)         /*!< Bit position for I2S_RCR2_BCI. */
02202 #define BM_I2S_RCR2_BCI      (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */
02203 #define BS_I2S_RCR2_BCI      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCI. */
02204 
02205 /*! @brief Read current value of the I2S_RCR2_BCI field. */
02206 #define BR_I2S_RCR2_BCI(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI)))
02207 
02208 /*! @brief Format value for bitfield I2S_RCR2_BCI. */
02209 #define BF_I2S_RCR2_BCI(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
02210 
02211 /*! @brief Set the BCI field to a new value. */
02212 #define BW_I2S_RCR2_BCI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI), v))
02213 /*@}*/
02214 
02215 /*!
02216  * @name Register I2S_RCR2, field BCS[29] (RW)
02217  *
02218  * This field swaps the bit clock used by the receiver. When the receiver is
02219  * configured in asynchronous mode and this bit is set, the receiver is clocked by
02220  * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
02221  * receiver to share the same bit clock, but the receiver continues to use the receiver
02222  * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
02223  * mode, the transmitter BCS field and receiver BCS field must be set to the same
02224  * value. When both are set, the transmitter and receiver are both clocked by the
02225  * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
02226  * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
02227  *
02228  * Values:
02229  * - 0 - Use the normal bit clock source.
02230  * - 1 - Swap the bit clock source.
02231  */
02232 /*@{*/
02233 #define BP_I2S_RCR2_BCS      (29U)         /*!< Bit position for I2S_RCR2_BCS. */
02234 #define BM_I2S_RCR2_BCS      (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */
02235 #define BS_I2S_RCR2_BCS      (1U)          /*!< Bit field size in bits for I2S_RCR2_BCS. */
02236 
02237 /*! @brief Read current value of the I2S_RCR2_BCS field. */
02238 #define BR_I2S_RCR2_BCS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS)))
02239 
02240 /*! @brief Format value for bitfield I2S_RCR2_BCS. */
02241 #define BF_I2S_RCR2_BCS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
02242 
02243 /*! @brief Set the BCS field to a new value. */
02244 #define BW_I2S_RCR2_BCS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS), v))
02245 /*@}*/
02246 
02247 /*!
02248  * @name Register I2S_RCR2, field SYNC[31:30] (RW)
02249  *
02250  * Configures between asynchronous and synchronous modes of operation. When
02251  * configured for a synchronous mode of operation, the transmitter or other SAI
02252  * peripheral must be configured for asynchronous operation.
02253  *
02254  * Values:
02255  * - 00 - Asynchronous mode.
02256  * - 01 - Synchronous with transmitter.
02257  * - 10 - Synchronous with another SAI receiver.
02258  * - 11 - Synchronous with another SAI transmitter.
02259  */
02260 /*@{*/
02261 #define BP_I2S_RCR2_SYNC     (30U)         /*!< Bit position for I2S_RCR2_SYNC. */
02262 #define BM_I2S_RCR2_SYNC     (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */
02263 #define BS_I2S_RCR2_SYNC     (2U)          /*!< Bit field size in bits for I2S_RCR2_SYNC. */
02264 
02265 /*! @brief Read current value of the I2S_RCR2_SYNC field. */
02266 #define BR_I2S_RCR2_SYNC(x)  (UNION_READ(hw_i2s_rcr2_t, HW_I2S_RCR2_ADDR(x), U, B.SYNC))
02267 
02268 /*! @brief Format value for bitfield I2S_RCR2_SYNC. */
02269 #define BF_I2S_RCR2_SYNC(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
02270 
02271 /*! @brief Set the SYNC field to a new value. */
02272 #define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
02273 /*@}*/
02274 
02275 /*******************************************************************************
02276  * HW_I2S_RCR3 - SAI Receive Configuration 3 Register
02277  ******************************************************************************/
02278 
02279 /*!
02280  * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
02281  *
02282  * Reset value: 0x00000000U
02283  *
02284  * This register must not be altered when RCSR[RE] is set.
02285  */
02286 typedef union _hw_i2s_rcr3
02287 {
02288     uint32_t U;
02289     struct _hw_i2s_rcr3_bitfields
02290     {
02291         uint32_t WDFL : 5;             /*!< [4:0] Word Flag Configuration */
02292         uint32_t RESERVED0 : 11;       /*!< [15:5]  */
02293         uint32_t RCE : 2;              /*!< [17:16] Receive Channel Enable */
02294         uint32_t RESERVED1 : 14;       /*!< [31:18]  */
02295     } B;
02296 } hw_i2s_rcr3_t;
02297 
02298 /*!
02299  * @name Constants and macros for entire I2S_RCR3 register
02300  */
02301 /*@{*/
02302 #define HW_I2S_RCR3_ADDR(x)      ((x) + 0x8CU)
02303 
02304 #define HW_I2S_RCR3(x)           (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
02305 #define HW_I2S_RCR3_RD(x)        (ADDRESS_READ(hw_i2s_rcr3_t, HW_I2S_RCR3_ADDR(x)))
02306 #define HW_I2S_RCR3_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcr3_t, HW_I2S_RCR3_ADDR(x), v))
02307 #define HW_I2S_RCR3_SET(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) |  (v)))
02308 #define HW_I2S_RCR3_CLR(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
02309 #define HW_I2S_RCR3_TOG(x, v)    (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^  (v)))
02310 /*@}*/
02311 
02312 /*
02313  * Constants & macros for individual I2S_RCR3 bitfields
02314  */
02315 
02316 /*!
02317  * @name Register I2S_RCR3, field WDFL[4:0] (RW)
02318  *
02319  * Configures which word the start of word flag is set. The value written should
02320  * be one less than the word number (for example, write zero to configure for
02321  * the first word in the frame). When configured to a value greater than the Frame
02322  * Size field, then the start of word flag is never set.
02323  */
02324 /*@{*/
02325 #define BP_I2S_RCR3_WDFL     (0U)          /*!< Bit position for I2S_RCR3_WDFL. */
02326 #define BM_I2S_RCR3_WDFL     (0x0000001FU) /*!< Bit mask for I2S_RCR3_WDFL. */
02327 #define BS_I2S_RCR3_WDFL     (5U)          /*!< Bit field size in bits for I2S_RCR3_WDFL. */
02328 
02329 /*! @brief Read current value of the I2S_RCR3_WDFL field. */
02330 #define BR_I2S_RCR3_WDFL(x)  (UNION_READ(hw_i2s_rcr3_t, HW_I2S_RCR3_ADDR(x), U, B.WDFL))
02331 
02332 /*! @brief Format value for bitfield I2S_RCR3_WDFL. */
02333 #define BF_I2S_RCR3_WDFL(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
02334 
02335 /*! @brief Set the WDFL field to a new value. */
02336 #define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
02337 /*@}*/
02338 
02339 /*!
02340  * @name Register I2S_RCR3, field RCE[17:16] (RW)
02341  *
02342  * Enables the corresponding data channel for receive operation. A channel must
02343  * be enabled before its FIFO is accessed.
02344  *
02345  * Values:
02346  * - 0 - Receive data channel N is disabled.
02347  * - 1 - Receive data channel N is enabled.
02348  */
02349 /*@{*/
02350 #define BP_I2S_RCR3_RCE      (16U)         /*!< Bit position for I2S_RCR3_RCE. */
02351 #define BM_I2S_RCR3_RCE      (0x00030000U) /*!< Bit mask for I2S_RCR3_RCE. */
02352 #define BS_I2S_RCR3_RCE      (2U)          /*!< Bit field size in bits for I2S_RCR3_RCE. */
02353 
02354 /*! @brief Read current value of the I2S_RCR3_RCE field. */
02355 #define BR_I2S_RCR3_RCE(x)   (UNION_READ(hw_i2s_rcr3_t, HW_I2S_RCR3_ADDR(x), U, B.RCE))
02356 
02357 /*! @brief Format value for bitfield I2S_RCR3_RCE. */
02358 #define BF_I2S_RCR3_RCE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
02359 
02360 /*! @brief Set the RCE field to a new value. */
02361 #define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
02362 /*@}*/
02363 
02364 /*******************************************************************************
02365  * HW_I2S_RCR4 - SAI Receive Configuration 4 Register
02366  ******************************************************************************/
02367 
02368 /*!
02369  * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
02370  *
02371  * Reset value: 0x00000000U
02372  *
02373  * This register must not be altered when RCSR[RE] is set.
02374  */
02375 typedef union _hw_i2s_rcr4
02376 {
02377     uint32_t U;
02378     struct _hw_i2s_rcr4_bitfields
02379     {
02380         uint32_t FSD : 1;              /*!< [0] Frame Sync Direction */
02381         uint32_t FSP : 1;              /*!< [1] Frame Sync Polarity */
02382         uint32_t RESERVED0 : 1;        /*!< [2]  */
02383         uint32_t FSE : 1;              /*!< [3] Frame Sync Early */
02384         uint32_t MF : 1;               /*!< [4] MSB First */
02385         uint32_t RESERVED1 : 3;        /*!< [7:5]  */
02386         uint32_t SYWD : 5;             /*!< [12:8] Sync Width */
02387         uint32_t RESERVED2 : 3;        /*!< [15:13]  */
02388         uint32_t FRSZ : 5;             /*!< [20:16] Frame Size */
02389         uint32_t RESERVED3 : 11;       /*!< [31:21]  */
02390     } B;
02391 } hw_i2s_rcr4_t;
02392 
02393 /*!
02394  * @name Constants and macros for entire I2S_RCR4 register
02395  */
02396 /*@{*/
02397 #define HW_I2S_RCR4_ADDR(x)      ((x) + 0x90U)
02398 
02399 #define HW_I2S_RCR4(x)           (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
02400 #define HW_I2S_RCR4_RD(x)        (ADDRESS_READ(hw_i2s_rcr4_t, HW_I2S_RCR4_ADDR(x)))
02401 #define HW_I2S_RCR4_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcr4_t, HW_I2S_RCR4_ADDR(x), v))
02402 #define HW_I2S_RCR4_SET(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) |  (v)))
02403 #define HW_I2S_RCR4_CLR(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
02404 #define HW_I2S_RCR4_TOG(x, v)    (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^  (v)))
02405 /*@}*/
02406 
02407 /*
02408  * Constants & macros for individual I2S_RCR4 bitfields
02409  */
02410 
02411 /*!
02412  * @name Register I2S_RCR4, field FSD[0] (RW)
02413  *
02414  * Configures the direction of the frame sync.
02415  *
02416  * Values:
02417  * - 0 - Frame Sync is generated externally in Slave mode.
02418  * - 1 - Frame Sync is generated internally in Master mode.
02419  */
02420 /*@{*/
02421 #define BP_I2S_RCR4_FSD      (0U)          /*!< Bit position for I2S_RCR4_FSD. */
02422 #define BM_I2S_RCR4_FSD      (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */
02423 #define BS_I2S_RCR4_FSD      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSD. */
02424 
02425 /*! @brief Read current value of the I2S_RCR4_FSD field. */
02426 #define BR_I2S_RCR4_FSD(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD)))
02427 
02428 /*! @brief Format value for bitfield I2S_RCR4_FSD. */
02429 #define BF_I2S_RCR4_FSD(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
02430 
02431 /*! @brief Set the FSD field to a new value. */
02432 #define BW_I2S_RCR4_FSD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD), v))
02433 /*@}*/
02434 
02435 /*!
02436  * @name Register I2S_RCR4, field FSP[1] (RW)
02437  *
02438  * Configures the polarity of the frame sync.
02439  *
02440  * Values:
02441  * - 0 - Frame sync is active high.
02442  * - 1 - Frame sync is active low.
02443  */
02444 /*@{*/
02445 #define BP_I2S_RCR4_FSP      (1U)          /*!< Bit position for I2S_RCR4_FSP. */
02446 #define BM_I2S_RCR4_FSP      (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */
02447 #define BS_I2S_RCR4_FSP      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSP. */
02448 
02449 /*! @brief Read current value of the I2S_RCR4_FSP field. */
02450 #define BR_I2S_RCR4_FSP(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP)))
02451 
02452 /*! @brief Format value for bitfield I2S_RCR4_FSP. */
02453 #define BF_I2S_RCR4_FSP(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
02454 
02455 /*! @brief Set the FSP field to a new value. */
02456 #define BW_I2S_RCR4_FSP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP), v))
02457 /*@}*/
02458 
02459 /*!
02460  * @name Register I2S_RCR4, field FSE[3] (RW)
02461  *
02462  * Values:
02463  * - 0 - Frame sync asserts with the first bit of the frame.
02464  * - 1 - Frame sync asserts one bit before the first bit of the frame.
02465  */
02466 /*@{*/
02467 #define BP_I2S_RCR4_FSE      (3U)          /*!< Bit position for I2S_RCR4_FSE. */
02468 #define BM_I2S_RCR4_FSE      (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */
02469 #define BS_I2S_RCR4_FSE      (1U)          /*!< Bit field size in bits for I2S_RCR4_FSE. */
02470 
02471 /*! @brief Read current value of the I2S_RCR4_FSE field. */
02472 #define BR_I2S_RCR4_FSE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE)))
02473 
02474 /*! @brief Format value for bitfield I2S_RCR4_FSE. */
02475 #define BF_I2S_RCR4_FSE(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
02476 
02477 /*! @brief Set the FSE field to a new value. */
02478 #define BW_I2S_RCR4_FSE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE), v))
02479 /*@}*/
02480 
02481 /*!
02482  * @name Register I2S_RCR4, field MF[4] (RW)
02483  *
02484  * Configures whether the LSB or the MSB is received first.
02485  *
02486  * Values:
02487  * - 0 - LSB is received first.
02488  * - 1 - MSB is received first.
02489  */
02490 /*@{*/
02491 #define BP_I2S_RCR4_MF       (4U)          /*!< Bit position for I2S_RCR4_MF. */
02492 #define BM_I2S_RCR4_MF       (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */
02493 #define BS_I2S_RCR4_MF       (1U)          /*!< Bit field size in bits for I2S_RCR4_MF. */
02494 
02495 /*! @brief Read current value of the I2S_RCR4_MF field. */
02496 #define BR_I2S_RCR4_MF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF)))
02497 
02498 /*! @brief Format value for bitfield I2S_RCR4_MF. */
02499 #define BF_I2S_RCR4_MF(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
02500 
02501 /*! @brief Set the MF field to a new value. */
02502 #define BW_I2S_RCR4_MF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF), v))
02503 /*@}*/
02504 
02505 /*!
02506  * @name Register I2S_RCR4, field SYWD[12:8] (RW)
02507  *
02508  * Configures the length of the frame sync in number of bit clocks. The value
02509  * written must be one less than the number of bit clocks. For example, write 0 for
02510  * the frame sync to assert for one bit clock only. The sync width cannot be
02511  * configured longer than the first word of the frame.
02512  */
02513 /*@{*/
02514 #define BP_I2S_RCR4_SYWD     (8U)          /*!< Bit position for I2S_RCR4_SYWD. */
02515 #define BM_I2S_RCR4_SYWD     (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */
02516 #define BS_I2S_RCR4_SYWD     (5U)          /*!< Bit field size in bits for I2S_RCR4_SYWD. */
02517 
02518 /*! @brief Read current value of the I2S_RCR4_SYWD field. */
02519 #define BR_I2S_RCR4_SYWD(x)  (UNION_READ(hw_i2s_rcr4_t, HW_I2S_RCR4_ADDR(x), U, B.SYWD))
02520 
02521 /*! @brief Format value for bitfield I2S_RCR4_SYWD. */
02522 #define BF_I2S_RCR4_SYWD(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
02523 
02524 /*! @brief Set the SYWD field to a new value. */
02525 #define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
02526 /*@}*/
02527 
02528 /*!
02529  * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
02530  *
02531  * Configures the number of words in each frame. The value written must be one
02532  * less than the number of words in the frame. For example, write 0 for one word
02533  * per frame. The maximum supported frame size is 32 words.
02534  */
02535 /*@{*/
02536 #define BP_I2S_RCR4_FRSZ     (16U)         /*!< Bit position for I2S_RCR4_FRSZ. */
02537 #define BM_I2S_RCR4_FRSZ     (0x001F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */
02538 #define BS_I2S_RCR4_FRSZ     (5U)          /*!< Bit field size in bits for I2S_RCR4_FRSZ. */
02539 
02540 /*! @brief Read current value of the I2S_RCR4_FRSZ field. */
02541 #define BR_I2S_RCR4_FRSZ(x)  (UNION_READ(hw_i2s_rcr4_t, HW_I2S_RCR4_ADDR(x), U, B.FRSZ))
02542 
02543 /*! @brief Format value for bitfield I2S_RCR4_FRSZ. */
02544 #define BF_I2S_RCR4_FRSZ(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
02545 
02546 /*! @brief Set the FRSZ field to a new value. */
02547 #define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
02548 /*@}*/
02549 
02550 /*******************************************************************************
02551  * HW_I2S_RCR5 - SAI Receive Configuration 5 Register
02552  ******************************************************************************/
02553 
02554 /*!
02555  * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
02556  *
02557  * Reset value: 0x00000000U
02558  *
02559  * This register must not be altered when RCSR[RE] is set.
02560  */
02561 typedef union _hw_i2s_rcr5
02562 {
02563     uint32_t U;
02564     struct _hw_i2s_rcr5_bitfields
02565     {
02566         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
02567         uint32_t FBT : 5;              /*!< [12:8] First Bit Shifted */
02568         uint32_t RESERVED1 : 3;        /*!< [15:13]  */
02569         uint32_t W0W : 5;              /*!< [20:16] Word 0 Width */
02570         uint32_t RESERVED2 : 3;        /*!< [23:21]  */
02571         uint32_t WNW : 5;              /*!< [28:24] Word N Width */
02572         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02573     } B;
02574 } hw_i2s_rcr5_t;
02575 
02576 /*!
02577  * @name Constants and macros for entire I2S_RCR5 register
02578  */
02579 /*@{*/
02580 #define HW_I2S_RCR5_ADDR(x)      ((x) + 0x94U)
02581 
02582 #define HW_I2S_RCR5(x)           (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
02583 #define HW_I2S_RCR5_RD(x)        (ADDRESS_READ(hw_i2s_rcr5_t, HW_I2S_RCR5_ADDR(x)))
02584 #define HW_I2S_RCR5_WR(x, v)     (ADDRESS_WRITE(hw_i2s_rcr5_t, HW_I2S_RCR5_ADDR(x), v))
02585 #define HW_I2S_RCR5_SET(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) |  (v)))
02586 #define HW_I2S_RCR5_CLR(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
02587 #define HW_I2S_RCR5_TOG(x, v)    (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^  (v)))
02588 /*@}*/
02589 
02590 /*
02591  * Constants & macros for individual I2S_RCR5 bitfields
02592  */
02593 
02594 /*!
02595  * @name Register I2S_RCR5, field FBT[12:8] (RW)
02596  *
02597  * Configures the bit index for the first bit received for each word in the
02598  * frame. If configured for MSB First, the index of the next bit received is one less
02599  * than the current bit received. If configured for LSB First, the index of the
02600  * next bit received is one more than the current bit received. The value written
02601  * must be greater than or equal to the word width when configured for MSB
02602  * First. The value written must be less than or equal to 31-word width when
02603  * configured for LSB First.
02604  */
02605 /*@{*/
02606 #define BP_I2S_RCR5_FBT      (8U)          /*!< Bit position for I2S_RCR5_FBT. */
02607 #define BM_I2S_RCR5_FBT      (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */
02608 #define BS_I2S_RCR5_FBT      (5U)          /*!< Bit field size in bits for I2S_RCR5_FBT. */
02609 
02610 /*! @brief Read current value of the I2S_RCR5_FBT field. */
02611 #define BR_I2S_RCR5_FBT(x)   (UNION_READ(hw_i2s_rcr5_t, HW_I2S_RCR5_ADDR(x), U, B.FBT))
02612 
02613 /*! @brief Format value for bitfield I2S_RCR5_FBT. */
02614 #define BF_I2S_RCR5_FBT(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
02615 
02616 /*! @brief Set the FBT field to a new value. */
02617 #define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
02618 /*@}*/
02619 
02620 /*!
02621  * @name Register I2S_RCR5, field W0W[20:16] (RW)
02622  *
02623  * Configures the number of bits in the first word in each frame. The value
02624  * written must be one less than the number of bits in the first word. Word width of
02625  * less than 8 bits is not supported if there is only one word per frame.
02626  */
02627 /*@{*/
02628 #define BP_I2S_RCR5_W0W      (16U)         /*!< Bit position for I2S_RCR5_W0W. */
02629 #define BM_I2S_RCR5_W0W      (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */
02630 #define BS_I2S_RCR5_W0W      (5U)          /*!< Bit field size in bits for I2S_RCR5_W0W. */
02631 
02632 /*! @brief Read current value of the I2S_RCR5_W0W field. */
02633 #define BR_I2S_RCR5_W0W(x)   (UNION_READ(hw_i2s_rcr5_t, HW_I2S_RCR5_ADDR(x), U, B.W0W))
02634 
02635 /*! @brief Format value for bitfield I2S_RCR5_W0W. */
02636 #define BF_I2S_RCR5_W0W(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
02637 
02638 /*! @brief Set the W0W field to a new value. */
02639 #define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
02640 /*@}*/
02641 
02642 /*!
02643  * @name Register I2S_RCR5, field WNW[28:24] (RW)
02644  *
02645  * Configures the number of bits in each word, for each word except the first in
02646  * the frame. The value written must be one less than the number of bits per
02647  * word. Word width of less than 8 bits is not supported.
02648  */
02649 /*@{*/
02650 #define BP_I2S_RCR5_WNW      (24U)         /*!< Bit position for I2S_RCR5_WNW. */
02651 #define BM_I2S_RCR5_WNW      (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */
02652 #define BS_I2S_RCR5_WNW      (5U)          /*!< Bit field size in bits for I2S_RCR5_WNW. */
02653 
02654 /*! @brief Read current value of the I2S_RCR5_WNW field. */
02655 #define BR_I2S_RCR5_WNW(x)   (UNION_READ(hw_i2s_rcr5_t, HW_I2S_RCR5_ADDR(x), U, B.WNW))
02656 
02657 /*! @brief Format value for bitfield I2S_RCR5_WNW. */
02658 #define BF_I2S_RCR5_WNW(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
02659 
02660 /*! @brief Set the WNW field to a new value. */
02661 #define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
02662 /*@}*/
02663 
02664 /*******************************************************************************
02665  * HW_I2S_RDRn - SAI Receive Data Register
02666  ******************************************************************************/
02667 
02668 /*!
02669  * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
02670  *
02671  * Reset value: 0x00000000U
02672  *
02673  * Reading this register introduces one additional peripheral clock wait state
02674  * on each read.
02675  */
02676 typedef union _hw_i2s_rdrn
02677 {
02678     uint32_t U;
02679     struct _hw_i2s_rdrn_bitfields
02680     {
02681         uint32_t RDR : 32;             /*!< [31:0] Receive Data Register */
02682     } B;
02683 } hw_i2s_rdrn_t;
02684 
02685 /*!
02686  * @name Constants and macros for entire I2S_RDRn register
02687  */
02688 /*@{*/
02689 #define HW_I2S_RDRn_COUNT (2U)
02690 
02691 #define HW_I2S_RDRn_ADDR(x, n)   ((x) + 0xA0U + (0x4U * (n)))
02692 
02693 #define HW_I2S_RDRn(x, n)        (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
02694 #define HW_I2S_RDRn_RD(x, n)     (ADDRESS_READ(hw_i2s_rdrn_t, HW_I2S_RDRn_ADDR(x, n)))
02695 /*@}*/
02696 
02697 /*
02698  * Constants & macros for individual I2S_RDRn bitfields
02699  */
02700 
02701 /*!
02702  * @name Register I2S_RDRn, field RDR[31:0] (RO)
02703  *
02704  * The corresponding RCR3[RCE] bit must be set before accessing the channel's
02705  * receive data register. Reads from this register when the receive FIFO is not
02706  * empty will return the data from the top of the receive FIFO. Reads from this
02707  * register when the receive FIFO is empty are ignored.
02708  */
02709 /*@{*/
02710 #define BP_I2S_RDRn_RDR      (0U)          /*!< Bit position for I2S_RDRn_RDR. */
02711 #define BM_I2S_RDRn_RDR      (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */
02712 #define BS_I2S_RDRn_RDR      (32U)         /*!< Bit field size in bits for I2S_RDRn_RDR. */
02713 
02714 /*! @brief Read current value of the I2S_RDRn_RDR field. */
02715 #define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
02716 /*@}*/
02717 
02718 /*******************************************************************************
02719  * HW_I2S_RFRn - SAI Receive FIFO Register
02720  ******************************************************************************/
02721 
02722 /*!
02723  * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
02724  *
02725  * Reset value: 0x00000000U
02726  *
02727  * The MSB of the read and write pointers is used to distinguish between FIFO
02728  * full and empty conditions. If the read and write pointers are identical, then
02729  * the FIFO is empty. If the read and write pointers are identical except for the
02730  * MSB, then the FIFO is full.
02731  */
02732 typedef union _hw_i2s_rfrn
02733 {
02734     uint32_t U;
02735     struct _hw_i2s_rfrn_bitfields
02736     {
02737         uint32_t RFP : 4;              /*!< [3:0] Read FIFO Pointer */
02738         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
02739         uint32_t WFP : 4;              /*!< [19:16] Write FIFO Pointer */
02740         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
02741     } B;
02742 } hw_i2s_rfrn_t;
02743 
02744 /*!
02745  * @name Constants and macros for entire I2S_RFRn register
02746  */
02747 /*@{*/
02748 #define HW_I2S_RFRn_COUNT (2U)
02749 
02750 #define HW_I2S_RFRn_ADDR(x, n)   ((x) + 0xC0U + (0x4U * (n)))
02751 
02752 #define HW_I2S_RFRn(x, n)        (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
02753 #define HW_I2S_RFRn_RD(x, n)     (ADDRESS_READ(hw_i2s_rfrn_t, HW_I2S_RFRn_ADDR(x, n)))
02754 /*@}*/
02755 
02756 /*
02757  * Constants & macros for individual I2S_RFRn bitfields
02758  */
02759 
02760 /*!
02761  * @name Register I2S_RFRn, field RFP[3:0] (RO)
02762  *
02763  * FIFO read pointer for receive data channel.
02764  */
02765 /*@{*/
02766 #define BP_I2S_RFRn_RFP      (0U)          /*!< Bit position for I2S_RFRn_RFP. */
02767 #define BM_I2S_RFRn_RFP      (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */
02768 #define BS_I2S_RFRn_RFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_RFP. */
02769 
02770 /*! @brief Read current value of the I2S_RFRn_RFP field. */
02771 #define BR_I2S_RFRn_RFP(x, n) (UNION_READ(hw_i2s_rfrn_t, HW_I2S_RFRn_ADDR(x, n), U, B.RFP))
02772 /*@}*/
02773 
02774 /*!
02775  * @name Register I2S_RFRn, field WFP[19:16] (RO)
02776  *
02777  * FIFO write pointer for receive data channel.
02778  */
02779 /*@{*/
02780 #define BP_I2S_RFRn_WFP      (16U)         /*!< Bit position for I2S_RFRn_WFP. */
02781 #define BM_I2S_RFRn_WFP      (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */
02782 #define BS_I2S_RFRn_WFP      (4U)          /*!< Bit field size in bits for I2S_RFRn_WFP. */
02783 
02784 /*! @brief Read current value of the I2S_RFRn_WFP field. */
02785 #define BR_I2S_RFRn_WFP(x, n) (UNION_READ(hw_i2s_rfrn_t, HW_I2S_RFRn_ADDR(x, n), U, B.WFP))
02786 /*@}*/
02787 
02788 /*******************************************************************************
02789  * HW_I2S_RMR - SAI Receive Mask Register
02790  ******************************************************************************/
02791 
02792 /*!
02793  * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
02794  *
02795  * Reset value: 0x00000000U
02796  *
02797  * This register is double-buffered and updates: When RCSR[RE] is first set At
02798  * the end of each frame This allows the masked words in each frame to change from
02799  * frame to frame.
02800  */
02801 typedef union _hw_i2s_rmr
02802 {
02803     uint32_t U;
02804     struct _hw_i2s_rmr_bitfields
02805     {
02806         uint32_t RWM : 32;             /*!< [31:0] Receive Word Mask */
02807     } B;
02808 } hw_i2s_rmr_t;
02809 
02810 /*!
02811  * @name Constants and macros for entire I2S_RMR register
02812  */
02813 /*@{*/
02814 #define HW_I2S_RMR_ADDR(x)       ((x) + 0xE0U)
02815 
02816 #define HW_I2S_RMR(x)            (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
02817 #define HW_I2S_RMR_RD(x)         (ADDRESS_READ(hw_i2s_rmr_t, HW_I2S_RMR_ADDR(x)))
02818 #define HW_I2S_RMR_WR(x, v)      (ADDRESS_WRITE(hw_i2s_rmr_t, HW_I2S_RMR_ADDR(x), v))
02819 #define HW_I2S_RMR_SET(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) |  (v)))
02820 #define HW_I2S_RMR_CLR(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
02821 #define HW_I2S_RMR_TOG(x, v)     (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^  (v)))
02822 /*@}*/
02823 
02824 /*
02825  * Constants & macros for individual I2S_RMR bitfields
02826  */
02827 
02828 /*!
02829  * @name Register I2S_RMR, field RWM[31:0] (RW)
02830  *
02831  * Configures whether the receive word is masked (received data ignored and not
02832  * written to receive FIFO) for the corresponding word in the frame.
02833  *
02834  * Values:
02835  * - 0 - Word N is enabled.
02836  * - 1 - Word N is masked.
02837  */
02838 /*@{*/
02839 #define BP_I2S_RMR_RWM       (0U)          /*!< Bit position for I2S_RMR_RWM. */
02840 #define BM_I2S_RMR_RWM       (0xFFFFFFFFU) /*!< Bit mask for I2S_RMR_RWM. */
02841 #define BS_I2S_RMR_RWM       (32U)         /*!< Bit field size in bits for I2S_RMR_RWM. */
02842 
02843 /*! @brief Read current value of the I2S_RMR_RWM field. */
02844 #define BR_I2S_RMR_RWM(x)    (HW_I2S_RMR(x).U)
02845 
02846 /*! @brief Format value for bitfield I2S_RMR_RWM. */
02847 #define BF_I2S_RMR_RWM(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
02848 
02849 /*! @brief Set the RWM field to a new value. */
02850 #define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
02851 /*@}*/
02852 
02853 /*******************************************************************************
02854  * HW_I2S_MCR - SAI MCLK Control Register
02855  ******************************************************************************/
02856 
02857 /*!
02858  * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
02859  *
02860  * Reset value: 0x00000000U
02861  *
02862  * The MCLK Control Register (MCR) controls the clock source and direction of
02863  * the audio master clock.
02864  */
02865 typedef union _hw_i2s_mcr
02866 {
02867     uint32_t U;
02868     struct _hw_i2s_mcr_bitfields
02869     {
02870         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
02871         uint32_t MICS : 2;             /*!< [25:24] MCLK Input Clock Select */
02872         uint32_t RESERVED1 : 4;        /*!< [29:26]  */
02873         uint32_t MOE : 1;              /*!< [30] MCLK Output Enable */
02874         uint32_t DUF : 1;              /*!< [31] Divider Update Flag */
02875     } B;
02876 } hw_i2s_mcr_t;
02877 
02878 /*!
02879  * @name Constants and macros for entire I2S_MCR register
02880  */
02881 /*@{*/
02882 #define HW_I2S_MCR_ADDR(x)       ((x) + 0x100U)
02883 
02884 #define HW_I2S_MCR(x)            (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
02885 #define HW_I2S_MCR_RD(x)         (ADDRESS_READ(hw_i2s_mcr_t, HW_I2S_MCR_ADDR(x)))
02886 #define HW_I2S_MCR_WR(x, v)      (ADDRESS_WRITE(hw_i2s_mcr_t, HW_I2S_MCR_ADDR(x), v))
02887 #define HW_I2S_MCR_SET(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) |  (v)))
02888 #define HW_I2S_MCR_CLR(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
02889 #define HW_I2S_MCR_TOG(x, v)     (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^  (v)))
02890 /*@}*/
02891 
02892 /*
02893  * Constants & macros for individual I2S_MCR bitfields
02894  */
02895 
02896 /*!
02897  * @name Register I2S_MCR, field MICS[25:24] (RW)
02898  *
02899  * Selects the clock input to the MCLK divider. This field cannot be changed
02900  * while the MCLK divider is enabled. See the chip configuration details for
02901  * information about the connections to these inputs.
02902  *
02903  * Values:
02904  * - 00 - MCLK divider input clock 0 selected.
02905  * - 01 - MCLK divider input clock 1 selected.
02906  * - 10 - MCLK divider input clock 2 selected.
02907  * - 11 - MCLK divider input clock 3 selected.
02908  */
02909 /*@{*/
02910 #define BP_I2S_MCR_MICS      (24U)         /*!< Bit position for I2S_MCR_MICS. */
02911 #define BM_I2S_MCR_MICS      (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */
02912 #define BS_I2S_MCR_MICS      (2U)          /*!< Bit field size in bits for I2S_MCR_MICS. */
02913 
02914 /*! @brief Read current value of the I2S_MCR_MICS field. */
02915 #define BR_I2S_MCR_MICS(x)   (UNION_READ(hw_i2s_mcr_t, HW_I2S_MCR_ADDR(x), U, B.MICS))
02916 
02917 /*! @brief Format value for bitfield I2S_MCR_MICS. */
02918 #define BF_I2S_MCR_MICS(v)   ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
02919 
02920 /*! @brief Set the MICS field to a new value. */
02921 #define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
02922 /*@}*/
02923 
02924 /*!
02925  * @name Register I2S_MCR, field MOE[30] (RW)
02926  *
02927  * Enables the MCLK divider and configures the MCLK signal pin as an output.
02928  * When software clears this field, it remains set until the MCLK divider is fully
02929  * disabled.
02930  *
02931  * Values:
02932  * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
02933  *     divider.
02934  * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
02935  *     the MCLK divider is enabled.
02936  */
02937 /*@{*/
02938 #define BP_I2S_MCR_MOE       (30U)         /*!< Bit position for I2S_MCR_MOE. */
02939 #define BM_I2S_MCR_MOE       (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */
02940 #define BS_I2S_MCR_MOE       (1U)          /*!< Bit field size in bits for I2S_MCR_MOE. */
02941 
02942 /*! @brief Read current value of the I2S_MCR_MOE field. */
02943 #define BR_I2S_MCR_MOE(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE)))
02944 
02945 /*! @brief Format value for bitfield I2S_MCR_MOE. */
02946 #define BF_I2S_MCR_MOE(v)    ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
02947 
02948 /*! @brief Set the MOE field to a new value. */
02949 #define BW_I2S_MCR_MOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE), v))
02950 /*@}*/
02951 
02952 /*!
02953  * @name Register I2S_MCR, field DUF[31] (RO)
02954  *
02955  * Provides the status of on-the-fly updates to the MCLK divider ratio.
02956  *
02957  * Values:
02958  * - 0 - MCLK divider ratio is not being updated currently.
02959  * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
02960  *     divider ratio are blocked while this flag remains set.
02961  */
02962 /*@{*/
02963 #define BP_I2S_MCR_DUF       (31U)         /*!< Bit position for I2S_MCR_DUF. */
02964 #define BM_I2S_MCR_DUF       (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */
02965 #define BS_I2S_MCR_DUF       (1U)          /*!< Bit field size in bits for I2S_MCR_DUF. */
02966 
02967 /*! @brief Read current value of the I2S_MCR_DUF field. */
02968 #define BR_I2S_MCR_DUF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF)))
02969 /*@}*/
02970 
02971 /*******************************************************************************
02972  * HW_I2S_MDR - SAI MCLK Divide Register
02973  ******************************************************************************/
02974 
02975 /*!
02976  * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
02977  *
02978  * Reset value: 0x00000000U
02979  *
02980  * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
02981  * MDR can be changed when the MCLK divider clock is enabled, additional writes
02982  * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
02983  * divided clock is disabled do not set MCR[DUF].
02984  */
02985 typedef union _hw_i2s_mdr
02986 {
02987     uint32_t U;
02988     struct _hw_i2s_mdr_bitfields
02989     {
02990         uint32_t DIVIDE : 12;          /*!< [11:0] MCLK Divide */
02991         uint32_t FRACT : 8;            /*!< [19:12] MCLK Fraction */
02992         uint32_t RESERVED0 : 12;       /*!< [31:20]  */
02993     } B;
02994 } hw_i2s_mdr_t;
02995 
02996 /*!
02997  * @name Constants and macros for entire I2S_MDR register
02998  */
02999 /*@{*/
03000 #define HW_I2S_MDR_ADDR(x)       ((x) + 0x104U)
03001 
03002 #define HW_I2S_MDR(x)            (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
03003 #define HW_I2S_MDR_RD(x)         (ADDRESS_READ(hw_i2s_mdr_t, HW_I2S_MDR_ADDR(x)))
03004 #define HW_I2S_MDR_WR(x, v)      (ADDRESS_WRITE(hw_i2s_mdr_t, HW_I2S_MDR_ADDR(x), v))
03005 #define HW_I2S_MDR_SET(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) |  (v)))
03006 #define HW_I2S_MDR_CLR(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
03007 #define HW_I2S_MDR_TOG(x, v)     (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^  (v)))
03008 /*@}*/
03009 
03010 /*
03011  * Constants & macros for individual I2S_MDR bitfields
03012  */
03013 
03014 /*!
03015  * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
03016  *
03017  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
03018  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
03019  * DIVIDE field.
03020  */
03021 /*@{*/
03022 #define BP_I2S_MDR_DIVIDE    (0U)          /*!< Bit position for I2S_MDR_DIVIDE. */
03023 #define BM_I2S_MDR_DIVIDE    (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */
03024 #define BS_I2S_MDR_DIVIDE    (12U)         /*!< Bit field size in bits for I2S_MDR_DIVIDE. */
03025 
03026 /*! @brief Read current value of the I2S_MDR_DIVIDE field. */
03027 #define BR_I2S_MDR_DIVIDE(x) (UNION_READ(hw_i2s_mdr_t, HW_I2S_MDR_ADDR(x), U, B.DIVIDE))
03028 
03029 /*! @brief Format value for bitfield I2S_MDR_DIVIDE. */
03030 #define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
03031 
03032 /*! @brief Set the DIVIDE field to a new value. */
03033 #define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
03034 /*@}*/
03035 
03036 /*!
03037  * @name Register I2S_MDR, field FRACT[19:12] (RW)
03038  *
03039  * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
03040  * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
03041  * DIVIDE field.
03042  */
03043 /*@{*/
03044 #define BP_I2S_MDR_FRACT     (12U)         /*!< Bit position for I2S_MDR_FRACT. */
03045 #define BM_I2S_MDR_FRACT     (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */
03046 #define BS_I2S_MDR_FRACT     (8U)          /*!< Bit field size in bits for I2S_MDR_FRACT. */
03047 
03048 /*! @brief Read current value of the I2S_MDR_FRACT field. */
03049 #define BR_I2S_MDR_FRACT(x)  (UNION_READ(hw_i2s_mdr_t, HW_I2S_MDR_ADDR(x), U, B.FRACT))
03050 
03051 /*! @brief Format value for bitfield I2S_MDR_FRACT. */
03052 #define BF_I2S_MDR_FRACT(v)  ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
03053 
03054 /*! @brief Set the FRACT field to a new value. */
03055 #define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
03056 /*@}*/
03057 
03058 /*******************************************************************************
03059  * hw_i2s_t - module struct
03060  ******************************************************************************/
03061 /*!
03062  * @brief All I2S module registers.
03063  */
03064 #pragma pack(1)
03065 typedef struct _hw_i2s
03066 {
03067     __IO hw_i2s_tcsr_t TCSR ;               /*!< [0x0] SAI Transmit Control Register */
03068     __IO hw_i2s_tcr1_t TCR1 ;               /*!< [0x4] SAI Transmit Configuration 1 Register */
03069     __IO hw_i2s_tcr2_t TCR2 ;               /*!< [0x8] SAI Transmit Configuration 2 Register */
03070     __IO hw_i2s_tcr3_t TCR3 ;               /*!< [0xC] SAI Transmit Configuration 3 Register */
03071     __IO hw_i2s_tcr4_t TCR4 ;               /*!< [0x10] SAI Transmit Configuration 4 Register */
03072     __IO hw_i2s_tcr5_t TCR5 ;               /*!< [0x14] SAI Transmit Configuration 5 Register */
03073     uint8_t _reserved0[8];
03074     __O hw_i2s_tdrn_t TDRn [2];             /*!< [0x20] SAI Transmit Data Register */
03075     uint8_t _reserved1[24];
03076     __I hw_i2s_tfrn_t TFRn [2];             /*!< [0x40] SAI Transmit FIFO Register */
03077     uint8_t _reserved2[24];
03078     __IO hw_i2s_tmr_t TMR ;                 /*!< [0x60] SAI Transmit Mask Register */
03079     uint8_t _reserved3[28];
03080     __IO hw_i2s_rcsr_t RCSR ;               /*!< [0x80] SAI Receive Control Register */
03081     __IO hw_i2s_rcr1_t RCR1 ;               /*!< [0x84] SAI Receive Configuration 1 Register */
03082     __IO hw_i2s_rcr2_t RCR2 ;               /*!< [0x88] SAI Receive Configuration 2 Register */
03083     __IO hw_i2s_rcr3_t RCR3 ;               /*!< [0x8C] SAI Receive Configuration 3 Register */
03084     __IO hw_i2s_rcr4_t RCR4 ;               /*!< [0x90] SAI Receive Configuration 4 Register */
03085     __IO hw_i2s_rcr5_t RCR5 ;               /*!< [0x94] SAI Receive Configuration 5 Register */
03086     uint8_t _reserved4[8];
03087     __I hw_i2s_rdrn_t RDRn [2];             /*!< [0xA0] SAI Receive Data Register */
03088     uint8_t _reserved5[24];
03089     __I hw_i2s_rfrn_t RFRn [2];             /*!< [0xC0] SAI Receive FIFO Register */
03090     uint8_t _reserved6[24];
03091     __IO hw_i2s_rmr_t RMR ;                 /*!< [0xE0] SAI Receive Mask Register */
03092     uint8_t _reserved7[28];
03093     __IO hw_i2s_mcr_t MCR ;                 /*!< [0x100] SAI MCLK Control Register */
03094     __IO hw_i2s_mdr_t MDR ;                 /*!< [0x104] SAI MCLK Divide Register */
03095 } hw_i2s_t;
03096 #pragma pack()
03097 
03098 /*! @brief Macro to access all I2S registers. */
03099 /*! @param x I2S module instance base address. */
03100 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
03101  *     use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
03102 #define HW_I2S(x)      (*(hw_i2s_t *)(x))
03103 
03104 #endif /* __HW_I2S_REGISTERS_H__ */
03105 /* EOF */