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_hw_dmamux_chcfgn Union Reference
HW_DMAMUX_CHCFGn - Channel Configuration register (RW) More...
#include <MK64F12_dmamux.h>
Detailed Description
HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
Reset value: 0x00U
Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL].
Definition at line 122 of file MK64F12_dmamux.h.
Generated on Sat Aug 27 2022 17:09:02 by
1.7.2