MK64F12_dmamux.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_DMAMUX_REGISTERS_H__
00088 #define __HW_DMAMUX_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 DMAMUX
00095  *
00096  * DMA channel multiplexor
00097  *
00098  * Registers defined in this header file:
00099  * - HW_DMAMUX_CHCFGn - Channel Configuration register
00100  *
00101  * - hw_dmamux_t - Struct containing all module registers.
00102  */
00103 
00104 #define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
00105 
00106 /*******************************************************************************
00107  * HW_DMAMUX_CHCFGn - Channel Configuration register
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
00112  *
00113  * Reset value: 0x00U
00114  *
00115  * Each of the DMA channels can be independently enabled/disabled and associated
00116  * with one of the DMA slots (peripheral slots or always-on slots) in the
00117  * system. Setting multiple CHCFG registers with the same source value will result in
00118  * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
00119  * Before changing the trigger or source settings, a DMA channel must be disabled
00120  * via CHCFGn[ENBL].
00121  */
00122 typedef union _hw_dmamux_chcfgn
00123 {
00124     uint8_t U;
00125     struct _hw_dmamux_chcfgn_bitfields
00126     {
00127         uint8_t SOURCE : 6;            /*!< [5:0] DMA Channel Source (Slot) */
00128         uint8_t TRIG : 1;              /*!< [6] DMA Channel Trigger Enable */
00129         uint8_t ENBL : 1;              /*!< [7] DMA Channel Enable */
00130     } B;
00131 } hw_dmamux_chcfgn_t;
00132 
00133 /*!
00134  * @name Constants and macros for entire DMAMUX_CHCFGn register
00135  */
00136 /*@{*/
00137 #define HW_DMAMUX_CHCFGn_COUNT (16U)
00138 
00139 #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
00140 
00141 #define HW_DMAMUX_CHCFGn(x, n)   (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
00142 #define HW_DMAMUX_CHCFGn_RD(x, n) (ADDRESS_READ(hw_dmamux_chcfgn_t, HW_DMAMUX_CHCFGn_ADDR(x, n)))
00143 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (ADDRESS_WRITE(hw_dmamux_chcfgn_t, HW_DMAMUX_CHCFGn_ADDR(x, n), v))
00144 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) |  (v)))
00145 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
00146 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^  (v)))
00147 /*@}*/
00148 
00149 /*
00150  * Constants & macros for individual DMAMUX_CHCFGn bitfields
00151  */
00152 
00153 /*!
00154  * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
00155  *
00156  * Specifies which DMA source, if any, is routed to a particular DMA channel.
00157  * See your device's chip configuration details for information about the
00158  * peripherals and their slot numbers.
00159  */
00160 /*@{*/
00161 #define BP_DMAMUX_CHCFGn_SOURCE (0U)       /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
00162 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU)    /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
00163 #define BS_DMAMUX_CHCFGn_SOURCE (6U)       /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
00164 
00165 /*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
00166 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (UNION_READ(hw_dmamux_chcfgn_t, HW_DMAMUX_CHCFGn_ADDR(x, n), U, B.SOURCE))
00167 
00168 /*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
00169 #define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
00170 
00171 /*! @brief Set the SOURCE field to a new value. */
00172 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
00173 /*@}*/
00174 
00175 /*!
00176  * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
00177  *
00178  * Enables the periodic trigger capability for the triggered DMA channel.
00179  *
00180  * Values:
00181  * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
00182  *     DMA Channel will simply route the specified source to the DMA channel.
00183  *     (Normal mode)
00184  * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
00185  *     DMAMUX is in Periodic Trigger mode.
00186  */
00187 /*@{*/
00188 #define BP_DMAMUX_CHCFGn_TRIG (6U)         /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
00189 #define BM_DMAMUX_CHCFGn_TRIG (0x40U)      /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
00190 #define BS_DMAMUX_CHCFGn_TRIG (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
00191 
00192 /*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
00193 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG)))
00194 
00195 /*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
00196 #define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
00197 
00198 /*! @brief Set the TRIG field to a new value. */
00199 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG), v))
00200 /*@}*/
00201 
00202 /*!
00203  * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
00204  *
00205  * Enables the DMA channel.
00206  *
00207  * Values:
00208  * - 0 - DMA channel is disabled. This mode is primarily used during
00209  *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
00210  *     should be used to disable or reconfigure a DMA channel.
00211  * - 1 - DMA channel is enabled
00212  */
00213 /*@{*/
00214 #define BP_DMAMUX_CHCFGn_ENBL (7U)         /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
00215 #define BM_DMAMUX_CHCFGn_ENBL (0x80U)      /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
00216 #define BS_DMAMUX_CHCFGn_ENBL (1U)         /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
00217 
00218 /*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
00219 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL)))
00220 
00221 /*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
00222 #define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
00223 
00224 /*! @brief Set the ENBL field to a new value. */
00225 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL), v))
00226 /*@}*/
00227 
00228 /*******************************************************************************
00229  * hw_dmamux_t - module struct
00230  ******************************************************************************/
00231 /*!
00232  * @brief All DMAMUX module registers.
00233  */
00234 #pragma pack(1)
00235 typedef struct _hw_dmamux
00236 {
00237     __IO hw_dmamux_chcfgn_t CHCFGn [16];    /*!< [0x0] Channel Configuration register */
00238 } hw_dmamux_t;
00239 #pragma pack()
00240 
00241 /*! @brief Macro to access all DMAMUX registers. */
00242 /*! @param x DMAMUX module instance base address. */
00243 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00244  *     use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
00245 #define HW_DMAMUX(x)   (*(hw_dmamux_t *)(x))
00246 
00247 #endif /* __HW_DMAMUX_REGISTERS_H__ */
00248 /* EOF */