MK64F12_spi.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_SPI_REGISTERS_H__
00088 #define __HW_SPI_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 SPI
00095  *
00096  * Serial Peripheral Interface
00097  *
00098  * Registers defined in this header file:
00099  * - HW_SPI_MCR - Module Configuration Register
00100  * - HW_SPI_TCR - Transfer Count Register
00101  * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
00102  * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
00103  * - HW_SPI_SR - Status Register
00104  * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
00105  * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
00106  * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
00107  * - HW_SPI_POPR - POP RX FIFO Register
00108  * - HW_SPI_TXFRn - Transmit FIFO Registers
00109  * - HW_SPI_RXFRn - Receive FIFO Registers
00110  *
00111  * - hw_spi_t - Struct containing all module registers.
00112  */
00113 
00114 #define HW_SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
00115 #define HW_SPI0 (0U) /*!< Instance number for SPI0. */
00116 #define HW_SPI1 (1U) /*!< Instance number for SPI1. */
00117 #define HW_SPI2 (2U) /*!< Instance number for SPI2. */
00118 
00119 /*******************************************************************************
00120  * HW_SPI_MCR - Module Configuration Register
00121  ******************************************************************************/
00122 
00123 /*!
00124  * @brief HW_SPI_MCR - Module Configuration Register (RW)
00125  *
00126  * Reset value: 0x00004001U
00127  *
00128  * Contains bits to configure various attributes associated with the module
00129  * operations. The HALT and MDIS bits can be changed at any time, but the effect
00130  * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
00131  * MCR can be changed, while the module is in the Running state.
00132  */
00133 typedef union _hw_spi_mcr
00134 {
00135     uint32_t U;
00136     struct _hw_spi_mcr_bitfields
00137     {
00138         uint32_t HALT : 1;             /*!< [0] Halt */
00139         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
00140         uint32_t SMPL_PT : 2;          /*!< [9:8] Sample Point */
00141         uint32_t CLR_RXF : 1;          /*!< [10]  */
00142         uint32_t CLR_TXF : 1;          /*!< [11] Clear TX FIFO */
00143         uint32_t DIS_RXF : 1;          /*!< [12] Disable Receive FIFO */
00144         uint32_t DIS_TXF : 1;          /*!< [13] Disable Transmit FIFO */
00145         uint32_t MDIS : 1;             /*!< [14] Module Disable */
00146         uint32_t DOZE : 1;             /*!< [15] Doze Enable */
00147         uint32_t PCSIS : 6;            /*!< [21:16] Peripheral Chip Select x Inactive
00148                                         * State */
00149         uint32_t RESERVED1 : 2;        /*!< [23:22]  */
00150         uint32_t ROOE : 1;             /*!< [24] Receive FIFO Overflow Overwrite Enable */
00151         uint32_t PCSSE : 1;            /*!< [25] Peripheral Chip Select Strobe Enable */
00152         uint32_t MTFE : 1;             /*!< [26] Modified Timing Format Enable */
00153         uint32_t FRZ : 1;              /*!< [27] Freeze */
00154         uint32_t DCONF : 2;            /*!< [29:28] SPI Configuration. */
00155         uint32_t CONT_SCKE : 1;        /*!< [30] Continuous SCK Enable */
00156         uint32_t MSTR : 1;             /*!< [31] Master/Slave Mode Select */
00157     } B;
00158 } hw_spi_mcr_t;
00159 
00160 /*!
00161  * @name Constants and macros for entire SPI_MCR register
00162  */
00163 /*@{*/
00164 #define HW_SPI_MCR_ADDR(x)       ((x) + 0x0U)
00165 
00166 #define HW_SPI_MCR(x)            (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
00167 #define HW_SPI_MCR_RD(x)         (ADDRESS_READ(hw_spi_mcr_t, HW_SPI_MCR_ADDR(x)))
00168 #define HW_SPI_MCR_WR(x, v)      (ADDRESS_WRITE(hw_spi_mcr_t, HW_SPI_MCR_ADDR(x), v))
00169 #define HW_SPI_MCR_SET(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) |  (v)))
00170 #define HW_SPI_MCR_CLR(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
00171 #define HW_SPI_MCR_TOG(x, v)     (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^  (v)))
00172 /*@}*/
00173 
00174 /*
00175  * Constants & macros for individual SPI_MCR bitfields
00176  */
00177 
00178 /*!
00179  * @name Register SPI_MCR, field HALT[0] (RW)
00180  *
00181  * The HALT bit starts and stops frame transfers. See Start and Stop of Module
00182  * transfers
00183  *
00184  * Values:
00185  * - 0 - Start transfers.
00186  * - 1 - Stop transfers.
00187  */
00188 /*@{*/
00189 #define BP_SPI_MCR_HALT      (0U)          /*!< Bit position for SPI_MCR_HALT. */
00190 #define BM_SPI_MCR_HALT      (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */
00191 #define BS_SPI_MCR_HALT      (1U)          /*!< Bit field size in bits for SPI_MCR_HALT. */
00192 
00193 /*! @brief Read current value of the SPI_MCR_HALT field. */
00194 #define BR_SPI_MCR_HALT(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT)))
00195 
00196 /*! @brief Format value for bitfield SPI_MCR_HALT. */
00197 #define BF_SPI_MCR_HALT(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT)
00198 
00199 /*! @brief Set the HALT field to a new value. */
00200 #define BW_SPI_MCR_HALT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT), v))
00201 /*@}*/
00202 
00203 /*!
00204  * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
00205  *
00206  * Controls when the module master samples SIN in Modified Transfer Format. This
00207  * field is valid only when CPHA bit in CTARn[CPHA] is 0.
00208  *
00209  * Values:
00210  * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
00211  * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
00212  * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
00213  * - 11 - Reserved
00214  */
00215 /*@{*/
00216 #define BP_SPI_MCR_SMPL_PT   (8U)          /*!< Bit position for SPI_MCR_SMPL_PT. */
00217 #define BM_SPI_MCR_SMPL_PT   (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */
00218 #define BS_SPI_MCR_SMPL_PT   (2U)          /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */
00219 
00220 /*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
00221 #define BR_SPI_MCR_SMPL_PT(x) (UNION_READ(hw_spi_mcr_t, HW_SPI_MCR_ADDR(x), U, B.SMPL_PT))
00222 
00223 /*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */
00224 #define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT)
00225 
00226 /*! @brief Set the SMPL_PT field to a new value. */
00227 #define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
00228 /*@}*/
00229 
00230 /*!
00231  * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
00232  *
00233  * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
00234  * CLR_RXF bit is always read as zero.
00235  *
00236  * Values:
00237  * - 0 - Do not clear the RX FIFO counter.
00238  * - 1 - Clear the RX FIFO counter.
00239  */
00240 /*@{*/
00241 #define BP_SPI_MCR_CLR_RXF   (10U)         /*!< Bit position for SPI_MCR_CLR_RXF. */
00242 #define BM_SPI_MCR_CLR_RXF   (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */
00243 #define BS_SPI_MCR_CLR_RXF   (1U)          /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */
00244 
00245 /*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */
00246 #define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF)
00247 
00248 /*! @brief Set the CLR_RXF field to a new value. */
00249 #define BW_SPI_MCR_CLR_RXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF), v))
00250 /*@}*/
00251 
00252 /*!
00253  * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
00254  *
00255  * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
00256  * CLR_TXF bit is always read as zero.
00257  *
00258  * Values:
00259  * - 0 - Do not clear the TX FIFO counter.
00260  * - 1 - Clear the TX FIFO counter.
00261  */
00262 /*@{*/
00263 #define BP_SPI_MCR_CLR_TXF   (11U)         /*!< Bit position for SPI_MCR_CLR_TXF. */
00264 #define BM_SPI_MCR_CLR_TXF   (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */
00265 #define BS_SPI_MCR_CLR_TXF   (1U)          /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */
00266 
00267 /*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */
00268 #define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF)
00269 
00270 /*! @brief Set the CLR_TXF field to a new value. */
00271 #define BW_SPI_MCR_CLR_TXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF), v))
00272 /*@}*/
00273 
00274 /*!
00275  * @name Register SPI_MCR, field DIS_RXF[12] (RW)
00276  *
00277  * When the RX FIFO is disabled, the receive part of the module operates as a
00278  * simplified double-buffered SPI. This bit can only be written when the MDIS bit
00279  * is cleared.
00280  *
00281  * Values:
00282  * - 0 - RX FIFO is enabled.
00283  * - 1 - RX FIFO is disabled.
00284  */
00285 /*@{*/
00286 #define BP_SPI_MCR_DIS_RXF   (12U)         /*!< Bit position for SPI_MCR_DIS_RXF. */
00287 #define BM_SPI_MCR_DIS_RXF   (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */
00288 #define BS_SPI_MCR_DIS_RXF   (1U)          /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */
00289 
00290 /*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
00291 #define BR_SPI_MCR_DIS_RXF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF)))
00292 
00293 /*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */
00294 #define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF)
00295 
00296 /*! @brief Set the DIS_RXF field to a new value. */
00297 #define BW_SPI_MCR_DIS_RXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF), v))
00298 /*@}*/
00299 
00300 /*!
00301  * @name Register SPI_MCR, field DIS_TXF[13] (RW)
00302  *
00303  * When the TX FIFO is disabled, the transmit part of the module operates as a
00304  * simplified double-buffered SPI. This bit can be written only when the MDIS bit
00305  * is cleared.
00306  *
00307  * Values:
00308  * - 0 - TX FIFO is enabled.
00309  * - 1 - TX FIFO is disabled.
00310  */
00311 /*@{*/
00312 #define BP_SPI_MCR_DIS_TXF   (13U)         /*!< Bit position for SPI_MCR_DIS_TXF. */
00313 #define BM_SPI_MCR_DIS_TXF   (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */
00314 #define BS_SPI_MCR_DIS_TXF   (1U)          /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */
00315 
00316 /*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
00317 #define BR_SPI_MCR_DIS_TXF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF)))
00318 
00319 /*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */
00320 #define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF)
00321 
00322 /*! @brief Set the DIS_TXF field to a new value. */
00323 #define BW_SPI_MCR_DIS_TXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF), v))
00324 /*@}*/
00325 
00326 /*!
00327  * @name Register SPI_MCR, field MDIS[14] (RW)
00328  *
00329  * Allows the clock to be stopped to the non-memory mapped logic in the module
00330  * effectively putting it in a software-controlled power-saving state. The reset
00331  * value of the MDIS bit is parameterized, with a default reset value of 0. When
00332  * the module is used in Slave Mode, we recommend leaving this bit 0, because a
00333  * slave doesn't have control over master transactions.
00334  *
00335  * Values:
00336  * - 0 - Enables the module clocks.
00337  * - 1 - Allows external logic to disable the module clocks.
00338  */
00339 /*@{*/
00340 #define BP_SPI_MCR_MDIS      (14U)         /*!< Bit position for SPI_MCR_MDIS. */
00341 #define BM_SPI_MCR_MDIS      (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */
00342 #define BS_SPI_MCR_MDIS      (1U)          /*!< Bit field size in bits for SPI_MCR_MDIS. */
00343 
00344 /*! @brief Read current value of the SPI_MCR_MDIS field. */
00345 #define BR_SPI_MCR_MDIS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS)))
00346 
00347 /*! @brief Format value for bitfield SPI_MCR_MDIS. */
00348 #define BF_SPI_MCR_MDIS(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS)
00349 
00350 /*! @brief Set the MDIS field to a new value. */
00351 #define BW_SPI_MCR_MDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS), v))
00352 /*@}*/
00353 
00354 /*!
00355  * @name Register SPI_MCR, field DOZE[15] (RW)
00356  *
00357  * Provides support for an externally controlled Doze mode power-saving
00358  * mechanism.
00359  *
00360  * Values:
00361  * - 0 - Doze mode has no effect on the module.
00362  * - 1 - Doze mode disables the module.
00363  */
00364 /*@{*/
00365 #define BP_SPI_MCR_DOZE      (15U)         /*!< Bit position for SPI_MCR_DOZE. */
00366 #define BM_SPI_MCR_DOZE      (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */
00367 #define BS_SPI_MCR_DOZE      (1U)          /*!< Bit field size in bits for SPI_MCR_DOZE. */
00368 
00369 /*! @brief Read current value of the SPI_MCR_DOZE field. */
00370 #define BR_SPI_MCR_DOZE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE)))
00371 
00372 /*! @brief Format value for bitfield SPI_MCR_DOZE. */
00373 #define BF_SPI_MCR_DOZE(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE)
00374 
00375 /*! @brief Set the DOZE field to a new value. */
00376 #define BW_SPI_MCR_DOZE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE), v))
00377 /*@}*/
00378 
00379 /*!
00380  * @name Register SPI_MCR, field PCSIS[21:16] (RW)
00381  *
00382  * Determines the inactive state of PCSx.
00383  *
00384  * Values:
00385  * - 0 - The inactive state of PCSx is low.
00386  * - 1 - The inactive state of PCSx is high.
00387  */
00388 /*@{*/
00389 #define BP_SPI_MCR_PCSIS     (16U)         /*!< Bit position for SPI_MCR_PCSIS. */
00390 #define BM_SPI_MCR_PCSIS     (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */
00391 #define BS_SPI_MCR_PCSIS     (6U)          /*!< Bit field size in bits for SPI_MCR_PCSIS. */
00392 
00393 /*! @brief Read current value of the SPI_MCR_PCSIS field. */
00394 #define BR_SPI_MCR_PCSIS(x)  (UNION_READ(hw_spi_mcr_t, HW_SPI_MCR_ADDR(x), U, B.PCSIS))
00395 
00396 /*! @brief Format value for bitfield SPI_MCR_PCSIS. */
00397 #define BF_SPI_MCR_PCSIS(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS)
00398 
00399 /*! @brief Set the PCSIS field to a new value. */
00400 #define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
00401 /*@}*/
00402 
00403 /*!
00404  * @name Register SPI_MCR, field ROOE[24] (RW)
00405  *
00406  * In the RX FIFO overflow condition, configures the module to ignore the
00407  * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
00408  * is received, the data from the transfer, generating the overflow, is ignored
00409  * or shifted into the shift register.
00410  *
00411  * Values:
00412  * - 0 - Incoming data is ignored.
00413  * - 1 - Incoming data is shifted into the shift register.
00414  */
00415 /*@{*/
00416 #define BP_SPI_MCR_ROOE      (24U)         /*!< Bit position for SPI_MCR_ROOE. */
00417 #define BM_SPI_MCR_ROOE      (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */
00418 #define BS_SPI_MCR_ROOE      (1U)          /*!< Bit field size in bits for SPI_MCR_ROOE. */
00419 
00420 /*! @brief Read current value of the SPI_MCR_ROOE field. */
00421 #define BR_SPI_MCR_ROOE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE)))
00422 
00423 /*! @brief Format value for bitfield SPI_MCR_ROOE. */
00424 #define BF_SPI_MCR_ROOE(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE)
00425 
00426 /*! @brief Set the ROOE field to a new value. */
00427 #define BW_SPI_MCR_ROOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE), v))
00428 /*@}*/
00429 
00430 /*!
00431  * @name Register SPI_MCR, field PCSSE[25] (RW)
00432  *
00433  * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
00434  *
00435  * Values:
00436  * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
00437  * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
00438  */
00439 /*@{*/
00440 #define BP_SPI_MCR_PCSSE     (25U)         /*!< Bit position for SPI_MCR_PCSSE. */
00441 #define BM_SPI_MCR_PCSSE     (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */
00442 #define BS_SPI_MCR_PCSSE     (1U)          /*!< Bit field size in bits for SPI_MCR_PCSSE. */
00443 
00444 /*! @brief Read current value of the SPI_MCR_PCSSE field. */
00445 #define BR_SPI_MCR_PCSSE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE)))
00446 
00447 /*! @brief Format value for bitfield SPI_MCR_PCSSE. */
00448 #define BF_SPI_MCR_PCSSE(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE)
00449 
00450 /*! @brief Set the PCSSE field to a new value. */
00451 #define BW_SPI_MCR_PCSSE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE), v))
00452 /*@}*/
00453 
00454 /*!
00455  * @name Register SPI_MCR, field MTFE[26] (RW)
00456  *
00457  * Enables a modified transfer format to be used.
00458  *
00459  * Values:
00460  * - 0 - Modified SPI transfer format disabled.
00461  * - 1 - Modified SPI transfer format enabled.
00462  */
00463 /*@{*/
00464 #define BP_SPI_MCR_MTFE      (26U)         /*!< Bit position for SPI_MCR_MTFE. */
00465 #define BM_SPI_MCR_MTFE      (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */
00466 #define BS_SPI_MCR_MTFE      (1U)          /*!< Bit field size in bits for SPI_MCR_MTFE. */
00467 
00468 /*! @brief Read current value of the SPI_MCR_MTFE field. */
00469 #define BR_SPI_MCR_MTFE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE)))
00470 
00471 /*! @brief Format value for bitfield SPI_MCR_MTFE. */
00472 #define BF_SPI_MCR_MTFE(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE)
00473 
00474 /*! @brief Set the MTFE field to a new value. */
00475 #define BW_SPI_MCR_MTFE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE), v))
00476 /*@}*/
00477 
00478 /*!
00479  * @name Register SPI_MCR, field FRZ[27] (RW)
00480  *
00481  * Enables transfers to be stopped on the next frame boundary when the device
00482  * enters Debug mode.
00483  *
00484  * Values:
00485  * - 0 - Do not halt serial transfers in Debug mode.
00486  * - 1 - Halt serial transfers in Debug mode.
00487  */
00488 /*@{*/
00489 #define BP_SPI_MCR_FRZ       (27U)         /*!< Bit position for SPI_MCR_FRZ. */
00490 #define BM_SPI_MCR_FRZ       (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */
00491 #define BS_SPI_MCR_FRZ       (1U)          /*!< Bit field size in bits for SPI_MCR_FRZ. */
00492 
00493 /*! @brief Read current value of the SPI_MCR_FRZ field. */
00494 #define BR_SPI_MCR_FRZ(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ)))
00495 
00496 /*! @brief Format value for bitfield SPI_MCR_FRZ. */
00497 #define BF_SPI_MCR_FRZ(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ)
00498 
00499 /*! @brief Set the FRZ field to a new value. */
00500 #define BW_SPI_MCR_FRZ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ), v))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register SPI_MCR, field DCONF[29:28] (RO)
00505  *
00506  * Selects among the different configurations of the module.
00507  *
00508  * Values:
00509  * - 00 - SPI
00510  * - 01 - Reserved
00511  * - 10 - Reserved
00512  * - 11 - Reserved
00513  */
00514 /*@{*/
00515 #define BP_SPI_MCR_DCONF     (28U)         /*!< Bit position for SPI_MCR_DCONF. */
00516 #define BM_SPI_MCR_DCONF     (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */
00517 #define BS_SPI_MCR_DCONF     (2U)          /*!< Bit field size in bits for SPI_MCR_DCONF. */
00518 
00519 /*! @brief Read current value of the SPI_MCR_DCONF field. */
00520 #define BR_SPI_MCR_DCONF(x)  (UNION_READ(hw_spi_mcr_t, HW_SPI_MCR_ADDR(x), U, B.DCONF))
00521 /*@}*/
00522 
00523 /*!
00524  * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
00525  *
00526  * Enables the Serial Communication Clock (SCK) to run continuously.
00527  *
00528  * Values:
00529  * - 0 - Continuous SCK disabled.
00530  * - 1 - Continuous SCK enabled.
00531  */
00532 /*@{*/
00533 #define BP_SPI_MCR_CONT_SCKE (30U)         /*!< Bit position for SPI_MCR_CONT_SCKE. */
00534 #define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */
00535 #define BS_SPI_MCR_CONT_SCKE (1U)          /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */
00536 
00537 /*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
00538 #define BR_SPI_MCR_CONT_SCKE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE)))
00539 
00540 /*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */
00541 #define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE)
00542 
00543 /*! @brief Set the CONT_SCKE field to a new value. */
00544 #define BW_SPI_MCR_CONT_SCKE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE), v))
00545 /*@}*/
00546 
00547 /*!
00548  * @name Register SPI_MCR, field MSTR[31] (RW)
00549  *
00550  * Enables either Master mode (if supported) or Slave mode (if supported)
00551  * operation.
00552  *
00553  * Values:
00554  * - 0 - Enables Slave mode
00555  * - 1 - Enables Master mode
00556  */
00557 /*@{*/
00558 #define BP_SPI_MCR_MSTR      (31U)         /*!< Bit position for SPI_MCR_MSTR. */
00559 #define BM_SPI_MCR_MSTR      (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */
00560 #define BS_SPI_MCR_MSTR      (1U)          /*!< Bit field size in bits for SPI_MCR_MSTR. */
00561 
00562 /*! @brief Read current value of the SPI_MCR_MSTR field. */
00563 #define BR_SPI_MCR_MSTR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR)))
00564 
00565 /*! @brief Format value for bitfield SPI_MCR_MSTR. */
00566 #define BF_SPI_MCR_MSTR(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR)
00567 
00568 /*! @brief Set the MSTR field to a new value. */
00569 #define BW_SPI_MCR_MSTR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR), v))
00570 /*@}*/
00571 
00572 /*******************************************************************************
00573  * HW_SPI_TCR - Transfer Count Register
00574  ******************************************************************************/
00575 
00576 /*!
00577  * @brief HW_SPI_TCR - Transfer Count Register (RW)
00578  *
00579  * Reset value: 0x00000000U
00580  *
00581  * TCR contains a counter that indicates the number of SPI transfers made. The
00582  * transfer counter is intended to assist in queue management. Do not write the
00583  * TCR when the module is in the Running state.
00584  */
00585 typedef union _hw_spi_tcr
00586 {
00587     uint32_t U;
00588     struct _hw_spi_tcr_bitfields
00589     {
00590         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
00591         uint32_t SPI_TCNT : 16;        /*!< [31:16] SPI Transfer Counter */
00592     } B;
00593 } hw_spi_tcr_t;
00594 
00595 /*!
00596  * @name Constants and macros for entire SPI_TCR register
00597  */
00598 /*@{*/
00599 #define HW_SPI_TCR_ADDR(x)       ((x) + 0x8U)
00600 
00601 #define HW_SPI_TCR(x)            (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
00602 #define HW_SPI_TCR_RD(x)         (ADDRESS_READ(hw_spi_tcr_t, HW_SPI_TCR_ADDR(x)))
00603 #define HW_SPI_TCR_WR(x, v)      (ADDRESS_WRITE(hw_spi_tcr_t, HW_SPI_TCR_ADDR(x), v))
00604 #define HW_SPI_TCR_SET(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) |  (v)))
00605 #define HW_SPI_TCR_CLR(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
00606 #define HW_SPI_TCR_TOG(x, v)     (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^  (v)))
00607 /*@}*/
00608 
00609 /*
00610  * Constants & macros for individual SPI_TCR bitfields
00611  */
00612 
00613 /*!
00614  * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
00615  *
00616  * Counts the number of SPI transfers the module makes. The SPI_TCNT field
00617  * increments every time the last bit of an SPI frame is transmitted. A value written
00618  * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
00619  * the beginning of the frame when the CTCNT field is set in the executing SPI
00620  * command. The Transfer Counter wraps around; incrementing the counter past 65535
00621  * resets the counter to zero.
00622  */
00623 /*@{*/
00624 #define BP_SPI_TCR_SPI_TCNT  (16U)         /*!< Bit position for SPI_TCR_SPI_TCNT. */
00625 #define BM_SPI_TCR_SPI_TCNT  (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */
00626 #define BS_SPI_TCR_SPI_TCNT  (16U)         /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */
00627 
00628 /*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
00629 #define BR_SPI_TCR_SPI_TCNT(x) (UNION_READ(hw_spi_tcr_t, HW_SPI_TCR_ADDR(x), U, B.SPI_TCNT))
00630 
00631 /*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */
00632 #define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT)
00633 
00634 /*! @brief Set the SPI_TCNT field to a new value. */
00635 #define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
00636 /*@}*/
00637 
00638 /*******************************************************************************
00639  * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
00640  ******************************************************************************/
00641 
00642 /*!
00643  * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
00644  *
00645  * Reset value: 0x78000000U
00646  *
00647  * CTAR registers are used to define different transfer attributes. Do not write
00648  * to the CTAR registers while the module is in the Running state. In Master
00649  * mode, the CTAR registers define combinations of transfer attributes such as frame
00650  * size, clock phase and polarity, data bit ordering, baud rate, and various
00651  * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
00652  * slave transfer attributes. When the module is configured as an SPI master, the
00653  * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
00654  * registers is used. When the module is configured as an SPI bus slave, it uses
00655  * the CTAR0 register.
00656  */
00657 typedef union _hw_spi_ctarn
00658 {
00659     uint32_t U;
00660     struct _hw_spi_ctarn_bitfields
00661     {
00662         uint32_t BR : 4;               /*!< [3:0] Baud Rate Scaler */
00663         uint32_t DT : 4;               /*!< [7:4] Delay After Transfer Scaler */
00664         uint32_t ASC : 4;              /*!< [11:8] After SCK Delay Scaler */
00665         uint32_t CSSCK : 4;            /*!< [15:12] PCS to SCK Delay Scaler */
00666         uint32_t PBR : 2;              /*!< [17:16] Baud Rate Prescaler */
00667         uint32_t PDT : 2;              /*!< [19:18] Delay after Transfer Prescaler */
00668         uint32_t PASC : 2;             /*!< [21:20] After SCK Delay Prescaler */
00669         uint32_t PCSSCK : 2;           /*!< [23:22] PCS to SCK Delay Prescaler */
00670         uint32_t LSBFE : 1;            /*!< [24] LSB First */
00671         uint32_t CPHA : 1;             /*!< [25] Clock Phase */
00672         uint32_t CPOL : 1;             /*!< [26] Clock Polarity */
00673         uint32_t FMSZ : 4;             /*!< [30:27] Frame Size */
00674         uint32_t DBR : 1;              /*!< [31] Double Baud Rate */
00675     } B;
00676 } hw_spi_ctarn_t;
00677 
00678 /*!
00679  * @name Constants and macros for entire SPI_CTARn register
00680  */
00681 /*@{*/
00682 #define HW_SPI_CTARn_COUNT (2U)
00683 
00684 #define HW_SPI_CTARn_ADDR(x, n)  ((x) + 0xCU + (0x4U * (n)))
00685 
00686 #define HW_SPI_CTARn(x, n)       (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
00687 #define HW_SPI_CTARn_RD(x, n)    (ADDRESS_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n)))
00688 #define HW_SPI_CTARn_WR(x, n, v) (ADDRESS_WRITE(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), v))
00689 #define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) |  (v)))
00690 #define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
00691 #define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^  (v)))
00692 /*@}*/
00693 
00694 /*
00695  * Constants & macros for individual SPI_CTARn bitfields
00696  */
00697 
00698 /*!
00699  * @name Register SPI_CTARn, field BR[3:0] (RW)
00700  *
00701  * Selects the scaler value for the baud rate. This field is used only in master
00702  * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
00703  * generate the frequency of the SCK. The baud rate is computed according to the
00704  * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
00705  * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
00706  * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
00707  * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
00708  */
00709 /*@{*/
00710 #define BP_SPI_CTARn_BR      (0U)          /*!< Bit position for SPI_CTARn_BR. */
00711 #define BM_SPI_CTARn_BR      (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */
00712 #define BS_SPI_CTARn_BR      (4U)          /*!< Bit field size in bits for SPI_CTARn_BR. */
00713 
00714 /*! @brief Read current value of the SPI_CTARn_BR field. */
00715 #define BR_SPI_CTARn_BR(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.BR))
00716 
00717 /*! @brief Format value for bitfield SPI_CTARn_BR. */
00718 #define BF_SPI_CTARn_BR(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR)
00719 
00720 /*! @brief Set the BR field to a new value. */
00721 #define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
00722 /*@}*/
00723 
00724 /*!
00725  * @name Register SPI_CTARn, field DT[7:4] (RW)
00726  *
00727  * Selects the Delay after Transfer Scaler. This field is used only in master
00728  * mode. The Delay after Transfer is the time between the negation of the PCS
00729  * signal at the end of a frame and the assertion of PCS at the beginning of the next
00730  * frame. In the Continuous Serial Communications Clock operation, the DT value
00731  * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
00732  * protocol clock period, and it is computed according to the following
00733  * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
00734  * field description for scaler values.
00735  */
00736 /*@{*/
00737 #define BP_SPI_CTARn_DT      (4U)          /*!< Bit position for SPI_CTARn_DT. */
00738 #define BM_SPI_CTARn_DT      (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */
00739 #define BS_SPI_CTARn_DT      (4U)          /*!< Bit field size in bits for SPI_CTARn_DT. */
00740 
00741 /*! @brief Read current value of the SPI_CTARn_DT field. */
00742 #define BR_SPI_CTARn_DT(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.DT))
00743 
00744 /*! @brief Format value for bitfield SPI_CTARn_DT. */
00745 #define BF_SPI_CTARn_DT(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT)
00746 
00747 /*! @brief Set the DT field to a new value. */
00748 #define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
00749 /*@}*/
00750 
00751 /*!
00752  * @name Register SPI_CTARn, field ASC[11:8] (RW)
00753  *
00754  * Selects the scaler value for the After SCK Delay. This field is used only in
00755  * master mode. The After SCK Delay is the delay between the last edge of SCK and
00756  * the negation of PCS. The delay is a multiple of the protocol clock period,
00757  * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
00758  * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
00759  * scaler values. Refer After SCK Delay (tASC ) for more details.
00760  */
00761 /*@{*/
00762 #define BP_SPI_CTARn_ASC     (8U)          /*!< Bit position for SPI_CTARn_ASC. */
00763 #define BM_SPI_CTARn_ASC     (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */
00764 #define BS_SPI_CTARn_ASC     (4U)          /*!< Bit field size in bits for SPI_CTARn_ASC. */
00765 
00766 /*! @brief Read current value of the SPI_CTARn_ASC field. */
00767 #define BR_SPI_CTARn_ASC(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.ASC))
00768 
00769 /*! @brief Format value for bitfield SPI_CTARn_ASC. */
00770 #define BF_SPI_CTARn_ASC(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC)
00771 
00772 /*! @brief Set the ASC field to a new value. */
00773 #define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
00774 /*@}*/
00775 
00776 /*!
00777  * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
00778  *
00779  * Selects the scaler value for the PCS to SCK delay. This field is used only in
00780  * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
00781  * and the first edge of the SCK. The delay is a multiple of the protocol clock
00782  * period, and it is computed according to the following equation: t CSC = (1/fP )
00783  * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
00784  * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
00785  * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
00786  * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
00787  * details.
00788  */
00789 /*@{*/
00790 #define BP_SPI_CTARn_CSSCK   (12U)         /*!< Bit position for SPI_CTARn_CSSCK. */
00791 #define BM_SPI_CTARn_CSSCK   (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */
00792 #define BS_SPI_CTARn_CSSCK   (4U)          /*!< Bit field size in bits for SPI_CTARn_CSSCK. */
00793 
00794 /*! @brief Read current value of the SPI_CTARn_CSSCK field. */
00795 #define BR_SPI_CTARn_CSSCK(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.CSSCK))
00796 
00797 /*! @brief Format value for bitfield SPI_CTARn_CSSCK. */
00798 #define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK)
00799 
00800 /*! @brief Set the CSSCK field to a new value. */
00801 #define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
00802 /*@}*/
00803 
00804 /*!
00805  * @name Register SPI_CTARn, field PBR[17:16] (RW)
00806  *
00807  * Selects the prescaler value for the baud rate. This field is used only in
00808  * master mode. The baud rate is the frequency of the SCK. The protocol clock is
00809  * divided by the prescaler value before the baud rate selection takes place. See
00810  * the BR field description for details on how to compute the baud rate.
00811  *
00812  * Values:
00813  * - 00 - Baud Rate Prescaler value is 2.
00814  * - 01 - Baud Rate Prescaler value is 3.
00815  * - 10 - Baud Rate Prescaler value is 5.
00816  * - 11 - Baud Rate Prescaler value is 7.
00817  */
00818 /*@{*/
00819 #define BP_SPI_CTARn_PBR     (16U)         /*!< Bit position for SPI_CTARn_PBR. */
00820 #define BM_SPI_CTARn_PBR     (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */
00821 #define BS_SPI_CTARn_PBR     (2U)          /*!< Bit field size in bits for SPI_CTARn_PBR. */
00822 
00823 /*! @brief Read current value of the SPI_CTARn_PBR field. */
00824 #define BR_SPI_CTARn_PBR(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.PBR))
00825 
00826 /*! @brief Format value for bitfield SPI_CTARn_PBR. */
00827 #define BF_SPI_CTARn_PBR(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR)
00828 
00829 /*! @brief Set the PBR field to a new value. */
00830 #define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
00831 /*@}*/
00832 
00833 /*!
00834  * @name Register SPI_CTARn, field PDT[19:18] (RW)
00835  *
00836  * Selects the prescaler value for the delay between the negation of the PCS
00837  * signal at the end of a frame and the assertion of PCS at the beginning of the
00838  * next frame. The PDT field is only used in master mode. See the DT field
00839  * description for details on how to compute the Delay after Transfer. Refer Delay after
00840  * Transfer (tDT ) for more details.
00841  *
00842  * Values:
00843  * - 00 - Delay after Transfer Prescaler value is 1.
00844  * - 01 - Delay after Transfer Prescaler value is 3.
00845  * - 10 - Delay after Transfer Prescaler value is 5.
00846  * - 11 - Delay after Transfer Prescaler value is 7.
00847  */
00848 /*@{*/
00849 #define BP_SPI_CTARn_PDT     (18U)         /*!< Bit position for SPI_CTARn_PDT. */
00850 #define BM_SPI_CTARn_PDT     (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */
00851 #define BS_SPI_CTARn_PDT     (2U)          /*!< Bit field size in bits for SPI_CTARn_PDT. */
00852 
00853 /*! @brief Read current value of the SPI_CTARn_PDT field. */
00854 #define BR_SPI_CTARn_PDT(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.PDT))
00855 
00856 /*! @brief Format value for bitfield SPI_CTARn_PDT. */
00857 #define BF_SPI_CTARn_PDT(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT)
00858 
00859 /*! @brief Set the PDT field to a new value. */
00860 #define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
00861 /*@}*/
00862 
00863 /*!
00864  * @name Register SPI_CTARn, field PASC[21:20] (RW)
00865  *
00866  * Selects the prescaler value for the delay between the last edge of SCK and
00867  * the negation of PCS. See the ASC field description for information on how to
00868  * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
00869  *
00870  * Values:
00871  * - 00 - Delay after Transfer Prescaler value is 1.
00872  * - 01 - Delay after Transfer Prescaler value is 3.
00873  * - 10 - Delay after Transfer Prescaler value is 5.
00874  * - 11 - Delay after Transfer Prescaler value is 7.
00875  */
00876 /*@{*/
00877 #define BP_SPI_CTARn_PASC    (20U)         /*!< Bit position for SPI_CTARn_PASC. */
00878 #define BM_SPI_CTARn_PASC    (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */
00879 #define BS_SPI_CTARn_PASC    (2U)          /*!< Bit field size in bits for SPI_CTARn_PASC. */
00880 
00881 /*! @brief Read current value of the SPI_CTARn_PASC field. */
00882 #define BR_SPI_CTARn_PASC(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.PASC))
00883 
00884 /*! @brief Format value for bitfield SPI_CTARn_PASC. */
00885 #define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC)
00886 
00887 /*! @brief Set the PASC field to a new value. */
00888 #define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
00889 /*@}*/
00890 
00891 /*!
00892  * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
00893  *
00894  * Selects the prescaler value for the delay between assertion of PCS and the
00895  * first edge of the SCK. See the CSSCK field description for information on how to
00896  * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
00897  *
00898  * Values:
00899  * - 00 - PCS to SCK Prescaler value is 1.
00900  * - 01 - PCS to SCK Prescaler value is 3.
00901  * - 10 - PCS to SCK Prescaler value is 5.
00902  * - 11 - PCS to SCK Prescaler value is 7.
00903  */
00904 /*@{*/
00905 #define BP_SPI_CTARn_PCSSCK  (22U)         /*!< Bit position for SPI_CTARn_PCSSCK. */
00906 #define BM_SPI_CTARn_PCSSCK  (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */
00907 #define BS_SPI_CTARn_PCSSCK  (2U)          /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */
00908 
00909 /*! @brief Read current value of the SPI_CTARn_PCSSCK field. */
00910 #define BR_SPI_CTARn_PCSSCK(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.PCSSCK))
00911 
00912 /*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */
00913 #define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK)
00914 
00915 /*! @brief Set the PCSSCK field to a new value. */
00916 #define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
00917 /*@}*/
00918 
00919 /*!
00920  * @name Register SPI_CTARn, field LSBFE[24] (RW)
00921  *
00922  * Specifies whether the LSB or MSB of the frame is transferred first.
00923  *
00924  * Values:
00925  * - 0 - Data is transferred MSB first.
00926  * - 1 - Data is transferred LSB first.
00927  */
00928 /*@{*/
00929 #define BP_SPI_CTARn_LSBFE   (24U)         /*!< Bit position for SPI_CTARn_LSBFE. */
00930 #define BM_SPI_CTARn_LSBFE   (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */
00931 #define BS_SPI_CTARn_LSBFE   (1U)          /*!< Bit field size in bits for SPI_CTARn_LSBFE. */
00932 
00933 /*! @brief Read current value of the SPI_CTARn_LSBFE field. */
00934 #define BR_SPI_CTARn_LSBFE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE)))
00935 
00936 /*! @brief Format value for bitfield SPI_CTARn_LSBFE. */
00937 #define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE)
00938 
00939 /*! @brief Set the LSBFE field to a new value. */
00940 #define BW_SPI_CTARn_LSBFE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE), v))
00941 /*@}*/
00942 
00943 /*!
00944  * @name Register SPI_CTARn, field CPHA[25] (RW)
00945  *
00946  * Selects which edge of SCK causes data to change and which edge causes data to
00947  * be captured. This bit is used in both master and slave mode. For successful
00948  * communication between serial devices, the devices must have identical clock
00949  * phase settings. In Continuous SCK mode, the bit value is ignored and the
00950  * transfers are done as if the CPHA bit is set to 1.
00951  *
00952  * Values:
00953  * - 0 - Data is captured on the leading edge of SCK and changed on the
00954  *     following edge.
00955  * - 1 - Data is changed on the leading edge of SCK and captured on the
00956  *     following edge.
00957  */
00958 /*@{*/
00959 #define BP_SPI_CTARn_CPHA    (25U)         /*!< Bit position for SPI_CTARn_CPHA. */
00960 #define BM_SPI_CTARn_CPHA    (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */
00961 #define BS_SPI_CTARn_CPHA    (1U)          /*!< Bit field size in bits for SPI_CTARn_CPHA. */
00962 
00963 /*! @brief Read current value of the SPI_CTARn_CPHA field. */
00964 #define BR_SPI_CTARn_CPHA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA)))
00965 
00966 /*! @brief Format value for bitfield SPI_CTARn_CPHA. */
00967 #define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA)
00968 
00969 /*! @brief Set the CPHA field to a new value. */
00970 #define BW_SPI_CTARn_CPHA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA), v))
00971 /*@}*/
00972 
00973 /*!
00974  * @name Register SPI_CTARn, field CPOL[26] (RW)
00975  *
00976  * Selects the inactive state of the Serial Communications Clock (SCK). This bit
00977  * is used in both master and slave mode. For successful communication between
00978  * serial devices, the devices must have identical clock polarities. When the
00979  * Continuous Selection Format is selected, switching between clock polarities
00980  * without stopping the module can cause errors in the transfer due to the peripheral
00981  * device interpreting the switch of clock polarity as a valid clock edge. In case
00982  * of continous sck mode, when the module goes in low power mode(disabled),
00983  * inactive state of sck is not guaranted.
00984  *
00985  * Values:
00986  * - 0 - The inactive state value of SCK is low.
00987  * - 1 - The inactive state value of SCK is high.
00988  */
00989 /*@{*/
00990 #define BP_SPI_CTARn_CPOL    (26U)         /*!< Bit position for SPI_CTARn_CPOL. */
00991 #define BM_SPI_CTARn_CPOL    (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */
00992 #define BS_SPI_CTARn_CPOL    (1U)          /*!< Bit field size in bits for SPI_CTARn_CPOL. */
00993 
00994 /*! @brief Read current value of the SPI_CTARn_CPOL field. */
00995 #define BR_SPI_CTARn_CPOL(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL)))
00996 
00997 /*! @brief Format value for bitfield SPI_CTARn_CPOL. */
00998 #define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL)
00999 
01000 /*! @brief Set the CPOL field to a new value. */
01001 #define BW_SPI_CTARn_CPOL(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL), v))
01002 /*@}*/
01003 
01004 /*!
01005  * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
01006  *
01007  * The number of bits transferred per frame is equal to the FMSZ value plus 1.
01008  * Regardless of the transmission mode, the minimum valid frame size value is 4.
01009  */
01010 /*@{*/
01011 #define BP_SPI_CTARn_FMSZ    (27U)         /*!< Bit position for SPI_CTARn_FMSZ. */
01012 #define BM_SPI_CTARn_FMSZ    (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */
01013 #define BS_SPI_CTARn_FMSZ    (4U)          /*!< Bit field size in bits for SPI_CTARn_FMSZ. */
01014 
01015 /*! @brief Read current value of the SPI_CTARn_FMSZ field. */
01016 #define BR_SPI_CTARn_FMSZ(x, n) (UNION_READ(hw_spi_ctarn_t, HW_SPI_CTARn_ADDR(x, n), U, B.FMSZ))
01017 
01018 /*! @brief Format value for bitfield SPI_CTARn_FMSZ. */
01019 #define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ)
01020 
01021 /*! @brief Set the FMSZ field to a new value. */
01022 #define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
01023 /*@}*/
01024 
01025 /*!
01026  * @name Register SPI_CTARn, field DBR[31] (RW)
01027  *
01028  * Doubles the effective baud rate of the Serial Communications Clock (SCK).
01029  * This field is used only in master mode. It effectively halves the Baud Rate
01030  * division ratio, supporting faster frequencies, and odd division ratios for the
01031  * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
01032  * Serial Communications Clock (SCK) depends on the value in the Baud Rate
01033  * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
01034  * description for details on how to compute the baud rate. SPI SCK Duty Cycle
01035  * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
01036  * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
01037  *
01038  * Values:
01039  * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
01040  * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
01041  *     Prescaler.
01042  */
01043 /*@{*/
01044 #define BP_SPI_CTARn_DBR     (31U)         /*!< Bit position for SPI_CTARn_DBR. */
01045 #define BM_SPI_CTARn_DBR     (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */
01046 #define BS_SPI_CTARn_DBR     (1U)          /*!< Bit field size in bits for SPI_CTARn_DBR. */
01047 
01048 /*! @brief Read current value of the SPI_CTARn_DBR field. */
01049 #define BR_SPI_CTARn_DBR(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR)))
01050 
01051 /*! @brief Format value for bitfield SPI_CTARn_DBR. */
01052 #define BF_SPI_CTARn_DBR(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR)
01053 
01054 /*! @brief Set the DBR field to a new value. */
01055 #define BW_SPI_CTARn_DBR(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR), v))
01056 /*@}*/
01057 /*******************************************************************************
01058  * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
01059  ******************************************************************************/
01060 
01061 /*!
01062  * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
01063  *
01064  * Reset value: 0x78000000U
01065  *
01066  * When the module is configured as an SPI bus slave, the CTAR0 register is used.
01067  */
01068 typedef union _hw_spi_ctarn_slave
01069 {
01070     uint32_t U;
01071     struct _hw_spi_ctarn_slave_bitfields
01072     {
01073         uint32_t RESERVED0 : 25;       /*!< [24:0]  */
01074         uint32_t CPHA : 1;             /*!< [25] Clock Phase */
01075         uint32_t CPOL : 1;             /*!< [26] Clock Polarity */
01076         uint32_t FMSZ : 5;             /*!< [31:27] Frame Size */
01077     } B;
01078 } hw_spi_ctarn_slave_t;
01079 
01080 /*!
01081  * @name Constants and macros for entire SPI_CTARn_SLAVE register
01082  */
01083 /*@{*/
01084 #define HW_SPI_CTARn_SLAVE_COUNT (1U)
01085 
01086 #define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
01087 
01088 #define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
01089 #define HW_SPI_CTARn_SLAVE_RD(x, n) (ADDRESS_READ(hw_spi_ctarn_slave_t, HW_SPI_CTARn_SLAVE_ADDR(x, n)))
01090 #define HW_SPI_CTARn_SLAVE_WR(x, n, v) (ADDRESS_WRITE(hw_spi_ctarn_slave_t, HW_SPI_CTARn_SLAVE_ADDR(x, n), v))
01091 #define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) |  (v)))
01092 #define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
01093 #define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^  (v)))
01094 /*@}*/
01095 
01096 /*
01097  * Constants & macros for individual SPI_CTARn_SLAVE bitfields
01098  */
01099 
01100 /*!
01101  * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
01102  *
01103  * Selects which edge of SCK causes data to change and which edge causes data to
01104  * be captured. This bit is used in both master and slave mode. For successful
01105  * communication between serial devices, the devices must have identical clock
01106  * phase settings. In Continuous SCK mode, the bit value is ignored and the
01107  * transfers are done as if the CPHA bit is set to 1.
01108  *
01109  * Values:
01110  * - 0 - Data is captured on the leading edge of SCK and changed on the
01111  *     following edge.
01112  * - 1 - Data is changed on the leading edge of SCK and captured on the
01113  *     following edge.
01114  */
01115 /*@{*/
01116 #define BP_SPI_CTARn_SLAVE_CPHA (25U)      /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */
01117 #define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */
01118 #define BS_SPI_CTARn_SLAVE_CPHA (1U)       /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */
01119 
01120 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */
01121 #define BR_SPI_CTARn_SLAVE_CPHA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA)))
01122 
01123 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */
01124 #define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA)
01125 
01126 /*! @brief Set the CPHA field to a new value. */
01127 #define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA), v))
01128 /*@}*/
01129 
01130 /*!
01131  * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
01132  *
01133  * Selects the inactive state of the Serial Communications Clock (SCK). In case
01134  * of continous sck mode, when the module goes in low power mode(disabled),
01135  * inactive state of sck is not guaranted.
01136  *
01137  * Values:
01138  * - 0 - The inactive state value of SCK is low.
01139  * - 1 - The inactive state value of SCK is high.
01140  */
01141 /*@{*/
01142 #define BP_SPI_CTARn_SLAVE_CPOL (26U)      /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */
01143 #define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */
01144 #define BS_SPI_CTARn_SLAVE_CPOL (1U)       /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */
01145 
01146 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */
01147 #define BR_SPI_CTARn_SLAVE_CPOL(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL)))
01148 
01149 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */
01150 #define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL)
01151 
01152 /*! @brief Set the CPOL field to a new value. */
01153 #define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL), v))
01154 /*@}*/
01155 
01156 /*!
01157  * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
01158  *
01159  * The number of bits transfered per frame is equal to the FMSZ field value plus
01160  * 1. Note that the minimum valid value of frame size is 4.
01161  */
01162 /*@{*/
01163 #define BP_SPI_CTARn_SLAVE_FMSZ (27U)      /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */
01164 #define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */
01165 #define BS_SPI_CTARn_SLAVE_FMSZ (5U)       /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */
01166 
01167 /*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */
01168 #define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (UNION_READ(hw_spi_ctarn_slave_t, HW_SPI_CTARn_SLAVE_ADDR(x, n), U, B.FMSZ))
01169 
01170 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */
01171 #define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ)
01172 
01173 /*! @brief Set the FMSZ field to a new value. */
01174 #define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
01175 /*@}*/
01176 
01177 /*******************************************************************************
01178  * HW_SPI_SR - Status Register
01179  ******************************************************************************/
01180 
01181 /*!
01182  * @brief HW_SPI_SR - Status Register (RW)
01183  *
01184  * Reset value: 0x02000000U
01185  *
01186  * SR contains status and flag bits. The bits reflect the status of the module
01187  * and indicate the occurrence of events that can generate interrupt or DMA
01188  * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
01189  * to a flag bit has no effect. This register may not be writable in Module
01190  * Disable mode due to the use of power saving mechanisms.
01191  */
01192 typedef union _hw_spi_sr
01193 {
01194     uint32_t U;
01195     struct _hw_spi_sr_bitfields
01196     {
01197         uint32_t POPNXTPTR : 4;        /*!< [3:0] Pop Next Pointer */
01198         uint32_t RXCTR : 4;            /*!< [7:4] RX FIFO Counter */
01199         uint32_t TXNXTPTR : 4;         /*!< [11:8] Transmit Next Pointer */
01200         uint32_t TXCTR : 4;            /*!< [15:12] TX FIFO Counter */
01201         uint32_t RESERVED0 : 1;        /*!< [16]  */
01202         uint32_t RFDF : 1;             /*!< [17] Receive FIFO Drain Flag */
01203         uint32_t RESERVED1 : 1;        /*!< [18]  */
01204         uint32_t RFOF : 1;             /*!< [19] Receive FIFO Overflow Flag */
01205         uint32_t RESERVED2 : 5;        /*!< [24:20]  */
01206         uint32_t TFFF : 1;             /*!< [25] Transmit FIFO Fill Flag */
01207         uint32_t RESERVED3 : 1;        /*!< [26]  */
01208         uint32_t TFUF : 1;             /*!< [27] Transmit FIFO Underflow Flag */
01209         uint32_t EOQF : 1;             /*!< [28] End of Queue Flag */
01210         uint32_t RESERVED4 : 1;        /*!< [29]  */
01211         uint32_t TXRXS : 1;            /*!< [30] TX and RX Status */
01212         uint32_t TCF : 1;              /*!< [31] Transfer Complete Flag */
01213     } B;
01214 } hw_spi_sr_t;
01215 
01216 /*!
01217  * @name Constants and macros for entire SPI_SR register
01218  */
01219 /*@{*/
01220 #define HW_SPI_SR_ADDR(x)        ((x) + 0x2CU)
01221 
01222 #define HW_SPI_SR(x)             (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
01223 #define HW_SPI_SR_RD(x)          (ADDRESS_READ(hw_spi_sr_t, HW_SPI_SR_ADDR(x)))
01224 #define HW_SPI_SR_WR(x, v)       (ADDRESS_WRITE(hw_spi_sr_t, HW_SPI_SR_ADDR(x), v))
01225 #define HW_SPI_SR_SET(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) |  (v)))
01226 #define HW_SPI_SR_CLR(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
01227 #define HW_SPI_SR_TOG(x, v)      (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^  (v)))
01228 /*@}*/
01229 
01230 /*
01231  * Constants & macros for individual SPI_SR bitfields
01232  */
01233 
01234 /*!
01235  * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
01236  *
01237  * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
01238  * The POPNXTPTR is updated when the POPR is read.
01239  */
01240 /*@{*/
01241 #define BP_SPI_SR_POPNXTPTR  (0U)          /*!< Bit position for SPI_SR_POPNXTPTR. */
01242 #define BM_SPI_SR_POPNXTPTR  (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */
01243 #define BS_SPI_SR_POPNXTPTR  (4U)          /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */
01244 
01245 /*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
01246 #define BR_SPI_SR_POPNXTPTR(x) (UNION_READ(hw_spi_sr_t, HW_SPI_SR_ADDR(x), U, B.POPNXTPTR))
01247 /*@}*/
01248 
01249 /*!
01250  * @name Register SPI_SR, field RXCTR[7:4] (RO)
01251  *
01252  * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
01253  * every time the POPR is read. The RXCTR is incremented every time data is
01254  * transferred from the shift register to the RX FIFO.
01255  */
01256 /*@{*/
01257 #define BP_SPI_SR_RXCTR      (4U)          /*!< Bit position for SPI_SR_RXCTR. */
01258 #define BM_SPI_SR_RXCTR      (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */
01259 #define BS_SPI_SR_RXCTR      (4U)          /*!< Bit field size in bits for SPI_SR_RXCTR. */
01260 
01261 /*! @brief Read current value of the SPI_SR_RXCTR field. */
01262 #define BR_SPI_SR_RXCTR(x)   (UNION_READ(hw_spi_sr_t, HW_SPI_SR_ADDR(x), U, B.RXCTR))
01263 /*@}*/
01264 
01265 /*!
01266  * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
01267  *
01268  * Indicates which TX FIFO entry is transmitted during the next transfer. The
01269  * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
01270  * the shift register.
01271  */
01272 /*@{*/
01273 #define BP_SPI_SR_TXNXTPTR   (8U)          /*!< Bit position for SPI_SR_TXNXTPTR. */
01274 #define BM_SPI_SR_TXNXTPTR   (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */
01275 #define BS_SPI_SR_TXNXTPTR   (4U)          /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */
01276 
01277 /*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
01278 #define BR_SPI_SR_TXNXTPTR(x) (UNION_READ(hw_spi_sr_t, HW_SPI_SR_ADDR(x), U, B.TXNXTPTR))
01279 /*@}*/
01280 
01281 /*!
01282  * @name Register SPI_SR, field TXCTR[15:12] (RO)
01283  *
01284  * Indicates the number of valid entries in the TX FIFO. The TXCTR is
01285  * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
01286  * command is executed and the SPI data is transferred to the shift register.
01287  */
01288 /*@{*/
01289 #define BP_SPI_SR_TXCTR      (12U)         /*!< Bit position for SPI_SR_TXCTR. */
01290 #define BM_SPI_SR_TXCTR      (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */
01291 #define BS_SPI_SR_TXCTR      (4U)          /*!< Bit field size in bits for SPI_SR_TXCTR. */
01292 
01293 /*! @brief Read current value of the SPI_SR_TXCTR field. */
01294 #define BR_SPI_SR_TXCTR(x)   (UNION_READ(hw_spi_sr_t, HW_SPI_SR_ADDR(x), U, B.TXCTR))
01295 /*@}*/
01296 
01297 /*!
01298  * @name Register SPI_SR, field RFDF[17] (W1C)
01299  *
01300  * Provides a method for the module to request that entries be removed from the
01301  * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
01302  * cleared by writing 1 to it or by acknowledgement from the DMA controller when
01303  * the RX FIFO is empty.
01304  *
01305  * Values:
01306  * - 0 - RX FIFO is empty.
01307  * - 1 - RX FIFO is not empty.
01308  */
01309 /*@{*/
01310 #define BP_SPI_SR_RFDF       (17U)         /*!< Bit position for SPI_SR_RFDF. */
01311 #define BM_SPI_SR_RFDF       (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */
01312 #define BS_SPI_SR_RFDF       (1U)          /*!< Bit field size in bits for SPI_SR_RFDF. */
01313 
01314 /*! @brief Read current value of the SPI_SR_RFDF field. */
01315 #define BR_SPI_SR_RFDF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF)))
01316 
01317 /*! @brief Format value for bitfield SPI_SR_RFDF. */
01318 #define BF_SPI_SR_RFDF(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF)
01319 
01320 /*! @brief Set the RFDF field to a new value. */
01321 #define BW_SPI_SR_RFDF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF), v))
01322 /*@}*/
01323 
01324 /*!
01325  * @name Register SPI_SR, field RFOF[19] (W1C)
01326  *
01327  * Indicates an overflow condition in the RX FIFO. The field is set when the RX
01328  * FIFO and shift register are full and a transfer is initiated. The bit remains
01329  * set until it is cleared by writing a 1 to it.
01330  *
01331  * Values:
01332  * - 0 - No Rx FIFO overflow.
01333  * - 1 - Rx FIFO overflow has occurred.
01334  */
01335 /*@{*/
01336 #define BP_SPI_SR_RFOF       (19U)         /*!< Bit position for SPI_SR_RFOF. */
01337 #define BM_SPI_SR_RFOF       (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */
01338 #define BS_SPI_SR_RFOF       (1U)          /*!< Bit field size in bits for SPI_SR_RFOF. */
01339 
01340 /*! @brief Read current value of the SPI_SR_RFOF field. */
01341 #define BR_SPI_SR_RFOF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF)))
01342 
01343 /*! @brief Format value for bitfield SPI_SR_RFOF. */
01344 #define BF_SPI_SR_RFOF(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF)
01345 
01346 /*! @brief Set the RFOF field to a new value. */
01347 #define BW_SPI_SR_RFOF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF), v))
01348 /*@}*/
01349 
01350 /*!
01351  * @name Register SPI_SR, field TFFF[25] (W1C)
01352  *
01353  * Provides a method for the module to request more entries to be added to the
01354  * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
01355  * cleared by writing 1 to it or by acknowledgement from the DMA controller to
01356  * the TX FIFO full request.
01357  *
01358  * Values:
01359  * - 0 - TX FIFO is full.
01360  * - 1 - TX FIFO is not full.
01361  */
01362 /*@{*/
01363 #define BP_SPI_SR_TFFF       (25U)         /*!< Bit position for SPI_SR_TFFF. */
01364 #define BM_SPI_SR_TFFF       (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */
01365 #define BS_SPI_SR_TFFF       (1U)          /*!< Bit field size in bits for SPI_SR_TFFF. */
01366 
01367 /*! @brief Read current value of the SPI_SR_TFFF field. */
01368 #define BR_SPI_SR_TFFF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF)))
01369 
01370 /*! @brief Format value for bitfield SPI_SR_TFFF. */
01371 #define BF_SPI_SR_TFFF(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF)
01372 
01373 /*! @brief Set the TFFF field to a new value. */
01374 #define BW_SPI_SR_TFFF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF), v))
01375 /*@}*/
01376 
01377 /*!
01378  * @name Register SPI_SR, field TFUF[27] (W1C)
01379  *
01380  * Indicates an underflow condition in the TX FIFO. The transmit underflow
01381  * condition is detected only for SPI blocks operating in Slave mode and SPI
01382  * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
01383  * is empty and an external SPI master initiates a transfer. The TFUF bit remains
01384  * set until cleared by writing 1 to it.
01385  *
01386  * Values:
01387  * - 0 - No TX FIFO underflow.
01388  * - 1 - TX FIFO underflow has occurred.
01389  */
01390 /*@{*/
01391 #define BP_SPI_SR_TFUF       (27U)         /*!< Bit position for SPI_SR_TFUF. */
01392 #define BM_SPI_SR_TFUF       (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */
01393 #define BS_SPI_SR_TFUF       (1U)          /*!< Bit field size in bits for SPI_SR_TFUF. */
01394 
01395 /*! @brief Read current value of the SPI_SR_TFUF field. */
01396 #define BR_SPI_SR_TFUF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF)))
01397 
01398 /*! @brief Format value for bitfield SPI_SR_TFUF. */
01399 #define BF_SPI_SR_TFUF(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF)
01400 
01401 /*! @brief Set the TFUF field to a new value. */
01402 #define BW_SPI_SR_TFUF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF), v))
01403 /*@}*/
01404 
01405 /*!
01406  * @name Register SPI_SR, field EOQF[28] (W1C)
01407  *
01408  * Indicates that the last entry in a queue has been transmitted when the module
01409  * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
01410  * set in the command halfword and the end of the transfer is reached. The EOQF
01411  * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
01412  * the TXRXS bit is automatically cleared.
01413  *
01414  * Values:
01415  * - 0 - EOQ is not set in the executing command.
01416  * - 1 - EOQ is set in the executing SPI command.
01417  */
01418 /*@{*/
01419 #define BP_SPI_SR_EOQF       (28U)         /*!< Bit position for SPI_SR_EOQF. */
01420 #define BM_SPI_SR_EOQF       (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */
01421 #define BS_SPI_SR_EOQF       (1U)          /*!< Bit field size in bits for SPI_SR_EOQF. */
01422 
01423 /*! @brief Read current value of the SPI_SR_EOQF field. */
01424 #define BR_SPI_SR_EOQF(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF)))
01425 
01426 /*! @brief Format value for bitfield SPI_SR_EOQF. */
01427 #define BF_SPI_SR_EOQF(v)    ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF)
01428 
01429 /*! @brief Set the EOQF field to a new value. */
01430 #define BW_SPI_SR_EOQF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF), v))
01431 /*@}*/
01432 
01433 /*!
01434  * @name Register SPI_SR, field TXRXS[30] (W1C)
01435  *
01436  * Reflects the run status of the module.
01437  *
01438  * Values:
01439  * - 0 - Transmit and receive operations are disabled (The module is in Stopped
01440  *     state).
01441  * - 1 - Transmit and receive operations are enabled (The module is in Running
01442  *     state).
01443  */
01444 /*@{*/
01445 #define BP_SPI_SR_TXRXS      (30U)         /*!< Bit position for SPI_SR_TXRXS. */
01446 #define BM_SPI_SR_TXRXS      (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */
01447 #define BS_SPI_SR_TXRXS      (1U)          /*!< Bit field size in bits for SPI_SR_TXRXS. */
01448 
01449 /*! @brief Read current value of the SPI_SR_TXRXS field. */
01450 #define BR_SPI_SR_TXRXS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS)))
01451 
01452 /*! @brief Format value for bitfield SPI_SR_TXRXS. */
01453 #define BF_SPI_SR_TXRXS(v)   ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS)
01454 
01455 /*! @brief Set the TXRXS field to a new value. */
01456 #define BW_SPI_SR_TXRXS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS), v))
01457 /*@}*/
01458 
01459 /*!
01460  * @name Register SPI_SR, field TCF[31] (W1C)
01461  *
01462  * Indicates that all bits in a frame have been shifted out. TCF remains set
01463  * until it is cleared by writing a 1 to it.
01464  *
01465  * Values:
01466  * - 0 - Transfer not complete.
01467  * - 1 - Transfer complete.
01468  */
01469 /*@{*/
01470 #define BP_SPI_SR_TCF        (31U)         /*!< Bit position for SPI_SR_TCF. */
01471 #define BM_SPI_SR_TCF        (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */
01472 #define BS_SPI_SR_TCF        (1U)          /*!< Bit field size in bits for SPI_SR_TCF. */
01473 
01474 /*! @brief Read current value of the SPI_SR_TCF field. */
01475 #define BR_SPI_SR_TCF(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF)))
01476 
01477 /*! @brief Format value for bitfield SPI_SR_TCF. */
01478 #define BF_SPI_SR_TCF(v)     ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF)
01479 
01480 /*! @brief Set the TCF field to a new value. */
01481 #define BW_SPI_SR_TCF(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF), v))
01482 /*@}*/
01483 
01484 /*******************************************************************************
01485  * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
01486  ******************************************************************************/
01487 
01488 /*!
01489  * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
01490  *
01491  * Reset value: 0x00000000U
01492  *
01493  * RSER controls DMA and interrupt requests. Do not write to the RSER while the
01494  * module is in the Running state.
01495  */
01496 typedef union _hw_spi_rser
01497 {
01498     uint32_t U;
01499     struct _hw_spi_rser_bitfields
01500     {
01501         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
01502         uint32_t RFDF_DIRS : 1;        /*!< [16] Receive FIFO Drain DMA or Interrupt
01503                                         * Request Select */
01504         uint32_t RFDF_RE : 1;          /*!< [17] Receive FIFO Drain Request Enable */
01505         uint32_t RESERVED1 : 1;        /*!< [18]  */
01506         uint32_t RFOF_RE : 1;          /*!< [19] Receive FIFO Overflow Request Enable
01507                                         * */
01508         uint32_t RESERVED2 : 4;        /*!< [23:20]  */
01509         uint32_t TFFF_DIRS : 1;        /*!< [24] Transmit FIFO Fill DMA or Interrupt
01510                                         * Request Select */
01511         uint32_t TFFF_RE : 1;          /*!< [25] Transmit FIFO Fill Request Enable */
01512         uint32_t RESERVED3 : 1;        /*!< [26]  */
01513         uint32_t TFUF_RE : 1;          /*!< [27] Transmit FIFO Underflow Request
01514                                         * Enable */
01515         uint32_t EOQF_RE : 1;          /*!< [28] Finished Request Enable */
01516         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
01517         uint32_t TCF_RE : 1;           /*!< [31] Transmission Complete Request Enable */
01518     } B;
01519 } hw_spi_rser_t;
01520 
01521 /*!
01522  * @name Constants and macros for entire SPI_RSER register
01523  */
01524 /*@{*/
01525 #define HW_SPI_RSER_ADDR(x)      ((x) + 0x30U)
01526 
01527 #define HW_SPI_RSER(x)           (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
01528 #define HW_SPI_RSER_RD(x)        (ADDRESS_READ(hw_spi_rser_t, HW_SPI_RSER_ADDR(x)))
01529 #define HW_SPI_RSER_WR(x, v)     (ADDRESS_WRITE(hw_spi_rser_t, HW_SPI_RSER_ADDR(x), v))
01530 #define HW_SPI_RSER_SET(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) |  (v)))
01531 #define HW_SPI_RSER_CLR(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
01532 #define HW_SPI_RSER_TOG(x, v)    (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^  (v)))
01533 /*@}*/
01534 
01535 /*
01536  * Constants & macros for individual SPI_RSER bitfields
01537  */
01538 
01539 /*!
01540  * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
01541  *
01542  * Selects between generating a DMA request or an interrupt request. When the
01543  * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
01544  * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
01545  *
01546  * Values:
01547  * - 0 - Interrupt request.
01548  * - 1 - DMA request.
01549  */
01550 /*@{*/
01551 #define BP_SPI_RSER_RFDF_DIRS (16U)        /*!< Bit position for SPI_RSER_RFDF_DIRS. */
01552 #define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */
01553 #define BS_SPI_RSER_RFDF_DIRS (1U)         /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */
01554 
01555 /*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
01556 #define BR_SPI_RSER_RFDF_DIRS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS)))
01557 
01558 /*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */
01559 #define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS)
01560 
01561 /*! @brief Set the RFDF_DIRS field to a new value. */
01562 #define BW_SPI_RSER_RFDF_DIRS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS), v))
01563 /*@}*/
01564 
01565 /*!
01566  * @name Register SPI_RSER, field RFDF_RE[17] (RW)
01567  *
01568  * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
01569  * selects between generating an interrupt request or a DMA request.
01570  *
01571  * Values:
01572  * - 0 - RFDF interrupt or DMA requests are disabled.
01573  * - 1 - RFDF interrupt or DMA requests are enabled.
01574  */
01575 /*@{*/
01576 #define BP_SPI_RSER_RFDF_RE  (17U)         /*!< Bit position for SPI_RSER_RFDF_RE. */
01577 #define BM_SPI_RSER_RFDF_RE  (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */
01578 #define BS_SPI_RSER_RFDF_RE  (1U)          /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */
01579 
01580 /*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
01581 #define BR_SPI_RSER_RFDF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE)))
01582 
01583 /*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */
01584 #define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE)
01585 
01586 /*! @brief Set the RFDF_RE field to a new value. */
01587 #define BW_SPI_RSER_RFDF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE), v))
01588 /*@}*/
01589 
01590 /*!
01591  * @name Register SPI_RSER, field RFOF_RE[19] (RW)
01592  *
01593  * Enables the RFOF flag in the SR to generate an interrupt request.
01594  *
01595  * Values:
01596  * - 0 - RFOF interrupt requests are disabled.
01597  * - 1 - RFOF interrupt requests are enabled.
01598  */
01599 /*@{*/
01600 #define BP_SPI_RSER_RFOF_RE  (19U)         /*!< Bit position for SPI_RSER_RFOF_RE. */
01601 #define BM_SPI_RSER_RFOF_RE  (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */
01602 #define BS_SPI_RSER_RFOF_RE  (1U)          /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */
01603 
01604 /*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
01605 #define BR_SPI_RSER_RFOF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE)))
01606 
01607 /*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */
01608 #define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE)
01609 
01610 /*! @brief Set the RFOF_RE field to a new value. */
01611 #define BW_SPI_RSER_RFOF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE), v))
01612 /*@}*/
01613 
01614 /*!
01615  * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
01616  *
01617  * Selects between generating a DMA request or an interrupt request. When
01618  * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
01619  * interrupt request or a DMA request.
01620  *
01621  * Values:
01622  * - 0 - TFFF flag generates interrupt requests.
01623  * - 1 - TFFF flag generates DMA requests.
01624  */
01625 /*@{*/
01626 #define BP_SPI_RSER_TFFF_DIRS (24U)        /*!< Bit position for SPI_RSER_TFFF_DIRS. */
01627 #define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */
01628 #define BS_SPI_RSER_TFFF_DIRS (1U)         /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */
01629 
01630 /*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
01631 #define BR_SPI_RSER_TFFF_DIRS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS)))
01632 
01633 /*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */
01634 #define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS)
01635 
01636 /*! @brief Set the TFFF_DIRS field to a new value. */
01637 #define BW_SPI_RSER_TFFF_DIRS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS), v))
01638 /*@}*/
01639 
01640 /*!
01641  * @name Register SPI_RSER, field TFFF_RE[25] (RW)
01642  *
01643  * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
01644  * selects between generating an interrupt request or a DMA request.
01645  *
01646  * Values:
01647  * - 0 - TFFF interrupts or DMA requests are disabled.
01648  * - 1 - TFFF interrupts or DMA requests are enabled.
01649  */
01650 /*@{*/
01651 #define BP_SPI_RSER_TFFF_RE  (25U)         /*!< Bit position for SPI_RSER_TFFF_RE. */
01652 #define BM_SPI_RSER_TFFF_RE  (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */
01653 #define BS_SPI_RSER_TFFF_RE  (1U)          /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */
01654 
01655 /*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
01656 #define BR_SPI_RSER_TFFF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE)))
01657 
01658 /*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */
01659 #define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE)
01660 
01661 /*! @brief Set the TFFF_RE field to a new value. */
01662 #define BW_SPI_RSER_TFFF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE), v))
01663 /*@}*/
01664 
01665 /*!
01666  * @name Register SPI_RSER, field TFUF_RE[27] (RW)
01667  *
01668  * Enables the TFUF flag in the SR to generate an interrupt request.
01669  *
01670  * Values:
01671  * - 0 - TFUF interrupt requests are disabled.
01672  * - 1 - TFUF interrupt requests are enabled.
01673  */
01674 /*@{*/
01675 #define BP_SPI_RSER_TFUF_RE  (27U)         /*!< Bit position for SPI_RSER_TFUF_RE. */
01676 #define BM_SPI_RSER_TFUF_RE  (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */
01677 #define BS_SPI_RSER_TFUF_RE  (1U)          /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */
01678 
01679 /*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
01680 #define BR_SPI_RSER_TFUF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE)))
01681 
01682 /*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */
01683 #define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE)
01684 
01685 /*! @brief Set the TFUF_RE field to a new value. */
01686 #define BW_SPI_RSER_TFUF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE), v))
01687 /*@}*/
01688 
01689 /*!
01690  * @name Register SPI_RSER, field EOQF_RE[28] (RW)
01691  *
01692  * Enables the EOQF flag in the SR to generate an interrupt request.
01693  *
01694  * Values:
01695  * - 0 - EOQF interrupt requests are disabled.
01696  * - 1 - EOQF interrupt requests are enabled.
01697  */
01698 /*@{*/
01699 #define BP_SPI_RSER_EOQF_RE  (28U)         /*!< Bit position for SPI_RSER_EOQF_RE. */
01700 #define BM_SPI_RSER_EOQF_RE  (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */
01701 #define BS_SPI_RSER_EOQF_RE  (1U)          /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */
01702 
01703 /*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
01704 #define BR_SPI_RSER_EOQF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE)))
01705 
01706 /*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */
01707 #define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE)
01708 
01709 /*! @brief Set the EOQF_RE field to a new value. */
01710 #define BW_SPI_RSER_EOQF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE), v))
01711 /*@}*/
01712 
01713 /*!
01714  * @name Register SPI_RSER, field TCF_RE[31] (RW)
01715  *
01716  * Enables TCF flag in the SR to generate an interrupt request.
01717  *
01718  * Values:
01719  * - 0 - TCF interrupt requests are disabled.
01720  * - 1 - TCF interrupt requests are enabled.
01721  */
01722 /*@{*/
01723 #define BP_SPI_RSER_TCF_RE   (31U)         /*!< Bit position for SPI_RSER_TCF_RE. */
01724 #define BM_SPI_RSER_TCF_RE   (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */
01725 #define BS_SPI_RSER_TCF_RE   (1U)          /*!< Bit field size in bits for SPI_RSER_TCF_RE. */
01726 
01727 /*! @brief Read current value of the SPI_RSER_TCF_RE field. */
01728 #define BR_SPI_RSER_TCF_RE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE)))
01729 
01730 /*! @brief Format value for bitfield SPI_RSER_TCF_RE. */
01731 #define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE)
01732 
01733 /*! @brief Set the TCF_RE field to a new value. */
01734 #define BW_SPI_RSER_TCF_RE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE), v))
01735 /*@}*/
01736 
01737 /*******************************************************************************
01738  * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
01739  ******************************************************************************/
01740 
01741 /*!
01742  * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
01743  *
01744  * Reset value: 0x00000000U
01745  *
01746  * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
01747  * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
01748  * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
01749  * can be used as data, supporting up to 32-bit frame operation. A read access
01750  * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
01751  * writing to this register does not update the FIFO. Therefore, any reads performed
01752  * while the module is disabled return the last PUSHR write performed while the
01753  * module was still enabled.
01754  */
01755 typedef union _hw_spi_pushr
01756 {
01757     uint32_t U;
01758     struct _hw_spi_pushr_bitfields
01759     {
01760         uint32_t TXDATA : 16;          /*!< [15:0] Transmit Data */
01761         uint32_t PCS : 6;              /*!< [21:16]  */
01762         uint32_t RESERVED0 : 4;        /*!< [25:22]  */
01763         uint32_t CTCNT : 1;            /*!< [26] Clear Transfer Counter */
01764         uint32_t EOQ : 1;              /*!< [27] End Of Queue */
01765         uint32_t CTAS : 3;             /*!< [30:28] Clock and Transfer Attributes Select
01766                                         * */
01767         uint32_t CONT : 1;             /*!< [31] Continuous Peripheral Chip Select Enable
01768                                         * */
01769     } B;
01770 } hw_spi_pushr_t;
01771 
01772 /*!
01773  * @name Constants and macros for entire SPI_PUSHR register
01774  */
01775 /*@{*/
01776 #define HW_SPI_PUSHR_ADDR(x)     ((x) + 0x34U)
01777 
01778 #define HW_SPI_PUSHR(x)          (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
01779 #define HW_SPI_PUSHR_RD(x)       (ADDRESS_READ(hw_spi_pushr_t, HW_SPI_PUSHR_ADDR(x)))
01780 #define HW_SPI_PUSHR_WR(x, v)    (ADDRESS_WRITE(hw_spi_pushr_t, HW_SPI_PUSHR_ADDR(x), v))
01781 #define HW_SPI_PUSHR_SET(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) |  (v)))
01782 #define HW_SPI_PUSHR_CLR(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
01783 #define HW_SPI_PUSHR_TOG(x, v)   (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^  (v)))
01784 /*@}*/
01785 
01786 /*
01787  * Constants & macros for individual SPI_PUSHR bitfields
01788  */
01789 
01790 /*!
01791  * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
01792  *
01793  * Holds SPI data to be transferred according to the associated SPI command.
01794  */
01795 /*@{*/
01796 #define BP_SPI_PUSHR_TXDATA  (0U)          /*!< Bit position for SPI_PUSHR_TXDATA. */
01797 #define BM_SPI_PUSHR_TXDATA  (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */
01798 #define BS_SPI_PUSHR_TXDATA  (16U)         /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */
01799 
01800 /*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
01801 #define BR_SPI_PUSHR_TXDATA(x) (UNION_READ(hw_spi_pushr_t, HW_SPI_PUSHR_ADDR(x), U, B.TXDATA))
01802 
01803 /*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */
01804 #define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA)
01805 
01806 /*! @brief Set the TXDATA field to a new value. */
01807 #define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
01808 /*@}*/
01809 
01810 /*!
01811  * @name Register SPI_PUSHR, field PCS[21:16] (RW)
01812  *
01813  * Select which PCS signals are to be asserted for the transfer. Refer to the
01814  * chip configuration details for the number of PCS signals used in this MCU.
01815  *
01816  * Values:
01817  * - 0 - Negate the PCS[x] signal.
01818  * - 1 - Assert the PCS[x] signal.
01819  */
01820 /*@{*/
01821 #define BP_SPI_PUSHR_PCS     (16U)         /*!< Bit position for SPI_PUSHR_PCS. */
01822 #define BM_SPI_PUSHR_PCS     (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */
01823 #define BS_SPI_PUSHR_PCS     (6U)          /*!< Bit field size in bits for SPI_PUSHR_PCS. */
01824 
01825 /*! @brief Read current value of the SPI_PUSHR_PCS field. */
01826 #define BR_SPI_PUSHR_PCS(x)  (UNION_READ(hw_spi_pushr_t, HW_SPI_PUSHR_ADDR(x), U, B.PCS))
01827 
01828 /*! @brief Format value for bitfield SPI_PUSHR_PCS. */
01829 #define BF_SPI_PUSHR_PCS(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS)
01830 
01831 /*! @brief Set the PCS field to a new value. */
01832 #define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
01833 /*@}*/
01834 
01835 /*!
01836  * @name Register SPI_PUSHR, field CTCNT[26] (RW)
01837  *
01838  * Clears the TCNT field in the TCR register. The TCNT field is cleared before
01839  * the module starts transmitting the current SPI frame.
01840  *
01841  * Values:
01842  * - 0 - Do not clear the TCR[TCNT] field.
01843  * - 1 - Clear the TCR[TCNT] field.
01844  */
01845 /*@{*/
01846 #define BP_SPI_PUSHR_CTCNT   (26U)         /*!< Bit position for SPI_PUSHR_CTCNT. */
01847 #define BM_SPI_PUSHR_CTCNT   (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */
01848 #define BS_SPI_PUSHR_CTCNT   (1U)          /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */
01849 
01850 /*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
01851 #define BR_SPI_PUSHR_CTCNT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT)))
01852 
01853 /*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */
01854 #define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT)
01855 
01856 /*! @brief Set the CTCNT field to a new value. */
01857 #define BW_SPI_PUSHR_CTCNT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT), v))
01858 /*@}*/
01859 
01860 /*!
01861  * @name Register SPI_PUSHR, field EOQ[27] (RW)
01862  *
01863  * Host software uses this bit to signal to the module that the current SPI
01864  * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
01865  * SR is set.
01866  *
01867  * Values:
01868  * - 0 - The SPI data is not the last data to transfer.
01869  * - 1 - The SPI data is the last data to transfer.
01870  */
01871 /*@{*/
01872 #define BP_SPI_PUSHR_EOQ     (27U)         /*!< Bit position for SPI_PUSHR_EOQ. */
01873 #define BM_SPI_PUSHR_EOQ     (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */
01874 #define BS_SPI_PUSHR_EOQ     (1U)          /*!< Bit field size in bits for SPI_PUSHR_EOQ. */
01875 
01876 /*! @brief Read current value of the SPI_PUSHR_EOQ field. */
01877 #define BR_SPI_PUSHR_EOQ(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ)))
01878 
01879 /*! @brief Format value for bitfield SPI_PUSHR_EOQ. */
01880 #define BF_SPI_PUSHR_EOQ(v)  ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ)
01881 
01882 /*! @brief Set the EOQ field to a new value. */
01883 #define BW_SPI_PUSHR_EOQ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ), v))
01884 /*@}*/
01885 
01886 /*!
01887  * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
01888  *
01889  * Selects which CTAR to use in master mode to specify the transfer attributes
01890  * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
01891  * configuration details to determine how many CTARs this device has. You should
01892  * not program a value in this field for a register that is not present.
01893  *
01894  * Values:
01895  * - 000 - CTAR0
01896  * - 001 - CTAR1
01897  * - 010 - Reserved
01898  * - 011 - Reserved
01899  * - 100 - Reserved
01900  * - 101 - Reserved
01901  * - 110 - Reserved
01902  * - 111 - Reserved
01903  */
01904 /*@{*/
01905 #define BP_SPI_PUSHR_CTAS    (28U)         /*!< Bit position for SPI_PUSHR_CTAS. */
01906 #define BM_SPI_PUSHR_CTAS    (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */
01907 #define BS_SPI_PUSHR_CTAS    (3U)          /*!< Bit field size in bits for SPI_PUSHR_CTAS. */
01908 
01909 /*! @brief Read current value of the SPI_PUSHR_CTAS field. */
01910 #define BR_SPI_PUSHR_CTAS(x) (UNION_READ(hw_spi_pushr_t, HW_SPI_PUSHR_ADDR(x), U, B.CTAS))
01911 
01912 /*! @brief Format value for bitfield SPI_PUSHR_CTAS. */
01913 #define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS)
01914 
01915 /*! @brief Set the CTAS field to a new value. */
01916 #define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
01917 /*@}*/
01918 
01919 /*!
01920  * @name Register SPI_PUSHR, field CONT[31] (RW)
01921  *
01922  * Selects a continuous selection format. The bit is used in SPI Master mode.
01923  * The bit enables the selected PCS signals to remain asserted between transfers.
01924  *
01925  * Values:
01926  * - 0 - Return PCSn signals to their inactive state between transfers.
01927  * - 1 - Keep PCSn signals asserted between transfers.
01928  */
01929 /*@{*/
01930 #define BP_SPI_PUSHR_CONT    (31U)         /*!< Bit position for SPI_PUSHR_CONT. */
01931 #define BM_SPI_PUSHR_CONT    (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */
01932 #define BS_SPI_PUSHR_CONT    (1U)          /*!< Bit field size in bits for SPI_PUSHR_CONT. */
01933 
01934 /*! @brief Read current value of the SPI_PUSHR_CONT field. */
01935 #define BR_SPI_PUSHR_CONT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT)))
01936 
01937 /*! @brief Format value for bitfield SPI_PUSHR_CONT. */
01938 #define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT)
01939 
01940 /*! @brief Set the CONT field to a new value. */
01941 #define BW_SPI_PUSHR_CONT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT), v))
01942 /*@}*/
01943 /*******************************************************************************
01944  * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
01945  ******************************************************************************/
01946 
01947 /*!
01948  * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
01949  *
01950  * Reset value: 0x00000000U
01951  *
01952  * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
01953  * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
01954  * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
01955  * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
01956  * SPI Frame operation.
01957  */
01958 typedef union _hw_spi_pushr_slave
01959 {
01960     uint32_t U;
01961     struct _hw_spi_pushr_slave_bitfields
01962     {
01963         uint32_t TXDATA : 32;          /*!< [31:0] Transmit Data */
01964     } B;
01965 } hw_spi_pushr_slave_t;
01966 
01967 /*!
01968  * @name Constants and macros for entire SPI_PUSHR_SLAVE register
01969  */
01970 /*@{*/
01971 #define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U)
01972 
01973 #define HW_SPI_PUSHR_SLAVE(x)    (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
01974 #define HW_SPI_PUSHR_SLAVE_RD(x) (ADDRESS_READ(hw_spi_pushr_slave_t, HW_SPI_PUSHR_SLAVE_ADDR(x)))
01975 #define HW_SPI_PUSHR_SLAVE_WR(x, v) (ADDRESS_WRITE(hw_spi_pushr_slave_t, HW_SPI_PUSHR_SLAVE_ADDR(x), v))
01976 #define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) |  (v)))
01977 #define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
01978 #define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^  (v)))
01979 /*@}*/
01980 
01981 /*
01982  * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
01983  */
01984 
01985 /*!
01986  * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
01987  *
01988  * Holds SPI data to be transferred according to the associated SPI command.
01989  */
01990 /*@{*/
01991 #define BP_SPI_PUSHR_SLAVE_TXDATA (0U)     /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */
01992 #define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */
01993 #define BS_SPI_PUSHR_SLAVE_TXDATA (32U)    /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */
01994 
01995 /*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */
01996 #define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
01997 
01998 /*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */
01999 #define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA)
02000 
02001 /*! @brief Set the TXDATA field to a new value. */
02002 #define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
02003 /*@}*/
02004 
02005 /*******************************************************************************
02006  * HW_SPI_POPR - POP RX FIFO Register
02007  ******************************************************************************/
02008 
02009 /*!
02010  * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
02011  *
02012  * Reset value: 0x00000000U
02013  *
02014  * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
02015  * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
02016  * this register will generate a Transfer Error.
02017  */
02018 typedef union _hw_spi_popr
02019 {
02020     uint32_t U;
02021     struct _hw_spi_popr_bitfields
02022     {
02023         uint32_t RXDATA : 32;          /*!< [31:0] Received Data */
02024     } B;
02025 } hw_spi_popr_t;
02026 
02027 /*!
02028  * @name Constants and macros for entire SPI_POPR register
02029  */
02030 /*@{*/
02031 #define HW_SPI_POPR_ADDR(x)      ((x) + 0x38U)
02032 
02033 #define HW_SPI_POPR(x)           (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
02034 #define HW_SPI_POPR_RD(x)        (ADDRESS_READ(hw_spi_popr_t, HW_SPI_POPR_ADDR(x)))
02035 /*@}*/
02036 
02037 /*
02038  * Constants & macros for individual SPI_POPR bitfields
02039  */
02040 
02041 /*!
02042  * @name Register SPI_POPR, field RXDATA[31:0] (RO)
02043  *
02044  * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
02045  * Pointer points.
02046  */
02047 /*@{*/
02048 #define BP_SPI_POPR_RXDATA   (0U)          /*!< Bit position for SPI_POPR_RXDATA. */
02049 #define BM_SPI_POPR_RXDATA   (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */
02050 #define BS_SPI_POPR_RXDATA   (32U)         /*!< Bit field size in bits for SPI_POPR_RXDATA. */
02051 
02052 /*! @brief Read current value of the SPI_POPR_RXDATA field. */
02053 #define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
02054 /*@}*/
02055 
02056 /*******************************************************************************
02057  * HW_SPI_TXFRn - Transmit FIFO Registers
02058  ******************************************************************************/
02059 
02060 /*!
02061  * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
02062  *
02063  * Reset value: 0x00000000U
02064  *
02065  * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
02066  * Each register is an entry in the TX FIFO. The registers are read-only and
02067  * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
02068  * FIFO.
02069  */
02070 typedef union _hw_spi_txfrn
02071 {
02072     uint32_t U;
02073     struct _hw_spi_txfrn_bitfields
02074     {
02075         uint32_t TXDATA : 16;          /*!< [15:0] Transmit Data */
02076         uint32_t TXCMD_TXDATA : 16;    /*!< [31:16] Transmit Command or Transmit
02077                                         * Data */
02078     } B;
02079 } hw_spi_txfrn_t;
02080 
02081 /*!
02082  * @name Constants and macros for entire SPI_TXFRn register
02083  */
02084 /*@{*/
02085 #define HW_SPI_TXFRn_COUNT (4U)
02086 
02087 #define HW_SPI_TXFRn_ADDR(x, n)  ((x) + 0x3CU + (0x4U * (n)))
02088 
02089 #define HW_SPI_TXFRn(x, n)       (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
02090 #define HW_SPI_TXFRn_RD(x, n)    (ADDRESS_READ(hw_spi_txfrn_t, HW_SPI_TXFRn_ADDR(x, n)))
02091 /*@}*/
02092 
02093 /*
02094  * Constants & macros for individual SPI_TXFRn bitfields
02095  */
02096 
02097 /*!
02098  * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
02099  *
02100  * Contains the SPI data to be shifted out.
02101  */
02102 /*@{*/
02103 #define BP_SPI_TXFRn_TXDATA  (0U)          /*!< Bit position for SPI_TXFRn_TXDATA. */
02104 #define BM_SPI_TXFRn_TXDATA  (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */
02105 #define BS_SPI_TXFRn_TXDATA  (16U)         /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */
02106 
02107 /*! @brief Read current value of the SPI_TXFRn_TXDATA field. */
02108 #define BR_SPI_TXFRn_TXDATA(x, n) (UNION_READ(hw_spi_txfrn_t, HW_SPI_TXFRn_ADDR(x, n), U, B.TXDATA))
02109 /*@}*/
02110 
02111 /*!
02112  * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
02113  *
02114  * In Master mode the TXCMD field contains the command that sets the transfer
02115  * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
02116  * the SPI data to be shifted out.
02117  */
02118 /*@{*/
02119 #define BP_SPI_TXFRn_TXCMD_TXDATA (16U)    /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */
02120 #define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */
02121 #define BS_SPI_TXFRn_TXCMD_TXDATA (16U)    /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */
02122 
02123 /*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */
02124 #define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (UNION_READ(hw_spi_txfrn_t, HW_SPI_TXFRn_ADDR(x, n), U, B.TXCMD_TXDATA))
02125 /*@}*/
02126 
02127 /*******************************************************************************
02128  * HW_SPI_RXFRn - Receive FIFO Registers
02129  ******************************************************************************/
02130 
02131 /*!
02132  * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
02133  *
02134  * Reset value: 0x00000000U
02135  *
02136  * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
02137  * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
02138  * RXFRx registers does not alter the state of the RX FIFO.
02139  */
02140 typedef union _hw_spi_rxfrn
02141 {
02142     uint32_t U;
02143     struct _hw_spi_rxfrn_bitfields
02144     {
02145         uint32_t RXDATA : 32;          /*!< [31:0] Receive Data */
02146     } B;
02147 } hw_spi_rxfrn_t;
02148 
02149 /*!
02150  * @name Constants and macros for entire SPI_RXFRn register
02151  */
02152 /*@{*/
02153 #define HW_SPI_RXFRn_COUNT (4U)
02154 
02155 #define HW_SPI_RXFRn_ADDR(x, n)  ((x) + 0x7CU + (0x4U * (n)))
02156 
02157 #define HW_SPI_RXFRn(x, n)       (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
02158 #define HW_SPI_RXFRn_RD(x, n)    (ADDRESS_READ(hw_spi_rxfrn_t, HW_SPI_RXFRn_ADDR(x, n)))
02159 /*@}*/
02160 
02161 /*
02162  * Constants & macros for individual SPI_RXFRn bitfields
02163  */
02164 
02165 /*!
02166  * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
02167  *
02168  * Contains the received SPI data.
02169  */
02170 /*@{*/
02171 #define BP_SPI_RXFRn_RXDATA  (0U)          /*!< Bit position for SPI_RXFRn_RXDATA. */
02172 #define BM_SPI_RXFRn_RXDATA  (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */
02173 #define BS_SPI_RXFRn_RXDATA  (32U)         /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */
02174 
02175 /*! @brief Read current value of the SPI_RXFRn_RXDATA field. */
02176 #define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
02177 /*@}*/
02178 
02179 /*
02180 ** Start of section using anonymous unions
02181 */
02182 
02183 #if defined(__ARMCC_VERSION)
02184   #pragma push
02185   #pragma anon_unions
02186 #elif defined(__CWCC__)
02187   #pragma push
02188   #pragma cpp_extensions on
02189 #elif defined(__GNUC__)
02190   /* anonymous unions are enabled by default */
02191 #elif defined(__IAR_SYSTEMS_ICC__)
02192   #pragma language=extended
02193 #else
02194   #error Not supported compiler type
02195 #endif
02196 
02197 /*******************************************************************************
02198  * hw_spi_t - module struct
02199  ******************************************************************************/
02200 /*!
02201  * @brief All SPI module registers.
02202  */
02203 #pragma pack(1)
02204 typedef struct _hw_spi
02205 {
02206     __IO hw_spi_mcr_t MCR ;                 /*!< [0x0] Module Configuration Register */
02207     uint8_t _reserved0[4];
02208     __IO hw_spi_tcr_t TCR ;                 /*!< [0x8] Transfer Count Register */
02209     union {
02210         __IO hw_spi_ctarn_t CTARn [2];      /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */
02211         __IO hw_spi_ctarn_slave_t CTARn_SLAVE [1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */
02212     };
02213     uint8_t _reserved1[24];
02214     __IO hw_spi_sr_t SR ;                   /*!< [0x2C] Status Register */
02215     __IO hw_spi_rser_t RSER ;               /*!< [0x30] DMA/Interrupt Request Select and Enable Register */
02216     union {
02217         __IO hw_spi_pushr_t PUSHR ;         /*!< [0x34] PUSH TX FIFO Register In Master Mode */
02218         __IO hw_spi_pushr_slave_t PUSHR_SLAVE ; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */
02219     };
02220     __I hw_spi_popr_t POPR ;                /*!< [0x38] POP RX FIFO Register */
02221     __I hw_spi_txfrn_t TXFRn [4];           /*!< [0x3C] Transmit FIFO Registers */
02222     uint8_t _reserved2[48];
02223     __I hw_spi_rxfrn_t RXFRn [4];           /*!< [0x7C] Receive FIFO Registers */
02224 } hw_spi_t;
02225 #pragma pack()
02226 
02227 /*! @brief Macro to access all SPI registers. */
02228 /*! @param x SPI module instance base address. */
02229 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
02230  *     use the '&' operator, like <code>&HW_SPI(SPI0_BASE)</code>. */
02231 #define HW_SPI(x)      (*(hw_spi_t *)(x))
02232 
02233 /*
02234 ** End of section using anonymous unions
02235 */
02236 
02237 #if defined(__ARMCC_VERSION)
02238   #pragma pop
02239 #elif defined(__CWCC__)
02240   #pragma pop
02241 #elif defined(__GNUC__)
02242   /* leave anonymous unions enabled */
02243 #elif defined(__IAR_SYSTEMS_ICC__)
02244   #pragma language=default
02245 #else
02246   #error Not supported compiler type
02247 #endif
02248 
02249 #endif /* __HW_SPI_REGISTERS_H__ */
02250 /* EOF */