MK64F12_pmc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_PMC_REGISTERS_H__
00088 #define __HW_PMC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 PMC
00095  *
00096  * Power Management Controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
00100  * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
00101  * - HW_PMC_REGSC - Regulator Status And Control register
00102  *
00103  * - hw_pmc_t - Struct containing all module registers.
00104  */
00105 
00106 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
00107 
00108 /*******************************************************************************
00109  * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
00110  ******************************************************************************/
00111 
00112 /*!
00113  * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
00114  *
00115  * Reset value: 0x10U
00116  *
00117  * This register contains status and control bits to support the low voltage
00118  * detect function. This register should be written during the reset initialization
00119  * program to set the desired controls even if the desired settings are the same
00120  * as the reset settings. While the device is in the very low power or low
00121  * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
00122  * systems that must have LVD always on, configure the Power Mode Protection
00123  * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
00124  * low leakage modes from being enabled. See the device's data sheet for the
00125  * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
00126  * register's other bits are reset on Chip Reset Not VLLS. For more information
00127  * about these reset types, refer to the Reset section details.
00128  */
00129 typedef union _hw_pmc_lvdsc1
00130 {
00131     uint8_t U;
00132     struct _hw_pmc_lvdsc1_bitfields
00133     {
00134         uint8_t LVDV : 2;              /*!< [1:0] Low-Voltage Detect Voltage Select */
00135         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
00136         uint8_t LVDRE : 1;             /*!< [4] Low-Voltage Detect Reset Enable */
00137         uint8_t LVDIE : 1;             /*!< [5] Low-Voltage Detect Interrupt Enable */
00138         uint8_t LVDACK : 1;            /*!< [6] Low-Voltage Detect Acknowledge */
00139         uint8_t LVDF : 1;              /*!< [7] Low-Voltage Detect Flag */
00140     } B;
00141 } hw_pmc_lvdsc1_t;
00142 
00143 /*!
00144  * @name Constants and macros for entire PMC_LVDSC1 register
00145  */
00146 /*@{*/
00147 #define HW_PMC_LVDSC1_ADDR(x)    ((x) + 0x0U)
00148 
00149 #define HW_PMC_LVDSC1(x)         (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
00150 #define HW_PMC_LVDSC1_RD(x)      (ADDRESS_READ(hw_pmc_lvdsc1_t, HW_PMC_LVDSC1_ADDR(x)))
00151 #define HW_PMC_LVDSC1_WR(x, v)   (ADDRESS_WRITE(hw_pmc_lvdsc1_t, HW_PMC_LVDSC1_ADDR(x), v))
00152 #define HW_PMC_LVDSC1_SET(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) |  (v)))
00153 #define HW_PMC_LVDSC1_CLR(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
00154 #define HW_PMC_LVDSC1_TOG(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^  (v)))
00155 /*@}*/
00156 
00157 /*
00158  * Constants & macros for individual PMC_LVDSC1 bitfields
00159  */
00160 
00161 /*!
00162  * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
00163  *
00164  * Selects the LVD trip point voltage (V LVD ).
00165  *
00166  * Values:
00167  * - 00 - Low trip point selected (V LVD = V LVDL )
00168  * - 01 - High trip point selected (V LVD = V LVDH )
00169  * - 10 - Reserved
00170  * - 11 - Reserved
00171  */
00172 /*@{*/
00173 #define BP_PMC_LVDSC1_LVDV   (0U)          /*!< Bit position for PMC_LVDSC1_LVDV. */
00174 #define BM_PMC_LVDSC1_LVDV   (0x03U)       /*!< Bit mask for PMC_LVDSC1_LVDV. */
00175 #define BS_PMC_LVDSC1_LVDV   (2U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
00176 
00177 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
00178 #define BR_PMC_LVDSC1_LVDV(x) (UNION_READ(hw_pmc_lvdsc1_t, HW_PMC_LVDSC1_ADDR(x), U, B.LVDV))
00179 
00180 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
00181 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
00182 
00183 /*! @brief Set the LVDV field to a new value. */
00184 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
00185 /*@}*/
00186 
00187 /*!
00188  * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
00189  *
00190  * This write-once bit enables LVDF events to generate a hardware reset.
00191  * Additional writes are ignored.
00192  *
00193  * Values:
00194  * - 0 - LVDF does not generate hardware resets
00195  * - 1 - Force an MCU reset when LVDF = 1
00196  */
00197 /*@{*/
00198 #define BP_PMC_LVDSC1_LVDRE  (4U)          /*!< Bit position for PMC_LVDSC1_LVDRE. */
00199 #define BM_PMC_LVDSC1_LVDRE  (0x10U)       /*!< Bit mask for PMC_LVDSC1_LVDRE. */
00200 #define BS_PMC_LVDSC1_LVDRE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
00201 
00202 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
00203 #define BR_PMC_LVDSC1_LVDRE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE)))
00204 
00205 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
00206 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
00207 
00208 /*! @brief Set the LVDRE field to a new value. */
00209 #define BW_PMC_LVDSC1_LVDRE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE), v))
00210 /*@}*/
00211 
00212 /*!
00213  * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
00214  *
00215  * Enables hardware interrupt requests for LVDF.
00216  *
00217  * Values:
00218  * - 0 - Hardware interrupt disabled (use polling)
00219  * - 1 - Request a hardware interrupt when LVDF = 1
00220  */
00221 /*@{*/
00222 #define BP_PMC_LVDSC1_LVDIE  (5U)          /*!< Bit position for PMC_LVDSC1_LVDIE. */
00223 #define BM_PMC_LVDSC1_LVDIE  (0x20U)       /*!< Bit mask for PMC_LVDSC1_LVDIE. */
00224 #define BS_PMC_LVDSC1_LVDIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
00225 
00226 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
00227 #define BR_PMC_LVDSC1_LVDIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE)))
00228 
00229 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
00230 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
00231 
00232 /*! @brief Set the LVDIE field to a new value. */
00233 #define BW_PMC_LVDSC1_LVDIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE), v))
00234 /*@}*/
00235 
00236 /*!
00237  * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
00238  *
00239  * This write-only field is used to acknowledge low voltage detection errors.
00240  * Write 1 to clear LVDF. Reads always return 0.
00241  */
00242 /*@{*/
00243 #define BP_PMC_LVDSC1_LVDACK (6U)          /*!< Bit position for PMC_LVDSC1_LVDACK. */
00244 #define BM_PMC_LVDSC1_LVDACK (0x40U)       /*!< Bit mask for PMC_LVDSC1_LVDACK. */
00245 #define BS_PMC_LVDSC1_LVDACK (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
00246 
00247 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
00248 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
00249 
00250 /*! @brief Set the LVDACK field to a new value. */
00251 #define BW_PMC_LVDSC1_LVDACK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK), v))
00252 /*@}*/
00253 
00254 /*!
00255  * @name Register PMC_LVDSC1, field LVDF[7] (RO)
00256  *
00257  * This read-only status field indicates a low-voltage detect event.
00258  *
00259  * Values:
00260  * - 0 - Low-voltage event not detected
00261  * - 1 - Low-voltage event detected
00262  */
00263 /*@{*/
00264 #define BP_PMC_LVDSC1_LVDF   (7U)          /*!< Bit position for PMC_LVDSC1_LVDF. */
00265 #define BM_PMC_LVDSC1_LVDF   (0x80U)       /*!< Bit mask for PMC_LVDSC1_LVDF. */
00266 #define BS_PMC_LVDSC1_LVDF   (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
00267 
00268 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
00269 #define BR_PMC_LVDSC1_LVDF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF)))
00270 /*@}*/
00271 
00272 /*******************************************************************************
00273  * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
00274  ******************************************************************************/
00275 
00276 /*!
00277  * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
00278  *
00279  * Reset value: 0x00U
00280  *
00281  * This register contains status and control bits to support the low voltage
00282  * warning function. While the device is in the very low power or low leakage modes,
00283  * the LVD system is disabled regardless of LVDSC2 settings. See the device's
00284  * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
00285  * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
00286  * register are reset on Chip Reset Not VLLS. For more information about these
00287  * reset types, refer to the Reset section details.
00288  */
00289 typedef union _hw_pmc_lvdsc2
00290 {
00291     uint8_t U;
00292     struct _hw_pmc_lvdsc2_bitfields
00293     {
00294         uint8_t LVWV : 2;              /*!< [1:0] Low-Voltage Warning Voltage Select */
00295         uint8_t RESERVED0 : 3;         /*!< [4:2]  */
00296         uint8_t LVWIE : 1;             /*!< [5] Low-Voltage Warning Interrupt Enable */
00297         uint8_t LVWACK : 1;            /*!< [6] Low-Voltage Warning Acknowledge */
00298         uint8_t LVWF : 1;              /*!< [7] Low-Voltage Warning Flag */
00299     } B;
00300 } hw_pmc_lvdsc2_t;
00301 
00302 /*!
00303  * @name Constants and macros for entire PMC_LVDSC2 register
00304  */
00305 /*@{*/
00306 #define HW_PMC_LVDSC2_ADDR(x)    ((x) + 0x1U)
00307 
00308 #define HW_PMC_LVDSC2(x)         (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
00309 #define HW_PMC_LVDSC2_RD(x)      (ADDRESS_READ(hw_pmc_lvdsc2_t, HW_PMC_LVDSC2_ADDR(x)))
00310 #define HW_PMC_LVDSC2_WR(x, v)   (ADDRESS_WRITE(hw_pmc_lvdsc2_t, HW_PMC_LVDSC2_ADDR(x), v))
00311 #define HW_PMC_LVDSC2_SET(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) |  (v)))
00312 #define HW_PMC_LVDSC2_CLR(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
00313 #define HW_PMC_LVDSC2_TOG(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^  (v)))
00314 /*@}*/
00315 
00316 /*
00317  * Constants & macros for individual PMC_LVDSC2 bitfields
00318  */
00319 
00320 /*!
00321  * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
00322  *
00323  * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
00324  * depends on LVDSC1[LVDV].
00325  *
00326  * Values:
00327  * - 00 - Low trip point selected (VLVW = VLVW1)
00328  * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
00329  * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
00330  * - 11 - High trip point selected (VLVW = VLVW4)
00331  */
00332 /*@{*/
00333 #define BP_PMC_LVDSC2_LVWV   (0U)          /*!< Bit position for PMC_LVDSC2_LVWV. */
00334 #define BM_PMC_LVDSC2_LVWV   (0x03U)       /*!< Bit mask for PMC_LVDSC2_LVWV. */
00335 #define BS_PMC_LVDSC2_LVWV   (2U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
00336 
00337 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
00338 #define BR_PMC_LVDSC2_LVWV(x) (UNION_READ(hw_pmc_lvdsc2_t, HW_PMC_LVDSC2_ADDR(x), U, B.LVWV))
00339 
00340 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
00341 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
00342 
00343 /*! @brief Set the LVWV field to a new value. */
00344 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
00345 /*@}*/
00346 
00347 /*!
00348  * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
00349  *
00350  * Enables hardware interrupt requests for LVWF.
00351  *
00352  * Values:
00353  * - 0 - Hardware interrupt disabled (use polling)
00354  * - 1 - Request a hardware interrupt when LVWF = 1
00355  */
00356 /*@{*/
00357 #define BP_PMC_LVDSC2_LVWIE  (5U)          /*!< Bit position for PMC_LVDSC2_LVWIE. */
00358 #define BM_PMC_LVDSC2_LVWIE  (0x20U)       /*!< Bit mask for PMC_LVDSC2_LVWIE. */
00359 #define BS_PMC_LVDSC2_LVWIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
00360 
00361 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
00362 #define BR_PMC_LVDSC2_LVWIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE)))
00363 
00364 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
00365 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
00366 
00367 /*! @brief Set the LVWIE field to a new value. */
00368 #define BW_PMC_LVDSC2_LVWIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE), v))
00369 /*@}*/
00370 
00371 /*!
00372  * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
00373  *
00374  * This write-only field is used to acknowledge low voltage warning errors.
00375  * Write 1 to clear LVWF. Reads always return 0.
00376  */
00377 /*@{*/
00378 #define BP_PMC_LVDSC2_LVWACK (6U)          /*!< Bit position for PMC_LVDSC2_LVWACK. */
00379 #define BM_PMC_LVDSC2_LVWACK (0x40U)       /*!< Bit mask for PMC_LVDSC2_LVWACK. */
00380 #define BS_PMC_LVDSC2_LVWACK (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
00381 
00382 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
00383 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
00384 
00385 /*! @brief Set the LVWACK field to a new value. */
00386 #define BW_PMC_LVDSC2_LVWACK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK), v))
00387 /*@}*/
00388 
00389 /*!
00390  * @name Register PMC_LVDSC2, field LVWF[7] (RO)
00391  *
00392  * This read-only status field indicates a low-voltage warning event. LVWF is
00393  * set when VSupply transitions below the trip point, or after reset and VSupply is
00394  * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
00395  * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
00396  * LVWACK first.
00397  *
00398  * Values:
00399  * - 0 - Low-voltage warning event not detected
00400  * - 1 - Low-voltage warning event detected
00401  */
00402 /*@{*/
00403 #define BP_PMC_LVDSC2_LVWF   (7U)          /*!< Bit position for PMC_LVDSC2_LVWF. */
00404 #define BM_PMC_LVDSC2_LVWF   (0x80U)       /*!< Bit mask for PMC_LVDSC2_LVWF. */
00405 #define BS_PMC_LVDSC2_LVWF   (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
00406 
00407 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
00408 #define BR_PMC_LVDSC2_LVWF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF)))
00409 /*@}*/
00410 
00411 /*******************************************************************************
00412  * HW_PMC_REGSC - Regulator Status And Control register
00413  ******************************************************************************/
00414 
00415 /*!
00416  * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
00417  *
00418  * Reset value: 0x04U
00419  *
00420  * The PMC contains an internal voltage regulator. The voltage regulator design
00421  * uses a bandgap reference that is also available through a buffer as input to
00422  * certain internal peripherals, such as the CMP and ADC. The internal regulator
00423  * provides a status bit (REGONS) indicating the regulator is in run regulation.
00424  * This register is reset on Chip Reset Not VLLS and by reset types that trigger
00425  * Chip Reset not VLLS. See the Reset section details for more information.
00426  */
00427 typedef union _hw_pmc_regsc
00428 {
00429     uint8_t U;
00430     struct _hw_pmc_regsc_bitfields
00431     {
00432         uint8_t BGBE : 1;              /*!< [0] Bandgap Buffer Enable */
00433         uint8_t RESERVED0 : 1;         /*!< [1]  */
00434         uint8_t REGONS : 1;            /*!< [2] Regulator In Run Regulation Status */
00435         uint8_t ACKISO : 1;            /*!< [3] Acknowledge Isolation */
00436         uint8_t BGEN : 1;              /*!< [4] Bandgap Enable In VLPx Operation */
00437         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
00438     } B;
00439 } hw_pmc_regsc_t;
00440 
00441 /*!
00442  * @name Constants and macros for entire PMC_REGSC register
00443  */
00444 /*@{*/
00445 #define HW_PMC_REGSC_ADDR(x)     ((x) + 0x2U)
00446 
00447 #define HW_PMC_REGSC(x)          (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
00448 #define HW_PMC_REGSC_RD(x)       (ADDRESS_READ(hw_pmc_regsc_t, HW_PMC_REGSC_ADDR(x)))
00449 #define HW_PMC_REGSC_WR(x, v)    (ADDRESS_WRITE(hw_pmc_regsc_t, HW_PMC_REGSC_ADDR(x), v))
00450 #define HW_PMC_REGSC_SET(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) |  (v)))
00451 #define HW_PMC_REGSC_CLR(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
00452 #define HW_PMC_REGSC_TOG(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^  (v)))
00453 /*@}*/
00454 
00455 /*
00456  * Constants & macros for individual PMC_REGSC bitfields
00457  */
00458 
00459 /*!
00460  * @name Register PMC_REGSC, field BGBE[0] (RW)
00461  *
00462  * Enables the bandgap buffer.
00463  *
00464  * Values:
00465  * - 0 - Bandgap buffer not enabled
00466  * - 1 - Bandgap buffer enabled
00467  */
00468 /*@{*/
00469 #define BP_PMC_REGSC_BGBE    (0U)          /*!< Bit position for PMC_REGSC_BGBE. */
00470 #define BM_PMC_REGSC_BGBE    (0x01U)       /*!< Bit mask for PMC_REGSC_BGBE. */
00471 #define BS_PMC_REGSC_BGBE    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGBE. */
00472 
00473 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
00474 #define BR_PMC_REGSC_BGBE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE)))
00475 
00476 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
00477 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
00478 
00479 /*! @brief Set the BGBE field to a new value. */
00480 #define BW_PMC_REGSC_BGBE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE), v))
00481 /*@}*/
00482 
00483 /*!
00484  * @name Register PMC_REGSC, field REGONS[2] (RO)
00485  *
00486  * This read-only field provides the current status of the internal voltage
00487  * regulator.
00488  *
00489  * Values:
00490  * - 0 - Regulator is in stop regulation or in transition to/from it
00491  * - 1 - Regulator is in run regulation
00492  */
00493 /*@{*/
00494 #define BP_PMC_REGSC_REGONS  (2U)          /*!< Bit position for PMC_REGSC_REGONS. */
00495 #define BM_PMC_REGSC_REGONS  (0x04U)       /*!< Bit mask for PMC_REGSC_REGONS. */
00496 #define BS_PMC_REGSC_REGONS  (1U)          /*!< Bit field size in bits for PMC_REGSC_REGONS. */
00497 
00498 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
00499 #define BR_PMC_REGSC_REGONS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS)))
00500 /*@}*/
00501 
00502 /*!
00503  * @name Register PMC_REGSC, field ACKISO[3] (W1C)
00504  *
00505  * Reading this field indicates whether certain peripherals and the I/O pads are
00506  * in a latched state as a result of having been in a VLLS mode. Writing 1 to
00507  * this field when it is set releases the I/O pads and certain peripherals to their
00508  * normal run mode state. After recovering from a VLLS mode, user should restore
00509  * chip configuration before clearing ACKISO. In particular, pin configuration
00510  * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
00511  * being falsely set when ACKISO is cleared.
00512  *
00513  * Values:
00514  * - 0 - Peripherals and I/O pads are in normal run state.
00515  * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
00516  */
00517 /*@{*/
00518 #define BP_PMC_REGSC_ACKISO  (3U)          /*!< Bit position for PMC_REGSC_ACKISO. */
00519 #define BM_PMC_REGSC_ACKISO  (0x08U)       /*!< Bit mask for PMC_REGSC_ACKISO. */
00520 #define BS_PMC_REGSC_ACKISO  (1U)          /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
00521 
00522 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
00523 #define BR_PMC_REGSC_ACKISO(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO)))
00524 
00525 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
00526 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
00527 
00528 /*! @brief Set the ACKISO field to a new value. */
00529 #define BW_PMC_REGSC_ACKISO(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO), v))
00530 /*@}*/
00531 
00532 /*!
00533  * @name Register PMC_REGSC, field BGEN[4] (RW)
00534  *
00535  * BGEN controls whether the bandgap is enabled in lower power modes of
00536  * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
00537  * reference in low power modes of operation, set BGEN to continue to enable the
00538  * bandgap operation. When the bandgap voltage reference is not needed in low
00539  * power modes, clear BGEN to avoid excess power consumption.
00540  *
00541  * Values:
00542  * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
00543  * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
00544  */
00545 /*@{*/
00546 #define BP_PMC_REGSC_BGEN    (4U)          /*!< Bit position for PMC_REGSC_BGEN. */
00547 #define BM_PMC_REGSC_BGEN    (0x10U)       /*!< Bit mask for PMC_REGSC_BGEN. */
00548 #define BS_PMC_REGSC_BGEN    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGEN. */
00549 
00550 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
00551 #define BR_PMC_REGSC_BGEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN)))
00552 
00553 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
00554 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
00555 
00556 /*! @brief Set the BGEN field to a new value. */
00557 #define BW_PMC_REGSC_BGEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN), v))
00558 /*@}*/
00559 
00560 /*******************************************************************************
00561  * hw_pmc_t - module struct
00562  ******************************************************************************/
00563 /*!
00564  * @brief All PMC module registers.
00565  */
00566 #pragma pack(1)
00567 typedef struct _hw_pmc
00568 {
00569     __IO hw_pmc_lvdsc1_t LVDSC1 ;           /*!< [0x0] Low Voltage Detect Status And Control 1 register */
00570     __IO hw_pmc_lvdsc2_t LVDSC2 ;           /*!< [0x1] Low Voltage Detect Status And Control 2 register */
00571     __IO hw_pmc_regsc_t REGSC ;             /*!< [0x2] Regulator Status And Control register */
00572 } hw_pmc_t;
00573 #pragma pack()
00574 
00575 /*! @brief Macro to access all PMC registers. */
00576 /*! @param x PMC module instance base address. */
00577 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00578  *     use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
00579 #define HW_PMC(x)      (*(hw_pmc_t *)(x))
00580 
00581 #endif /* __HW_PMC_REGISTERS_H__ */
00582 /* EOF */