MK64F12_fb.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_FB_REGISTERS_H__
00088 #define __HW_FB_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 FB
00095  *
00096  * FlexBus external bus interface
00097  *
00098  * Registers defined in this header file:
00099  * - HW_FB_CSARn - Chip Select Address Register
00100  * - HW_FB_CSMRn - Chip Select Mask Register
00101  * - HW_FB_CSCRn - Chip Select Control Register
00102  * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
00103  *
00104  * - hw_fb_t - Struct containing all module registers.
00105  */
00106 
00107 #define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
00108 
00109 /*******************************************************************************
00110  * HW_FB_CSARn - Chip Select Address Register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_FB_CSARn - Chip Select Address Register (RW)
00115  *
00116  * Reset value: 0x00000000U
00117  *
00118  * Specifies the associated chip-select's base address.
00119  */
00120 typedef union _hw_fb_csarn
00121 {
00122     uint32_t U;
00123     struct _hw_fb_csarn_bitfields
00124     {
00125         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
00126         uint32_t BA : 16;              /*!< [31:16] Base Address */
00127     } B;
00128 } hw_fb_csarn_t;
00129 
00130 /*!
00131  * @name Constants and macros for entire FB_CSARn register
00132  */
00133 /*@{*/
00134 #define HW_FB_CSARn_COUNT (6U)
00135 
00136 #define HW_FB_CSARn_ADDR(x, n)   ((x) + 0x0U + (0xCU * (n)))
00137 
00138 #define HW_FB_CSARn(x, n)        (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
00139 #define HW_FB_CSARn_RD(x, n)     (ADDRESS_READ(hw_fb_csarn_t, HW_FB_CSARn_ADDR(x, n)))
00140 #define HW_FB_CSARn_WR(x, n, v)  (ADDRESS_WRITE(hw_fb_csarn_t, HW_FB_CSARn_ADDR(x, n), v))
00141 #define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) |  (v)))
00142 #define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
00143 #define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^  (v)))
00144 /*@}*/
00145 
00146 /*
00147  * Constants & macros for individual FB_CSARn bitfields
00148  */
00149 
00150 /*!
00151  * @name Register FB_CSARn, field BA[31:16] (RW)
00152  *
00153  * Defines the base address for memory dedicated to the associated chip-select.
00154  * BA is compared to bits 31-16 on the internal address bus to determine if the
00155  * associated chip-select's memory is being accessed. Because the FlexBus module
00156  * is one of the slaves connected to the crossbar switch, it is only accessible
00157  * within a certain memory range. See the chip memory map for the applicable
00158  * FlexBus "expansion" address range for which the chip-selects can be active. Set the
00159  * CSARn and CSMRn registers appropriately before accessing this region.
00160  */
00161 /*@{*/
00162 #define BP_FB_CSARn_BA       (16U)         /*!< Bit position for FB_CSARn_BA. */
00163 #define BM_FB_CSARn_BA       (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
00164 #define BS_FB_CSARn_BA       (16U)         /*!< Bit field size in bits for FB_CSARn_BA. */
00165 
00166 /*! @brief Read current value of the FB_CSARn_BA field. */
00167 #define BR_FB_CSARn_BA(x, n) (UNION_READ(hw_fb_csarn_t, HW_FB_CSARn_ADDR(x, n), U, B.BA))
00168 
00169 /*! @brief Format value for bitfield FB_CSARn_BA. */
00170 #define BF_FB_CSARn_BA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
00171 
00172 /*! @brief Set the BA field to a new value. */
00173 #define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
00174 /*@}*/
00175 /*******************************************************************************
00176  * HW_FB_CSMRn - Chip Select Mask Register
00177  ******************************************************************************/
00178 
00179 /*!
00180  * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
00181  *
00182  * Reset value: 0x00000000U
00183  *
00184  * Specifies the address mask and allowable access types for the associated
00185  * chip-select.
00186  */
00187 typedef union _hw_fb_csmrn
00188 {
00189     uint32_t U;
00190     struct _hw_fb_csmrn_bitfields
00191     {
00192         uint32_t V : 1;                /*!< [0] Valid */
00193         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
00194         uint32_t WP : 1;               /*!< [8] Write Protect */
00195         uint32_t RESERVED1 : 7;        /*!< [15:9]  */
00196         uint32_t BAM : 16;             /*!< [31:16] Base Address Mask */
00197     } B;
00198 } hw_fb_csmrn_t;
00199 
00200 /*!
00201  * @name Constants and macros for entire FB_CSMRn register
00202  */
00203 /*@{*/
00204 #define HW_FB_CSMRn_COUNT (6U)
00205 
00206 #define HW_FB_CSMRn_ADDR(x, n)   ((x) + 0x4U + (0xCU * (n)))
00207 
00208 #define HW_FB_CSMRn(x, n)        (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
00209 #define HW_FB_CSMRn_RD(x, n)     (ADDRESS_READ(hw_fb_csmrn_t, HW_FB_CSMRn_ADDR(x, n)))
00210 #define HW_FB_CSMRn_WR(x, n, v)  (ADDRESS_WRITE(hw_fb_csmrn_t, HW_FB_CSMRn_ADDR(x, n), v))
00211 #define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) |  (v)))
00212 #define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
00213 #define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^  (v)))
00214 /*@}*/
00215 
00216 /*
00217  * Constants & macros for individual FB_CSMRn bitfields
00218  */
00219 
00220 /*!
00221  * @name Register FB_CSMRn, field V[0] (RW)
00222  *
00223  * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
00224  * Programmed chip-selects do not assert until the V bit is 1b (except for
00225  * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
00226  * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
00227  * select initialization sequence to allow other chip selects to function as
00228  * programmed.
00229  *
00230  * Values:
00231  * - 0 - Chip-select is invalid.
00232  * - 1 - Chip-select is valid.
00233  */
00234 /*@{*/
00235 #define BP_FB_CSMRn_V        (0U)          /*!< Bit position for FB_CSMRn_V. */
00236 #define BM_FB_CSMRn_V        (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
00237 #define BS_FB_CSMRn_V        (1U)          /*!< Bit field size in bits for FB_CSMRn_V. */
00238 
00239 /*! @brief Read current value of the FB_CSMRn_V field. */
00240 #define BR_FB_CSMRn_V(x, n)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V)))
00241 
00242 /*! @brief Format value for bitfield FB_CSMRn_V. */
00243 #define BF_FB_CSMRn_V(v)     ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
00244 
00245 /*! @brief Set the V field to a new value. */
00246 #define BW_FB_CSMRn_V(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V), v))
00247 /*@}*/
00248 
00249 /*!
00250  * @name Register FB_CSMRn, field WP[8] (RW)
00251  *
00252  * Controls write accesses to the address range in the corresponding CSAR.
00253  *
00254  * Values:
00255  * - 0 - Write accesses are allowed.
00256  * - 1 - Write accesses are not allowed. Attempting to write to the range of
00257  *     addresses for which the WP bit is set results in a bus error termination of
00258  *     the internal cycle and no external cycle.
00259  */
00260 /*@{*/
00261 #define BP_FB_CSMRn_WP       (8U)          /*!< Bit position for FB_CSMRn_WP. */
00262 #define BM_FB_CSMRn_WP       (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
00263 #define BS_FB_CSMRn_WP       (1U)          /*!< Bit field size in bits for FB_CSMRn_WP. */
00264 
00265 /*! @brief Read current value of the FB_CSMRn_WP field. */
00266 #define BR_FB_CSMRn_WP(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP)))
00267 
00268 /*! @brief Format value for bitfield FB_CSMRn_WP. */
00269 #define BF_FB_CSMRn_WP(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
00270 
00271 /*! @brief Set the WP field to a new value. */
00272 #define BW_FB_CSMRn_WP(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP), v))
00273 /*@}*/
00274 
00275 /*!
00276  * @name Register FB_CSMRn, field BAM[31:16] (RW)
00277  *
00278  * Defines the associated chip-select's block size by masking address bits.
00279  *
00280  * Values:
00281  * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
00282  * - 1 - The corresponding address bit in CSAR is a don't care in the
00283  *     chip-select decode.
00284  */
00285 /*@{*/
00286 #define BP_FB_CSMRn_BAM      (16U)         /*!< Bit position for FB_CSMRn_BAM. */
00287 #define BM_FB_CSMRn_BAM      (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
00288 #define BS_FB_CSMRn_BAM      (16U)         /*!< Bit field size in bits for FB_CSMRn_BAM. */
00289 
00290 /*! @brief Read current value of the FB_CSMRn_BAM field. */
00291 #define BR_FB_CSMRn_BAM(x, n) (UNION_READ(hw_fb_csmrn_t, HW_FB_CSMRn_ADDR(x, n), U, B.BAM))
00292 
00293 /*! @brief Format value for bitfield FB_CSMRn_BAM. */
00294 #define BF_FB_CSMRn_BAM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
00295 
00296 /*! @brief Set the BAM field to a new value. */
00297 #define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
00298 /*@}*/
00299 /*******************************************************************************
00300  * HW_FB_CSCRn - Chip Select Control Register
00301  ******************************************************************************/
00302 
00303 /*!
00304  * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
00305  *
00306  * Reset value: 0x003FFC00U
00307  *
00308  * Controls the auto-acknowledge, address setup and hold times, port size, burst
00309  * capability, and number of wait states for the associated chip select. To
00310  * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
00311  * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
00312  * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
00313  * particular chip for information on the exact CSCR0 reset value.
00314  */
00315 typedef union _hw_fb_cscrn
00316 {
00317     uint32_t U;
00318     struct _hw_fb_cscrn_bitfields
00319     {
00320         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
00321         uint32_t BSTW : 1;             /*!< [3] Burst-Write Enable */
00322         uint32_t BSTR : 1;             /*!< [4] Burst-Read Enable */
00323         uint32_t BEM : 1;              /*!< [5] Byte-Enable Mode */
00324         uint32_t PS : 2;               /*!< [7:6] Port Size */
00325         uint32_t AA : 1;               /*!< [8] Auto-Acknowledge Enable */
00326         uint32_t BLS : 1;              /*!< [9] Byte-Lane Shift */
00327         uint32_t WS : 6;               /*!< [15:10] Wait States */
00328         uint32_t WRAH : 2;             /*!< [17:16] Write Address Hold or Deselect */
00329         uint32_t RDAH : 2;             /*!< [19:18] Read Address Hold or Deselect */
00330         uint32_t ASET : 2;             /*!< [21:20] Address Setup */
00331         uint32_t EXTS : 1;             /*!< [22]  */
00332         uint32_t SWSEN : 1;            /*!< [23] Secondary Wait State Enable */
00333         uint32_t RESERVED1 : 2;        /*!< [25:24]  */
00334         uint32_t SWS : 6;              /*!< [31:26] Secondary Wait States */
00335     } B;
00336 } hw_fb_cscrn_t;
00337 
00338 /*!
00339  * @name Constants and macros for entire FB_CSCRn register
00340  */
00341 /*@{*/
00342 #define HW_FB_CSCRn_COUNT (6U)
00343 
00344 #define HW_FB_CSCRn_ADDR(x, n)   ((x) + 0x8U + (0xCU * (n)))
00345 
00346 #define HW_FB_CSCRn(x, n)        (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
00347 #define HW_FB_CSCRn_RD(x, n)     (ADDRESS_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n)))
00348 #define HW_FB_CSCRn_WR(x, n, v)  (ADDRESS_WRITE(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), v))
00349 #define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) |  (v)))
00350 #define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
00351 #define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^  (v)))
00352 /*@}*/
00353 
00354 /*
00355  * Constants & macros for individual FB_CSCRn bitfields
00356  */
00357 
00358 /*!
00359  * @name Register FB_CSCRn, field BSTW[3] (RW)
00360  *
00361  * Specifies whether burst writes are enabled for memory associated with each
00362  * chip select.
00363  *
00364  * Values:
00365  * - 0 - Disabled. Data exceeding the specified port size is broken into
00366  *     individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
00367  *     port takes four byte writes.
00368  * - 1 - Enabled. Enables burst write of data larger than the specified port
00369  *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
00370  *     ports, and line writes to 8-, 16-, and 32-bit ports.
00371  */
00372 /*@{*/
00373 #define BP_FB_CSCRn_BSTW     (3U)          /*!< Bit position for FB_CSCRn_BSTW. */
00374 #define BM_FB_CSCRn_BSTW     (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
00375 #define BS_FB_CSCRn_BSTW     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTW. */
00376 
00377 /*! @brief Read current value of the FB_CSCRn_BSTW field. */
00378 #define BR_FB_CSCRn_BSTW(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW)))
00379 
00380 /*! @brief Format value for bitfield FB_CSCRn_BSTW. */
00381 #define BF_FB_CSCRn_BSTW(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
00382 
00383 /*! @brief Set the BSTW field to a new value. */
00384 #define BW_FB_CSCRn_BSTW(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW), v))
00385 /*@}*/
00386 
00387 /*!
00388  * @name Register FB_CSCRn, field BSTR[4] (RW)
00389  *
00390  * Specifies whether burst reads are enabled for memory associated with each
00391  * chip select.
00392  *
00393  * Values:
00394  * - 0 - Disabled. Data exceeding the specified port size is broken into
00395  *     individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
00396  *     port is broken into four 8-bit reads.
00397  * - 1 - Enabled. Enables data burst reads larger than the specified port size,
00398  *     including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
00399  *     ports, and line reads from 8-, 16-, and 32-bit ports.
00400  */
00401 /*@{*/
00402 #define BP_FB_CSCRn_BSTR     (4U)          /*!< Bit position for FB_CSCRn_BSTR. */
00403 #define BM_FB_CSCRn_BSTR     (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
00404 #define BS_FB_CSCRn_BSTR     (1U)          /*!< Bit field size in bits for FB_CSCRn_BSTR. */
00405 
00406 /*! @brief Read current value of the FB_CSCRn_BSTR field. */
00407 #define BR_FB_CSCRn_BSTR(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR)))
00408 
00409 /*! @brief Format value for bitfield FB_CSCRn_BSTR. */
00410 #define BF_FB_CSCRn_BSTR(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
00411 
00412 /*! @brief Set the BSTR field to a new value. */
00413 #define BW_FB_CSCRn_BSTR(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR), v))
00414 /*@}*/
00415 
00416 /*!
00417  * @name Register FB_CSCRn, field BEM[5] (RW)
00418  *
00419  * Specifies whether the corresponding FB_BE is asserted for read accesses.
00420  * Certain memories have byte enables that must be asserted during reads and writes.
00421  * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
00422  * of byte enable support for these SRAMs.
00423  *
00424  * Values:
00425  * - 0 - FB_BE is asserted for data write only.
00426  * - 1 - FB_BE is asserted for data read and write accesses.
00427  */
00428 /*@{*/
00429 #define BP_FB_CSCRn_BEM      (5U)          /*!< Bit position for FB_CSCRn_BEM. */
00430 #define BM_FB_CSCRn_BEM      (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
00431 #define BS_FB_CSCRn_BEM      (1U)          /*!< Bit field size in bits for FB_CSCRn_BEM. */
00432 
00433 /*! @brief Read current value of the FB_CSCRn_BEM field. */
00434 #define BR_FB_CSCRn_BEM(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM)))
00435 
00436 /*! @brief Format value for bitfield FB_CSCRn_BEM. */
00437 #define BF_FB_CSCRn_BEM(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
00438 
00439 /*! @brief Set the BEM field to a new value. */
00440 #define BW_FB_CSCRn_BEM(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM), v))
00441 /*@}*/
00442 
00443 /*!
00444  * @name Register FB_CSCRn, field PS[7:6] (RW)
00445  *
00446  * Specifies the data port width of the associated chip-select, and determines
00447  * where data is driven during write cycles and where data is sampled during read
00448  * cycles.
00449  *
00450  * Values:
00451  * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
00452  * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
00453  *     BLS is 0b, or FB_D[7:0] when BLS is 1b.
00454  */
00455 /*@{*/
00456 #define BP_FB_CSCRn_PS       (6U)          /*!< Bit position for FB_CSCRn_PS. */
00457 #define BM_FB_CSCRn_PS       (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
00458 #define BS_FB_CSCRn_PS       (2U)          /*!< Bit field size in bits for FB_CSCRn_PS. */
00459 
00460 /*! @brief Read current value of the FB_CSCRn_PS field. */
00461 #define BR_FB_CSCRn_PS(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.PS))
00462 
00463 /*! @brief Format value for bitfield FB_CSCRn_PS. */
00464 #define BF_FB_CSCRn_PS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
00465 
00466 /*! @brief Set the PS field to a new value. */
00467 #define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
00468 /*@}*/
00469 
00470 /*!
00471  * @name Register FB_CSCRn, field AA[8] (RW)
00472  *
00473  * Asserts the internal transfer acknowledge for accesses specified by the
00474  * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
00475  * asserts an external FB_TA before the wait-state countdown asserts the
00476  * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
00477  * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
00478  *
00479  * Values:
00480  * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
00481  *     terminated externally.
00482  * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
00483  */
00484 /*@{*/
00485 #define BP_FB_CSCRn_AA       (8U)          /*!< Bit position for FB_CSCRn_AA. */
00486 #define BM_FB_CSCRn_AA       (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
00487 #define BS_FB_CSCRn_AA       (1U)          /*!< Bit field size in bits for FB_CSCRn_AA. */
00488 
00489 /*! @brief Read current value of the FB_CSCRn_AA field. */
00490 #define BR_FB_CSCRn_AA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA)))
00491 
00492 /*! @brief Format value for bitfield FB_CSCRn_AA. */
00493 #define BF_FB_CSCRn_AA(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
00494 
00495 /*! @brief Set the AA field to a new value. */
00496 #define BW_FB_CSCRn_AA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA), v))
00497 /*@}*/
00498 
00499 /*!
00500  * @name Register FB_CSCRn, field BLS[9] (RW)
00501  *
00502  * Specifies if data on FB_AD appears left-aligned or right-aligned during the
00503  * data phase of a FlexBus access.
00504  *
00505  * Values:
00506  * - 0 - Not shifted. Data is left-aligned on FB_AD.
00507  * - 1 - Shifted. Data is right-aligned on FB_AD.
00508  */
00509 /*@{*/
00510 #define BP_FB_CSCRn_BLS      (9U)          /*!< Bit position for FB_CSCRn_BLS. */
00511 #define BM_FB_CSCRn_BLS      (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
00512 #define BS_FB_CSCRn_BLS      (1U)          /*!< Bit field size in bits for FB_CSCRn_BLS. */
00513 
00514 /*! @brief Read current value of the FB_CSCRn_BLS field. */
00515 #define BR_FB_CSCRn_BLS(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS)))
00516 
00517 /*! @brief Format value for bitfield FB_CSCRn_BLS. */
00518 #define BF_FB_CSCRn_BLS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
00519 
00520 /*! @brief Set the BLS field to a new value. */
00521 #define BW_FB_CSCRn_BLS(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS), v))
00522 /*@}*/
00523 
00524 /*!
00525  * @name Register FB_CSCRn, field WS[15:10] (RW)
00526  *
00527  * Specifies the number of wait states inserted after FlexBus asserts the
00528  * associated chip-select and before an internal transfer acknowledge is generated (WS
00529  * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
00530  */
00531 /*@{*/
00532 #define BP_FB_CSCRn_WS       (10U)         /*!< Bit position for FB_CSCRn_WS. */
00533 #define BM_FB_CSCRn_WS       (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
00534 #define BS_FB_CSCRn_WS       (6U)          /*!< Bit field size in bits for FB_CSCRn_WS. */
00535 
00536 /*! @brief Read current value of the FB_CSCRn_WS field. */
00537 #define BR_FB_CSCRn_WS(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.WS))
00538 
00539 /*! @brief Format value for bitfield FB_CSCRn_WS. */
00540 #define BF_FB_CSCRn_WS(v)    ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
00541 
00542 /*! @brief Set the WS field to a new value. */
00543 #define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
00544 /*@}*/
00545 
00546 /*!
00547  * @name Register FB_CSCRn, field WRAH[17:16] (RW)
00548  *
00549  * Controls the address, data, and attribute hold time after the termination of
00550  * a write cycle that hits in the associated chip-select's address space. The
00551  * hold time applies only at the end of a transfer. Therefore, during a burst
00552  * transfer or a transfer to a port size smaller than the transfer size, the hold time
00553  * is only added after the last bus cycle.
00554  *
00555  * Values:
00556  * - 00 - 1 cycle (default for all but FB_CS0 )
00557  * - 01 - 2 cycles
00558  * - 10 - 3 cycles
00559  * - 11 - 4 cycles (default for FB_CS0 )
00560  */
00561 /*@{*/
00562 #define BP_FB_CSCRn_WRAH     (16U)         /*!< Bit position for FB_CSCRn_WRAH. */
00563 #define BM_FB_CSCRn_WRAH     (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
00564 #define BS_FB_CSCRn_WRAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_WRAH. */
00565 
00566 /*! @brief Read current value of the FB_CSCRn_WRAH field. */
00567 #define BR_FB_CSCRn_WRAH(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.WRAH))
00568 
00569 /*! @brief Format value for bitfield FB_CSCRn_WRAH. */
00570 #define BF_FB_CSCRn_WRAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
00571 
00572 /*! @brief Set the WRAH field to a new value. */
00573 #define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
00574 /*@}*/
00575 
00576 /*!
00577  * @name Register FB_CSCRn, field RDAH[19:18] (RW)
00578  *
00579  * Controls the address and attribute hold time after the termination during a
00580  * read cycle that hits in the associated chip-select's address space. The hold
00581  * time applies only at the end of a transfer. Therefore, during a burst transfer
00582  * or a transfer to a port size smaller than the transfer size, the hold time is
00583  * only added after the last bus cycle. The number of cycles the address and
00584  * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
00585  *
00586  * Values:
00587  * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
00588  * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
00589  * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
00590  * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
00591  */
00592 /*@{*/
00593 #define BP_FB_CSCRn_RDAH     (18U)         /*!< Bit position for FB_CSCRn_RDAH. */
00594 #define BM_FB_CSCRn_RDAH     (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
00595 #define BS_FB_CSCRn_RDAH     (2U)          /*!< Bit field size in bits for FB_CSCRn_RDAH. */
00596 
00597 /*! @brief Read current value of the FB_CSCRn_RDAH field. */
00598 #define BR_FB_CSCRn_RDAH(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.RDAH))
00599 
00600 /*! @brief Format value for bitfield FB_CSCRn_RDAH. */
00601 #define BF_FB_CSCRn_RDAH(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
00602 
00603 /*! @brief Set the RDAH field to a new value. */
00604 #define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
00605 /*@}*/
00606 
00607 /*!
00608  * @name Register FB_CSCRn, field ASET[21:20] (RW)
00609  *
00610  * Controls when the chip-select is asserted with respect to assertion of a
00611  * valid address and attributes.
00612  *
00613  * Values:
00614  * - 00 - Assert FB_CSn on the first rising clock edge after the address is
00615  *     asserted (default for all but FB_CS0 ).
00616  * - 01 - Assert FB_CSn on the second rising clock edge after the address is
00617  *     asserted.
00618  * - 10 - Assert FB_CSn on the third rising clock edge after the address is
00619  *     asserted.
00620  * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
00621  *     asserted (default for FB_CS0 ).
00622  */
00623 /*@{*/
00624 #define BP_FB_CSCRn_ASET     (20U)         /*!< Bit position for FB_CSCRn_ASET. */
00625 #define BM_FB_CSCRn_ASET     (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
00626 #define BS_FB_CSCRn_ASET     (2U)          /*!< Bit field size in bits for FB_CSCRn_ASET. */
00627 
00628 /*! @brief Read current value of the FB_CSCRn_ASET field. */
00629 #define BR_FB_CSCRn_ASET(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.ASET))
00630 
00631 /*! @brief Format value for bitfield FB_CSCRn_ASET. */
00632 #define BF_FB_CSCRn_ASET(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
00633 
00634 /*! @brief Set the ASET field to a new value. */
00635 #define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
00636 /*@}*/
00637 
00638 /*!
00639  * @name Register FB_CSCRn, field EXTS[22] (RW)
00640  *
00641  * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
00642  * /FB_ALE is asserted.
00643  *
00644  * Values:
00645  * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
00646  * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
00647  *     edge after FB_CSn asserts.
00648  */
00649 /*@{*/
00650 #define BP_FB_CSCRn_EXTS     (22U)         /*!< Bit position for FB_CSCRn_EXTS. */
00651 #define BM_FB_CSCRn_EXTS     (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
00652 #define BS_FB_CSCRn_EXTS     (1U)          /*!< Bit field size in bits for FB_CSCRn_EXTS. */
00653 
00654 /*! @brief Read current value of the FB_CSCRn_EXTS field. */
00655 #define BR_FB_CSCRn_EXTS(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS)))
00656 
00657 /*! @brief Format value for bitfield FB_CSCRn_EXTS. */
00658 #define BF_FB_CSCRn_EXTS(v)  ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
00659 
00660 /*! @brief Set the EXTS field to a new value. */
00661 #define BW_FB_CSCRn_EXTS(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS), v))
00662 /*@}*/
00663 
00664 /*!
00665  * @name Register FB_CSCRn, field SWSEN[23] (RW)
00666  *
00667  * Values:
00668  * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
00669  *     an internal transfer acknowledge is generated for all transfers.
00670  * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
00671  *     an internal transfer acknowledge is generated for burst transfer
00672  *     secondary terminations.
00673  */
00674 /*@{*/
00675 #define BP_FB_CSCRn_SWSEN    (23U)         /*!< Bit position for FB_CSCRn_SWSEN. */
00676 #define BM_FB_CSCRn_SWSEN    (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
00677 #define BS_FB_CSCRn_SWSEN    (1U)          /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
00678 
00679 /*! @brief Read current value of the FB_CSCRn_SWSEN field. */
00680 #define BR_FB_CSCRn_SWSEN(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN)))
00681 
00682 /*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
00683 #define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
00684 
00685 /*! @brief Set the SWSEN field to a new value. */
00686 #define BW_FB_CSCRn_SWSEN(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN), v))
00687 /*@}*/
00688 
00689 /*!
00690  * @name Register FB_CSCRn, field SWS[31:26] (RW)
00691  *
00692  * Used only when the SWSEN bit is 1b. Specifies the number of wait states
00693  * inserted before an internal transfer acknowledge is generated for a burst transfer
00694  * (except for the first termination, which is controlled by WS).
00695  */
00696 /*@{*/
00697 #define BP_FB_CSCRn_SWS      (26U)         /*!< Bit position for FB_CSCRn_SWS. */
00698 #define BM_FB_CSCRn_SWS      (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
00699 #define BS_FB_CSCRn_SWS      (6U)          /*!< Bit field size in bits for FB_CSCRn_SWS. */
00700 
00701 /*! @brief Read current value of the FB_CSCRn_SWS field. */
00702 #define BR_FB_CSCRn_SWS(x, n) (UNION_READ(hw_fb_cscrn_t, HW_FB_CSCRn_ADDR(x, n), U, B.SWS))
00703 
00704 /*! @brief Format value for bitfield FB_CSCRn_SWS. */
00705 #define BF_FB_CSCRn_SWS(v)   ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
00706 
00707 /*! @brief Set the SWS field to a new value. */
00708 #define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
00709 /*@}*/
00710 
00711 /*******************************************************************************
00712  * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
00713  ******************************************************************************/
00714 
00715 /*!
00716  * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
00717  *
00718  * Reset value: 0x00000000U
00719  *
00720  * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
00721  * do any of the following: Write to a reserved address Write to a reserved
00722  * field in this register, or Access this register using a size other than 32 bits.
00723  */
00724 typedef union _hw_fb_cspmcr
00725 {
00726     uint32_t U;
00727     struct _hw_fb_cspmcr_bitfields
00728     {
00729         uint32_t RESERVED0 : 12;       /*!< [11:0]  */
00730         uint32_t GROUP5 : 4;           /*!< [15:12] FlexBus Signal Group 5 Multiplex
00731                                         * control */
00732         uint32_t GROUP4 : 4;           /*!< [19:16] FlexBus Signal Group 4 Multiplex
00733                                         * control */
00734         uint32_t GROUP3 : 4;           /*!< [23:20] FlexBus Signal Group 3 Multiplex
00735                                         * control */
00736         uint32_t GROUP2 : 4;           /*!< [27:24] FlexBus Signal Group 2 Multiplex
00737                                         * control */
00738         uint32_t GROUP1 : 4;           /*!< [31:28] FlexBus Signal Group 1 Multiplex
00739                                         * control */
00740     } B;
00741 } hw_fb_cspmcr_t;
00742 
00743 /*!
00744  * @name Constants and macros for entire FB_CSPMCR register
00745  */
00746 /*@{*/
00747 #define HW_FB_CSPMCR_ADDR(x)     ((x) + 0x60U)
00748 
00749 #define HW_FB_CSPMCR(x)          (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
00750 #define HW_FB_CSPMCR_RD(x)       (ADDRESS_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x)))
00751 #define HW_FB_CSPMCR_WR(x, v)    (ADDRESS_WRITE(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), v))
00752 #define HW_FB_CSPMCR_SET(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) |  (v)))
00753 #define HW_FB_CSPMCR_CLR(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
00754 #define HW_FB_CSPMCR_TOG(x, v)   (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^  (v)))
00755 /*@}*/
00756 
00757 /*
00758  * Constants & macros for individual FB_CSPMCR bitfields
00759  */
00760 
00761 /*!
00762  * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
00763  *
00764  * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
00765  * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
00766  * bus hangs during a transfer.
00767  *
00768  * Values:
00769  * - 0000 - FB_TA
00770  * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
00771  * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
00772  */
00773 /*@{*/
00774 #define BP_FB_CSPMCR_GROUP5  (12U)         /*!< Bit position for FB_CSPMCR_GROUP5. */
00775 #define BM_FB_CSPMCR_GROUP5  (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
00776 #define BS_FB_CSPMCR_GROUP5  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
00777 
00778 /*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
00779 #define BR_FB_CSPMCR_GROUP5(x) (UNION_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), U, B.GROUP5))
00780 
00781 /*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
00782 #define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
00783 
00784 /*! @brief Set the GROUP5 field to a new value. */
00785 #define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
00786 /*@}*/
00787 
00788 /*!
00789  * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
00790  *
00791  * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
00792  *
00793  * Values:
00794  * - 0000 - FB_TBST
00795  * - 0001 - FB_CS2
00796  * - 0010 - FB_BE_15_8
00797  */
00798 /*@{*/
00799 #define BP_FB_CSPMCR_GROUP4  (16U)         /*!< Bit position for FB_CSPMCR_GROUP4. */
00800 #define BM_FB_CSPMCR_GROUP4  (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
00801 #define BS_FB_CSPMCR_GROUP4  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
00802 
00803 /*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
00804 #define BR_FB_CSPMCR_GROUP4(x) (UNION_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), U, B.GROUP4))
00805 
00806 /*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
00807 #define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
00808 
00809 /*! @brief Set the GROUP4 field to a new value. */
00810 #define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
00811 /*@}*/
00812 
00813 /*!
00814  * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
00815  *
00816  * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
00817  *
00818  * Values:
00819  * - 0000 - FB_CS5
00820  * - 0001 - FB_TSIZ1
00821  * - 0010 - FB_BE_23_16
00822  */
00823 /*@{*/
00824 #define BP_FB_CSPMCR_GROUP3  (20U)         /*!< Bit position for FB_CSPMCR_GROUP3. */
00825 #define BM_FB_CSPMCR_GROUP3  (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
00826 #define BS_FB_CSPMCR_GROUP3  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
00827 
00828 /*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
00829 #define BR_FB_CSPMCR_GROUP3(x) (UNION_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), U, B.GROUP3))
00830 
00831 /*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
00832 #define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
00833 
00834 /*! @brief Set the GROUP3 field to a new value. */
00835 #define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
00836 /*@}*/
00837 
00838 /*!
00839  * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
00840  *
00841  * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
00842  *
00843  * Values:
00844  * - 0000 - FB_CS4
00845  * - 0001 - FB_TSIZ0
00846  * - 0010 - FB_BE_31_24
00847  */
00848 /*@{*/
00849 #define BP_FB_CSPMCR_GROUP2  (24U)         /*!< Bit position for FB_CSPMCR_GROUP2. */
00850 #define BM_FB_CSPMCR_GROUP2  (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
00851 #define BS_FB_CSPMCR_GROUP2  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
00852 
00853 /*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
00854 #define BR_FB_CSPMCR_GROUP2(x) (UNION_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), U, B.GROUP2))
00855 
00856 /*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
00857 #define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
00858 
00859 /*! @brief Set the GROUP2 field to a new value. */
00860 #define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
00861 /*@}*/
00862 
00863 /*!
00864  * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
00865  *
00866  * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
00867  *
00868  * Values:
00869  * - 0000 - FB_ALE
00870  * - 0001 - FB_CS1
00871  * - 0010 - FB_TS
00872  */
00873 /*@{*/
00874 #define BP_FB_CSPMCR_GROUP1  (28U)         /*!< Bit position for FB_CSPMCR_GROUP1. */
00875 #define BM_FB_CSPMCR_GROUP1  (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
00876 #define BS_FB_CSPMCR_GROUP1  (4U)          /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
00877 
00878 /*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
00879 #define BR_FB_CSPMCR_GROUP1(x) (UNION_READ(hw_fb_cspmcr_t, HW_FB_CSPMCR_ADDR(x), U, B.GROUP1))
00880 
00881 /*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
00882 #define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
00883 
00884 /*! @brief Set the GROUP1 field to a new value. */
00885 #define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
00886 /*@}*/
00887 
00888 /*******************************************************************************
00889  * hw_fb_t - module struct
00890  ******************************************************************************/
00891 /*!
00892  * @brief All FB module registers.
00893  */
00894 #pragma pack(1)
00895 typedef struct _hw_fb
00896 {
00897     struct {
00898         __IO hw_fb_csarn_t CSARn ;          /*!< [0x0] Chip Select Address Register */
00899         __IO hw_fb_csmrn_t CSMRn ;          /*!< [0x4] Chip Select Mask Register */
00900         __IO hw_fb_cscrn_t CSCRn ;          /*!< [0x8] Chip Select Control Register */
00901     } CS[6];
00902     uint8_t _reserved0[24];
00903     __IO hw_fb_cspmcr_t CSPMCR ;            /*!< [0x60] Chip Select port Multiplexing Control Register */
00904 } hw_fb_t;
00905 #pragma pack()
00906 
00907 /*! @brief Macro to access all FB registers. */
00908 /*! @param x FB module instance base address. */
00909 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00910  *     use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
00911 #define HW_FB(x)       (*(hw_fb_t *)(x))
00912 
00913 #endif /* __HW_FB_REGISTERS_H__ */
00914 /* EOF */