MK64F12_axbs.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_AXBS_REGISTERS_H__
00088 #define __HW_AXBS_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 AXBS
00095  *
00096  * Crossbar switch
00097  *
00098  * Registers defined in this header file:
00099  * - HW_AXBS_PRSn - Priority Registers Slave
00100  * - HW_AXBS_CRSn - Control Register
00101  * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
00102  * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
00103  * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
00104  * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
00105  * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
00106  * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
00107  *
00108  * - hw_axbs_t - Struct containing all module registers.
00109  */
00110 
00111 #define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
00112 
00113 /*******************************************************************************
00114  * HW_AXBS_PRSn - Priority Registers Slave
00115  ******************************************************************************/
00116 
00117 /*!
00118  * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
00119  *
00120  * Reset value: 0x00543210U
00121  *
00122  * The priority registers (PRSn) set the priority of each master port on a per
00123  * slave port basis and reside in each slave port. The priority register can be
00124  * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
00125  * register can only be read; attempts to write to it have no effect on PRSn and
00126  * result in a bus-error response to the master initiating the write. Two available
00127  * masters must not be programmed with the same priority level. Attempts to
00128  * program two or more masters with the same priority level result in a bus-error
00129  * response and the PRSn is not updated. Valid values for the Mn priority fields
00130  * depend on which masters are available on the chip. This information can be found in
00131  * the chip-specific information for the crossbar. If the chip contains less
00132  * than five masters, values 0 to 3 are valid. Writing other values will result in
00133  * an error. If the chip contains five or more masters, valid values are 0 to n-1,
00134  * where n is the number of masters attached to the AXBS module. Other values
00135  * will result in an error.
00136  */
00137 typedef union _hw_axbs_prsn
00138 {
00139     uint32_t U;
00140     struct _hw_axbs_prsn_bitfields
00141     {
00142         uint32_t M0 : 3;               /*!< [2:0] Master 0 Priority. Sets the arbitration
00143                                         * priority for this port on the associated slave port. */
00144         uint32_t RESERVED0 : 1;        /*!< [3]  */
00145         uint32_t M1 : 3;               /*!< [6:4] Master 1 Priority. Sets the arbitration
00146                                         * priority for this port on the associated slave port. */
00147         uint32_t RESERVED1 : 1;        /*!< [7]  */
00148         uint32_t M2 : 3;               /*!< [10:8] Master 2 Priority. Sets the arbitration
00149                                         * priority for this port on the associated slave port. */
00150         uint32_t RESERVED2 : 1;        /*!< [11]  */
00151         uint32_t M3 : 3;               /*!< [14:12] Master 3 Priority. Sets the arbitration
00152                                         * priority for this port on the associated slave port. */
00153         uint32_t RESERVED3 : 1;        /*!< [15]  */
00154         uint32_t M4 : 3;               /*!< [18:16] Master 4 Priority. Sets the arbitration
00155                                         * priority for this port on the associated slave port. */
00156         uint32_t RESERVED4 : 1;        /*!< [19]  */
00157         uint32_t M5 : 3;               /*!< [22:20] Master 5 Priority. Sets the arbitration
00158                                         * priority for this port on the associated slave port. */
00159         uint32_t RESERVED5 : 9;        /*!< [31:23]  */
00160     } B;
00161 } hw_axbs_prsn_t;
00162 
00163 /*!
00164  * @name Constants and macros for entire AXBS_PRSn register
00165  */
00166 /*@{*/
00167 #define HW_AXBS_PRSn_COUNT (5U)
00168 
00169 #define HW_AXBS_PRSn_ADDR(x, n)  ((x) + 0x0U + (0x100U * (n)))
00170 
00171 #define HW_AXBS_PRSn(x, n)       (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n))
00172 #define HW_AXBS_PRSn_RD(x, n)    (ADDRESS_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n)))
00173 #define HW_AXBS_PRSn_WR(x, n, v) (ADDRESS_WRITE(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), v))
00174 #define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) |  (v)))
00175 #define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v)))
00176 #define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^  (v)))
00177 /*@}*/
00178 
00179 /*
00180  * Constants & macros for individual AXBS_PRSn bitfields
00181  */
00182 
00183 /*!
00184  * @name Register AXBS_PRSn, field M0[2:0] (RW)
00185  *
00186  * Values:
00187  * - 000 - This master has level 1, or highest, priority when accessing the
00188  *     slave port.
00189  * - 001 - This master has level 2 priority when accessing the slave port.
00190  * - 010 - This master has level 3 priority when accessing the slave port.
00191  * - 011 - This master has level 4 priority when accessing the slave port.
00192  * - 100 - This master has level 5 priority when accessing the slave port.
00193  * - 101 - This master has level 6 priority when accessing the slave port.
00194  * - 110 - This master has level 7 priority when accessing the slave port.
00195  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00196  *     port.
00197  */
00198 /*@{*/
00199 #define BP_AXBS_PRSn_M0      (0U)          /*!< Bit position for AXBS_PRSn_M0. */
00200 #define BM_AXBS_PRSn_M0      (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */
00201 #define BS_AXBS_PRSn_M0      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M0. */
00202 
00203 /*! @brief Read current value of the AXBS_PRSn_M0 field. */
00204 #define BR_AXBS_PRSn_M0(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M0))
00205 
00206 /*! @brief Format value for bitfield AXBS_PRSn_M0. */
00207 #define BF_AXBS_PRSn_M0(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0)
00208 
00209 /*! @brief Set the M0 field to a new value. */
00210 #define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
00211 /*@}*/
00212 
00213 /*!
00214  * @name Register AXBS_PRSn, field M1[6:4] (RW)
00215  *
00216  * Values:
00217  * - 000 - This master has level 1, or highest, priority when accessing the
00218  *     slave port.
00219  * - 001 - This master has level 2 priority when accessing the slave port.
00220  * - 010 - This master has level 3 priority when accessing the slave port.
00221  * - 011 - This master has level 4 priority when accessing the slave port.
00222  * - 100 - This master has level 5 priority when accessing the slave port.
00223  * - 101 - This master has level 6 priority when accessing the slave port.
00224  * - 110 - This master has level 7 priority when accessing the slave port.
00225  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00226  *     port.
00227  */
00228 /*@{*/
00229 #define BP_AXBS_PRSn_M1      (4U)          /*!< Bit position for AXBS_PRSn_M1. */
00230 #define BM_AXBS_PRSn_M1      (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */
00231 #define BS_AXBS_PRSn_M1      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M1. */
00232 
00233 /*! @brief Read current value of the AXBS_PRSn_M1 field. */
00234 #define BR_AXBS_PRSn_M1(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M1))
00235 
00236 /*! @brief Format value for bitfield AXBS_PRSn_M1. */
00237 #define BF_AXBS_PRSn_M1(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1)
00238 
00239 /*! @brief Set the M1 field to a new value. */
00240 #define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
00241 /*@}*/
00242 
00243 /*!
00244  * @name Register AXBS_PRSn, field M2[10:8] (RW)
00245  *
00246  * Values:
00247  * - 000 - This master has level 1, or highest, priority when accessing the
00248  *     slave port.
00249  * - 001 - This master has level 2 priority when accessing the slave port.
00250  * - 010 - This master has level 3 priority when accessing the slave port.
00251  * - 011 - This master has level 4 priority when accessing the slave port.
00252  * - 100 - This master has level 5 priority when accessing the slave port.
00253  * - 101 - This master has level 6 priority when accessing the slave port.
00254  * - 110 - This master has level 7 priority when accessing the slave port.
00255  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00256  *     port.
00257  */
00258 /*@{*/
00259 #define BP_AXBS_PRSn_M2      (8U)          /*!< Bit position for AXBS_PRSn_M2. */
00260 #define BM_AXBS_PRSn_M2      (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */
00261 #define BS_AXBS_PRSn_M2      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M2. */
00262 
00263 /*! @brief Read current value of the AXBS_PRSn_M2 field. */
00264 #define BR_AXBS_PRSn_M2(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M2))
00265 
00266 /*! @brief Format value for bitfield AXBS_PRSn_M2. */
00267 #define BF_AXBS_PRSn_M2(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2)
00268 
00269 /*! @brief Set the M2 field to a new value. */
00270 #define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
00271 /*@}*/
00272 
00273 /*!
00274  * @name Register AXBS_PRSn, field M3[14:12] (RW)
00275  *
00276  * Values:
00277  * - 000 - This master has level 1, or highest, priority when accessing the
00278  *     slave port.
00279  * - 001 - This master has level 2 priority when accessing the slave port.
00280  * - 010 - This master has level 3 priority when accessing the slave port.
00281  * - 011 - This master has level 4 priority when accessing the slave port.
00282  * - 100 - This master has level 5 priority when accessing the slave port.
00283  * - 101 - This master has level 6 priority when accessing the slave port.
00284  * - 110 - This master has level 7 priority when accessing the slave port.
00285  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00286  *     port.
00287  */
00288 /*@{*/
00289 #define BP_AXBS_PRSn_M3      (12U)         /*!< Bit position for AXBS_PRSn_M3. */
00290 #define BM_AXBS_PRSn_M3      (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */
00291 #define BS_AXBS_PRSn_M3      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M3. */
00292 
00293 /*! @brief Read current value of the AXBS_PRSn_M3 field. */
00294 #define BR_AXBS_PRSn_M3(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M3))
00295 
00296 /*! @brief Format value for bitfield AXBS_PRSn_M3. */
00297 #define BF_AXBS_PRSn_M3(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3)
00298 
00299 /*! @brief Set the M3 field to a new value. */
00300 #define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
00301 /*@}*/
00302 
00303 /*!
00304  * @name Register AXBS_PRSn, field M4[18:16] (RW)
00305  *
00306  * Values:
00307  * - 000 - This master has level 1, or highest, priority when accessing the
00308  *     slave port.
00309  * - 001 - This master has level 2 priority when accessing the slave port.
00310  * - 010 - This master has level 3 priority when accessing the slave port.
00311  * - 011 - This master has level 4 priority when accessing the slave port.
00312  * - 100 - This master has level 5 priority when accessing the slave port.
00313  * - 101 - This master has level 6 priority when accessing the slave port.
00314  * - 110 - This master has level 7 priority when accessing the slave port.
00315  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00316  *     port.
00317  */
00318 /*@{*/
00319 #define BP_AXBS_PRSn_M4      (16U)         /*!< Bit position for AXBS_PRSn_M4. */
00320 #define BM_AXBS_PRSn_M4      (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */
00321 #define BS_AXBS_PRSn_M4      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M4. */
00322 
00323 /*! @brief Read current value of the AXBS_PRSn_M4 field. */
00324 #define BR_AXBS_PRSn_M4(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M4))
00325 
00326 /*! @brief Format value for bitfield AXBS_PRSn_M4. */
00327 #define BF_AXBS_PRSn_M4(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4)
00328 
00329 /*! @brief Set the M4 field to a new value. */
00330 #define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
00331 /*@}*/
00332 
00333 /*!
00334  * @name Register AXBS_PRSn, field M5[22:20] (RW)
00335  *
00336  * Values:
00337  * - 000 - This master has level 1, or highest, priority when accessing the
00338  *     slave port.
00339  * - 001 - This master has level 2 priority when accessing the slave port.
00340  * - 010 - This master has level 3 priority when accessing the slave port.
00341  * - 011 - This master has level 4 priority when accessing the slave port.
00342  * - 100 - This master has level 5 priority when accessing the slave port.
00343  * - 101 - This master has level 6 priority when accessing the slave port.
00344  * - 110 - This master has level 7 priority when accessing the slave port.
00345  * - 111 - This master has level 8, or lowest, priority when accessing the slave
00346  *     port.
00347  */
00348 /*@{*/
00349 #define BP_AXBS_PRSn_M5      (20U)         /*!< Bit position for AXBS_PRSn_M5. */
00350 #define BM_AXBS_PRSn_M5      (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */
00351 #define BS_AXBS_PRSn_M5      (3U)          /*!< Bit field size in bits for AXBS_PRSn_M5. */
00352 
00353 /*! @brief Read current value of the AXBS_PRSn_M5 field. */
00354 #define BR_AXBS_PRSn_M5(x, n) (UNION_READ(hw_axbs_prsn_t, HW_AXBS_PRSn_ADDR(x, n), U, B.M5))
00355 
00356 /*! @brief Format value for bitfield AXBS_PRSn_M5. */
00357 #define BF_AXBS_PRSn_M5(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5)
00358 
00359 /*! @brief Set the M5 field to a new value. */
00360 #define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
00361 /*@}*/
00362 /*******************************************************************************
00363  * HW_AXBS_CRSn - Control Register
00364  ******************************************************************************/
00365 
00366 /*!
00367  * @brief HW_AXBS_CRSn - Control Register (RW)
00368  *
00369  * Reset value: 0x00000000U
00370  *
00371  * These registers control several features of each slave port and must be
00372  * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
00373  * attempts to write to it have no effect and result in an error response.
00374  */
00375 typedef union _hw_axbs_crsn
00376 {
00377     uint32_t U;
00378     struct _hw_axbs_crsn_bitfields
00379     {
00380         uint32_t PARK : 3;             /*!< [2:0] Park */
00381         uint32_t RESERVED0 : 1;        /*!< [3]  */
00382         uint32_t PCTL : 2;             /*!< [5:4] Parking Control */
00383         uint32_t RESERVED1 : 2;        /*!< [7:6]  */
00384         uint32_t ARB : 2;              /*!< [9:8] Arbitration Mode */
00385         uint32_t RESERVED2 : 20;       /*!< [29:10]  */
00386         uint32_t HLP : 1;              /*!< [30] Halt Low Priority */
00387         uint32_t RO : 1;               /*!< [31] Read Only */
00388     } B;
00389 } hw_axbs_crsn_t;
00390 
00391 /*!
00392  * @name Constants and macros for entire AXBS_CRSn register
00393  */
00394 /*@{*/
00395 #define HW_AXBS_CRSn_COUNT (5U)
00396 
00397 #define HW_AXBS_CRSn_ADDR(x, n)  ((x) + 0x10U + (0x100U * (n)))
00398 
00399 #define HW_AXBS_CRSn(x, n)       (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n))
00400 #define HW_AXBS_CRSn_RD(x, n)    (ADDRESS_READ(hw_axbs_crsn_t, HW_AXBS_CRSn_ADDR(x, n)))
00401 #define HW_AXBS_CRSn_WR(x, n, v) (ADDRESS_WRITE(hw_axbs_crsn_t, HW_AXBS_CRSn_ADDR(x, n), v))
00402 #define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) |  (v)))
00403 #define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v)))
00404 #define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^  (v)))
00405 /*@}*/
00406 
00407 /*
00408  * Constants & macros for individual AXBS_CRSn bitfields
00409  */
00410 
00411 /*!
00412  * @name Register AXBS_CRSn, field PARK[2:0] (RW)
00413  *
00414  * Determines which master port the current slave port parks on when no masters
00415  * are actively making requests and the PCTL bits are cleared. Select only master
00416  * ports that are present on the chip. Otherwise, undefined behavior might occur.
00417  *
00418  * Values:
00419  * - 000 - Park on master port M0
00420  * - 001 - Park on master port M1
00421  * - 010 - Park on master port M2
00422  * - 011 - Park on master port M3
00423  * - 100 - Park on master port M4
00424  * - 101 - Park on master port M5
00425  * - 110 - Park on master port M6
00426  * - 111 - Park on master port M7
00427  */
00428 /*@{*/
00429 #define BP_AXBS_CRSn_PARK    (0U)          /*!< Bit position for AXBS_CRSn_PARK. */
00430 #define BM_AXBS_CRSn_PARK    (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */
00431 #define BS_AXBS_CRSn_PARK    (3U)          /*!< Bit field size in bits for AXBS_CRSn_PARK. */
00432 
00433 /*! @brief Read current value of the AXBS_CRSn_PARK field. */
00434 #define BR_AXBS_CRSn_PARK(x, n) (UNION_READ(hw_axbs_crsn_t, HW_AXBS_CRSn_ADDR(x, n), U, B.PARK))
00435 
00436 /*! @brief Format value for bitfield AXBS_CRSn_PARK. */
00437 #define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK)
00438 
00439 /*! @brief Set the PARK field to a new value. */
00440 #define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
00441 /*@}*/
00442 
00443 /*!
00444  * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
00445  *
00446  * Determines the slave port's parking control. The low-power park feature
00447  * results in an overall power savings if the slave port is not saturated. However,
00448  * this forces an extra latency clock when any master tries to access the slave
00449  * port while not in use because it is not parked on any master.
00450  *
00451  * Values:
00452  * - 00 - When no master makes a request, the arbiter parks the slave port on
00453  *     the master port defined by the PARK field
00454  * - 01 - When no master makes a request, the arbiter parks the slave port on
00455  *     the last master to be in control of the slave port
00456  * - 10 - When no master makes a request, the slave port is not parked on a
00457  *     master and the arbiter drives all outputs to a constant safe state
00458  * - 11 - Reserved
00459  */
00460 /*@{*/
00461 #define BP_AXBS_CRSn_PCTL    (4U)          /*!< Bit position for AXBS_CRSn_PCTL. */
00462 #define BM_AXBS_CRSn_PCTL    (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */
00463 #define BS_AXBS_CRSn_PCTL    (2U)          /*!< Bit field size in bits for AXBS_CRSn_PCTL. */
00464 
00465 /*! @brief Read current value of the AXBS_CRSn_PCTL field. */
00466 #define BR_AXBS_CRSn_PCTL(x, n) (UNION_READ(hw_axbs_crsn_t, HW_AXBS_CRSn_ADDR(x, n), U, B.PCTL))
00467 
00468 /*! @brief Format value for bitfield AXBS_CRSn_PCTL. */
00469 #define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL)
00470 
00471 /*! @brief Set the PCTL field to a new value. */
00472 #define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
00473 /*@}*/
00474 
00475 /*!
00476  * @name Register AXBS_CRSn, field ARB[9:8] (RW)
00477  *
00478  * Selects the arbitration policy for the slave port.
00479  *
00480  * Values:
00481  * - 00 - Fixed priority
00482  * - 01 - Round-robin, or rotating, priority
00483  * - 10 - Reserved
00484  * - 11 - Reserved
00485  */
00486 /*@{*/
00487 #define BP_AXBS_CRSn_ARB     (8U)          /*!< Bit position for AXBS_CRSn_ARB. */
00488 #define BM_AXBS_CRSn_ARB     (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */
00489 #define BS_AXBS_CRSn_ARB     (2U)          /*!< Bit field size in bits for AXBS_CRSn_ARB. */
00490 
00491 /*! @brief Read current value of the AXBS_CRSn_ARB field. */
00492 #define BR_AXBS_CRSn_ARB(x, n) (UNION_READ(hw_axbs_crsn_t, HW_AXBS_CRSn_ADDR(x, n), U, B.ARB))
00493 
00494 /*! @brief Format value for bitfield AXBS_CRSn_ARB. */
00495 #define BF_AXBS_CRSn_ARB(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB)
00496 
00497 /*! @brief Set the ARB field to a new value. */
00498 #define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
00499 /*@}*/
00500 
00501 /*!
00502  * @name Register AXBS_CRSn, field HLP[30] (RW)
00503  *
00504  * Sets the initial arbitration priority for low power mode requests . Setting
00505  * this bit will not affect the request for low power mode from attaining highest
00506  * priority once it has control of the slave ports.
00507  *
00508  * Values:
00509  * - 0 - The low power mode request has the highest priority for arbitration on
00510  *     this slave port
00511  * - 1 - The low power mode request has the lowest initial priority for
00512  *     arbitration on this slave port
00513  */
00514 /*@{*/
00515 #define BP_AXBS_CRSn_HLP     (30U)         /*!< Bit position for AXBS_CRSn_HLP. */
00516 #define BM_AXBS_CRSn_HLP     (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */
00517 #define BS_AXBS_CRSn_HLP     (1U)          /*!< Bit field size in bits for AXBS_CRSn_HLP. */
00518 
00519 /*! @brief Read current value of the AXBS_CRSn_HLP field. */
00520 #define BR_AXBS_CRSn_HLP(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP)))
00521 
00522 /*! @brief Format value for bitfield AXBS_CRSn_HLP. */
00523 #define BF_AXBS_CRSn_HLP(v)  ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP)
00524 
00525 /*! @brief Set the HLP field to a new value. */
00526 #define BW_AXBS_CRSn_HLP(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP), v))
00527 /*@}*/
00528 
00529 /*!
00530  * @name Register AXBS_CRSn, field RO[31] (RW)
00531  *
00532  * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
00533  * only a hardware reset clears it.
00534  *
00535  * Values:
00536  * - 0 - The slave port's registers are writeable
00537  * - 1 - The slave port's registers are read-only and cannot be written.
00538  *     Attempted writes have no effect on the registers and result in a bus error
00539  *     response.
00540  */
00541 /*@{*/
00542 #define BP_AXBS_CRSn_RO      (31U)         /*!< Bit position for AXBS_CRSn_RO. */
00543 #define BM_AXBS_CRSn_RO      (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */
00544 #define BS_AXBS_CRSn_RO      (1U)          /*!< Bit field size in bits for AXBS_CRSn_RO. */
00545 
00546 /*! @brief Read current value of the AXBS_CRSn_RO field. */
00547 #define BR_AXBS_CRSn_RO(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO)))
00548 
00549 /*! @brief Format value for bitfield AXBS_CRSn_RO. */
00550 #define BF_AXBS_CRSn_RO(v)   ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO)
00551 
00552 /*! @brief Set the RO field to a new value. */
00553 #define BW_AXBS_CRSn_RO(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO), v))
00554 /*@}*/
00555 
00556 /*******************************************************************************
00557  * HW_AXBS_MGPCR0 - Master General Purpose Control Register
00558  ******************************************************************************/
00559 
00560 /*!
00561  * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
00562  *
00563  * Reset value: 0x00000000U
00564  *
00565  * The MGPCR controls only whether the master's undefined length burst accesses
00566  * are allowed to complete uninterrupted or whether they can be broken by
00567  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00568  * mode with 32-bit accesses.
00569  */
00570 typedef union _hw_axbs_mgpcr0
00571 {
00572     uint32_t U;
00573     struct _hw_axbs_mgpcr0_bitfields
00574     {
00575         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00576         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00577     } B;
00578 } hw_axbs_mgpcr0_t;
00579 
00580 /*!
00581  * @name Constants and macros for entire AXBS_MGPCR0 register
00582  */
00583 /*@{*/
00584 #define HW_AXBS_MGPCR0_ADDR(x)   ((x) + 0x800U)
00585 
00586 #define HW_AXBS_MGPCR0(x)        (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x))
00587 #define HW_AXBS_MGPCR0_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr0_t, HW_AXBS_MGPCR0_ADDR(x)))
00588 #define HW_AXBS_MGPCR0_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr0_t, HW_AXBS_MGPCR0_ADDR(x), v))
00589 #define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) |  (v)))
00590 #define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v)))
00591 #define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^  (v)))
00592 /*@}*/
00593 
00594 /*
00595  * Constants & macros for individual AXBS_MGPCR0 bitfields
00596  */
00597 
00598 /*!
00599  * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
00600  *
00601  * Determines whether, and when, the crossbar switch arbitrates away the slave
00602  * port the master owns when the master is performing undefined length burst
00603  * accesses.
00604  *
00605  * Values:
00606  * - 000 - No arbitration is allowed during an undefined length burst
00607  * - 001 - Arbitration is allowed at any time during an undefined length burst
00608  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00609  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00610  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00611  * - 101 - Reserved
00612  * - 110 - Reserved
00613  * - 111 - Reserved
00614  */
00615 /*@{*/
00616 #define BP_AXBS_MGPCR0_AULB  (0U)          /*!< Bit position for AXBS_MGPCR0_AULB. */
00617 #define BM_AXBS_MGPCR0_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */
00618 #define BS_AXBS_MGPCR0_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */
00619 
00620 /*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
00621 #define BR_AXBS_MGPCR0_AULB(x) (UNION_READ(hw_axbs_mgpcr0_t, HW_AXBS_MGPCR0_ADDR(x), U, B.AULB))
00622 
00623 /*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */
00624 #define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB)
00625 
00626 /*! @brief Set the AULB field to a new value. */
00627 #define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
00628 /*@}*/
00629 
00630 /*******************************************************************************
00631  * HW_AXBS_MGPCR1 - Master General Purpose Control Register
00632  ******************************************************************************/
00633 
00634 /*!
00635  * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
00636  *
00637  * Reset value: 0x00000000U
00638  *
00639  * The MGPCR controls only whether the master's undefined length burst accesses
00640  * are allowed to complete uninterrupted or whether they can be broken by
00641  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00642  * mode with 32-bit accesses.
00643  */
00644 typedef union _hw_axbs_mgpcr1
00645 {
00646     uint32_t U;
00647     struct _hw_axbs_mgpcr1_bitfields
00648     {
00649         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00650         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00651     } B;
00652 } hw_axbs_mgpcr1_t;
00653 
00654 /*!
00655  * @name Constants and macros for entire AXBS_MGPCR1 register
00656  */
00657 /*@{*/
00658 #define HW_AXBS_MGPCR1_ADDR(x)   ((x) + 0x900U)
00659 
00660 #define HW_AXBS_MGPCR1(x)        (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x))
00661 #define HW_AXBS_MGPCR1_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr1_t, HW_AXBS_MGPCR1_ADDR(x)))
00662 #define HW_AXBS_MGPCR1_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr1_t, HW_AXBS_MGPCR1_ADDR(x), v))
00663 #define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) |  (v)))
00664 #define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v)))
00665 #define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^  (v)))
00666 /*@}*/
00667 
00668 /*
00669  * Constants & macros for individual AXBS_MGPCR1 bitfields
00670  */
00671 
00672 /*!
00673  * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
00674  *
00675  * Determines whether, and when, the crossbar switch arbitrates away the slave
00676  * port the master owns when the master is performing undefined length burst
00677  * accesses.
00678  *
00679  * Values:
00680  * - 000 - No arbitration is allowed during an undefined length burst
00681  * - 001 - Arbitration is allowed at any time during an undefined length burst
00682  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00683  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00684  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00685  * - 101 - Reserved
00686  * - 110 - Reserved
00687  * - 111 - Reserved
00688  */
00689 /*@{*/
00690 #define BP_AXBS_MGPCR1_AULB  (0U)          /*!< Bit position for AXBS_MGPCR1_AULB. */
00691 #define BM_AXBS_MGPCR1_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */
00692 #define BS_AXBS_MGPCR1_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */
00693 
00694 /*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
00695 #define BR_AXBS_MGPCR1_AULB(x) (UNION_READ(hw_axbs_mgpcr1_t, HW_AXBS_MGPCR1_ADDR(x), U, B.AULB))
00696 
00697 /*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */
00698 #define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB)
00699 
00700 /*! @brief Set the AULB field to a new value. */
00701 #define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
00702 /*@}*/
00703 
00704 /*******************************************************************************
00705  * HW_AXBS_MGPCR2 - Master General Purpose Control Register
00706  ******************************************************************************/
00707 
00708 /*!
00709  * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
00710  *
00711  * Reset value: 0x00000000U
00712  *
00713  * The MGPCR controls only whether the master's undefined length burst accesses
00714  * are allowed to complete uninterrupted or whether they can be broken by
00715  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00716  * mode with 32-bit accesses.
00717  */
00718 typedef union _hw_axbs_mgpcr2
00719 {
00720     uint32_t U;
00721     struct _hw_axbs_mgpcr2_bitfields
00722     {
00723         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00724         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00725     } B;
00726 } hw_axbs_mgpcr2_t;
00727 
00728 /*!
00729  * @name Constants and macros for entire AXBS_MGPCR2 register
00730  */
00731 /*@{*/
00732 #define HW_AXBS_MGPCR2_ADDR(x)   ((x) + 0xA00U)
00733 
00734 #define HW_AXBS_MGPCR2(x)        (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x))
00735 #define HW_AXBS_MGPCR2_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr2_t, HW_AXBS_MGPCR2_ADDR(x)))
00736 #define HW_AXBS_MGPCR2_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr2_t, HW_AXBS_MGPCR2_ADDR(x), v))
00737 #define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) |  (v)))
00738 #define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v)))
00739 #define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^  (v)))
00740 /*@}*/
00741 
00742 /*
00743  * Constants & macros for individual AXBS_MGPCR2 bitfields
00744  */
00745 
00746 /*!
00747  * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
00748  *
00749  * Determines whether, and when, the crossbar switch arbitrates away the slave
00750  * port the master owns when the master is performing undefined length burst
00751  * accesses.
00752  *
00753  * Values:
00754  * - 000 - No arbitration is allowed during an undefined length burst
00755  * - 001 - Arbitration is allowed at any time during an undefined length burst
00756  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00757  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00758  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00759  * - 101 - Reserved
00760  * - 110 - Reserved
00761  * - 111 - Reserved
00762  */
00763 /*@{*/
00764 #define BP_AXBS_MGPCR2_AULB  (0U)          /*!< Bit position for AXBS_MGPCR2_AULB. */
00765 #define BM_AXBS_MGPCR2_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */
00766 #define BS_AXBS_MGPCR2_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */
00767 
00768 /*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
00769 #define BR_AXBS_MGPCR2_AULB(x) (UNION_READ(hw_axbs_mgpcr2_t, HW_AXBS_MGPCR2_ADDR(x), U, B.AULB))
00770 
00771 /*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */
00772 #define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB)
00773 
00774 /*! @brief Set the AULB field to a new value. */
00775 #define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
00776 /*@}*/
00777 
00778 /*******************************************************************************
00779  * HW_AXBS_MGPCR3 - Master General Purpose Control Register
00780  ******************************************************************************/
00781 
00782 /*!
00783  * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
00784  *
00785  * Reset value: 0x00000000U
00786  *
00787  * The MGPCR controls only whether the master's undefined length burst accesses
00788  * are allowed to complete uninterrupted or whether they can be broken by
00789  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00790  * mode with 32-bit accesses.
00791  */
00792 typedef union _hw_axbs_mgpcr3
00793 {
00794     uint32_t U;
00795     struct _hw_axbs_mgpcr3_bitfields
00796     {
00797         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00798         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00799     } B;
00800 } hw_axbs_mgpcr3_t;
00801 
00802 /*!
00803  * @name Constants and macros for entire AXBS_MGPCR3 register
00804  */
00805 /*@{*/
00806 #define HW_AXBS_MGPCR3_ADDR(x)   ((x) + 0xB00U)
00807 
00808 #define HW_AXBS_MGPCR3(x)        (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x))
00809 #define HW_AXBS_MGPCR3_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr3_t, HW_AXBS_MGPCR3_ADDR(x)))
00810 #define HW_AXBS_MGPCR3_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr3_t, HW_AXBS_MGPCR3_ADDR(x), v))
00811 #define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) |  (v)))
00812 #define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v)))
00813 #define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^  (v)))
00814 /*@}*/
00815 
00816 /*
00817  * Constants & macros for individual AXBS_MGPCR3 bitfields
00818  */
00819 
00820 /*!
00821  * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
00822  *
00823  * Determines whether, and when, the crossbar switch arbitrates away the slave
00824  * port the master owns when the master is performing undefined length burst
00825  * accesses.
00826  *
00827  * Values:
00828  * - 000 - No arbitration is allowed during an undefined length burst
00829  * - 001 - Arbitration is allowed at any time during an undefined length burst
00830  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00831  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00832  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00833  * - 101 - Reserved
00834  * - 110 - Reserved
00835  * - 111 - Reserved
00836  */
00837 /*@{*/
00838 #define BP_AXBS_MGPCR3_AULB  (0U)          /*!< Bit position for AXBS_MGPCR3_AULB. */
00839 #define BM_AXBS_MGPCR3_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */
00840 #define BS_AXBS_MGPCR3_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */
00841 
00842 /*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
00843 #define BR_AXBS_MGPCR3_AULB(x) (UNION_READ(hw_axbs_mgpcr3_t, HW_AXBS_MGPCR3_ADDR(x), U, B.AULB))
00844 
00845 /*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */
00846 #define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB)
00847 
00848 /*! @brief Set the AULB field to a new value. */
00849 #define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
00850 /*@}*/
00851 
00852 /*******************************************************************************
00853  * HW_AXBS_MGPCR4 - Master General Purpose Control Register
00854  ******************************************************************************/
00855 
00856 /*!
00857  * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
00858  *
00859  * Reset value: 0x00000000U
00860  *
00861  * The MGPCR controls only whether the master's undefined length burst accesses
00862  * are allowed to complete uninterrupted or whether they can be broken by
00863  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00864  * mode with 32-bit accesses.
00865  */
00866 typedef union _hw_axbs_mgpcr4
00867 {
00868     uint32_t U;
00869     struct _hw_axbs_mgpcr4_bitfields
00870     {
00871         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00872         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00873     } B;
00874 } hw_axbs_mgpcr4_t;
00875 
00876 /*!
00877  * @name Constants and macros for entire AXBS_MGPCR4 register
00878  */
00879 /*@{*/
00880 #define HW_AXBS_MGPCR4_ADDR(x)   ((x) + 0xC00U)
00881 
00882 #define HW_AXBS_MGPCR4(x)        (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x))
00883 #define HW_AXBS_MGPCR4_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr4_t, HW_AXBS_MGPCR4_ADDR(x)))
00884 #define HW_AXBS_MGPCR4_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr4_t, HW_AXBS_MGPCR4_ADDR(x), v))
00885 #define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) |  (v)))
00886 #define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v)))
00887 #define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^  (v)))
00888 /*@}*/
00889 
00890 /*
00891  * Constants & macros for individual AXBS_MGPCR4 bitfields
00892  */
00893 
00894 /*!
00895  * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
00896  *
00897  * Determines whether, and when, the crossbar switch arbitrates away the slave
00898  * port the master owns when the master is performing undefined length burst
00899  * accesses.
00900  *
00901  * Values:
00902  * - 000 - No arbitration is allowed during an undefined length burst
00903  * - 001 - Arbitration is allowed at any time during an undefined length burst
00904  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00905  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00906  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00907  * - 101 - Reserved
00908  * - 110 - Reserved
00909  * - 111 - Reserved
00910  */
00911 /*@{*/
00912 #define BP_AXBS_MGPCR4_AULB  (0U)          /*!< Bit position for AXBS_MGPCR4_AULB. */
00913 #define BM_AXBS_MGPCR4_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */
00914 #define BS_AXBS_MGPCR4_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */
00915 
00916 /*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
00917 #define BR_AXBS_MGPCR4_AULB(x) (UNION_READ(hw_axbs_mgpcr4_t, HW_AXBS_MGPCR4_ADDR(x), U, B.AULB))
00918 
00919 /*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */
00920 #define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB)
00921 
00922 /*! @brief Set the AULB field to a new value. */
00923 #define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
00924 /*@}*/
00925 
00926 /*******************************************************************************
00927  * HW_AXBS_MGPCR5 - Master General Purpose Control Register
00928  ******************************************************************************/
00929 
00930 /*!
00931  * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
00932  *
00933  * Reset value: 0x00000000U
00934  *
00935  * The MGPCR controls only whether the master's undefined length burst accesses
00936  * are allowed to complete uninterrupted or whether they can be broken by
00937  * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
00938  * mode with 32-bit accesses.
00939  */
00940 typedef union _hw_axbs_mgpcr5
00941 {
00942     uint32_t U;
00943     struct _hw_axbs_mgpcr5_bitfields
00944     {
00945         uint32_t AULB : 3;             /*!< [2:0] Arbitrates On Undefined Length Bursts */
00946         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00947     } B;
00948 } hw_axbs_mgpcr5_t;
00949 
00950 /*!
00951  * @name Constants and macros for entire AXBS_MGPCR5 register
00952  */
00953 /*@{*/
00954 #define HW_AXBS_MGPCR5_ADDR(x)   ((x) + 0xD00U)
00955 
00956 #define HW_AXBS_MGPCR5(x)        (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x))
00957 #define HW_AXBS_MGPCR5_RD(x)     (ADDRESS_READ(hw_axbs_mgpcr5_t, HW_AXBS_MGPCR5_ADDR(x)))
00958 #define HW_AXBS_MGPCR5_WR(x, v)  (ADDRESS_WRITE(hw_axbs_mgpcr5_t, HW_AXBS_MGPCR5_ADDR(x), v))
00959 #define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) |  (v)))
00960 #define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v)))
00961 #define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^  (v)))
00962 /*@}*/
00963 
00964 /*
00965  * Constants & macros for individual AXBS_MGPCR5 bitfields
00966  */
00967 
00968 /*!
00969  * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
00970  *
00971  * Determines whether, and when, the crossbar switch arbitrates away the slave
00972  * port the master owns when the master is performing undefined length burst
00973  * accesses.
00974  *
00975  * Values:
00976  * - 000 - No arbitration is allowed during an undefined length burst
00977  * - 001 - Arbitration is allowed at any time during an undefined length burst
00978  * - 010 - Arbitration is allowed after four beats of an undefined length burst
00979  * - 011 - Arbitration is allowed after eight beats of an undefined length burst
00980  * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
00981  * - 101 - Reserved
00982  * - 110 - Reserved
00983  * - 111 - Reserved
00984  */
00985 /*@{*/
00986 #define BP_AXBS_MGPCR5_AULB  (0U)          /*!< Bit position for AXBS_MGPCR5_AULB. */
00987 #define BM_AXBS_MGPCR5_AULB  (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */
00988 #define BS_AXBS_MGPCR5_AULB  (3U)          /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */
00989 
00990 /*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
00991 #define BR_AXBS_MGPCR5_AULB(x) (UNION_READ(hw_axbs_mgpcr5_t, HW_AXBS_MGPCR5_ADDR(x), U, B.AULB))
00992 
00993 /*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */
00994 #define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB)
00995 
00996 /*! @brief Set the AULB field to a new value. */
00997 #define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
00998 /*@}*/
00999 
01000 /*******************************************************************************
01001  * hw_axbs_t - module struct
01002  ******************************************************************************/
01003 /*!
01004  * @brief All AXBS module registers.
01005  */
01006 #pragma pack(1)
01007 typedef struct _hw_axbs
01008 {
01009     struct {
01010         __IO hw_axbs_prsn_t PRSn ;          /*!< [0x0] Priority Registers Slave */
01011         uint8_t _reserved0[12];
01012         __IO hw_axbs_crsn_t CRSn ;          /*!< [0x10] Control Register */
01013         uint8_t _reserved1[236];
01014     } SLAVE[5];
01015     uint8_t _reserved0[768];
01016     __IO hw_axbs_mgpcr0_t MGPCR0 ;          /*!< [0x800] Master General Purpose Control Register */
01017     uint8_t _reserved1[252];
01018     __IO hw_axbs_mgpcr1_t MGPCR1 ;          /*!< [0x900] Master General Purpose Control Register */
01019     uint8_t _reserved2[252];
01020     __IO hw_axbs_mgpcr2_t MGPCR2 ;          /*!< [0xA00] Master General Purpose Control Register */
01021     uint8_t _reserved3[252];
01022     __IO hw_axbs_mgpcr3_t MGPCR3 ;          /*!< [0xB00] Master General Purpose Control Register */
01023     uint8_t _reserved4[252];
01024     __IO hw_axbs_mgpcr4_t MGPCR4 ;          /*!< [0xC00] Master General Purpose Control Register */
01025     uint8_t _reserved5[252];
01026     __IO hw_axbs_mgpcr5_t MGPCR5 ;          /*!< [0xD00] Master General Purpose Control Register */
01027 } hw_axbs_t;
01028 #pragma pack()
01029 
01030 /*! @brief Macro to access all AXBS registers. */
01031 /*! @param x AXBS module instance base address. */
01032 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01033  *     use the '&' operator, like <code>&HW_AXBS(AXBS_BASE)</code>. */
01034 #define HW_AXBS(x)     (*(hw_axbs_t *)(x))
01035 
01036 #endif /* __HW_AXBS_REGISTERS_H__ */
01037 /* EOF */