Alessandro Angelino / target-mcu-k64f

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Fork of target-mcu-k64f by Morpheus

hal/device/device/MK64F12/MK64F12_smc.h@5:41cb6fa198f3, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:09:12 2016 +0100
Revision:
5:41cb6fa198f3
Parent:
0:c5e2f793b59a 
Mirror huge PR from mbed OS



The following PRs have been mirrored:

https://github.com/ARMmbed/mbed-hal-k64f/pull/6  "All Freescale macros for memory access replaced"

https://github.com/ARMmbed/mbed-hal-k64f/pull/7  "Fix bug in union access macros"

https://github.com/ARMmbed/mbed-hal-k64f/pull/8  "Simpler and more universal macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/9  "Fixed bug in fallback macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/10 "Added volatile keyword to address for union read"

https://github.com/ARMmbed/mbed-hal-k64f/pull/14 "Removing copyright and revision from unmodified file"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
Alessandro Angelino 5:41cb6fa198f3 18 ** (C) COPYRIGHT 2015-2015 ARM Limited
Alessandro Angelino 5:41cb6fa198f3 19 ** ALL RIGHTS RESERVED
Alessandro Angelino 5:41cb6fa198f3 20 **
screamer 0:c5e2f793b59a 21 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 22 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 25 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 26 **
screamer 0:c5e2f793b59a 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 28 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 29 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 30 **
screamer 0:c5e2f793b59a 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 32 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 33 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 34 **
screamer 0:c5e2f793b59a 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** http: www.freescale.com
screamer 0:c5e2f793b59a 47 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 48 **
screamer 0:c5e2f793b59a 49 ** Revisions:
screamer 0:c5e2f793b59a 50 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 51 ** Initial version.
screamer 0:c5e2f793b59a 52 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 53 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 55 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 56 ** System initialization updated.
screamer 0:c5e2f793b59a 57 ** MCG - registers updated.
screamer 0:c5e2f793b59a 58 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 59 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 61 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 62 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 63 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 64 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 65 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 66 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 67 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 73 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Alessandro Angelino 5:41cb6fa198f3 74 ** - rev. 2.6 (2015-08-03) (ARM)
Alessandro Angelino 5:41cb6fa198f3 75 ** All accesses to memory are replaced by equivalent macros; this allows
Alessandro Angelino 5:41cb6fa198f3 76 ** memory read/write operations to be re-defined if needed (for example,
Alessandro Angelino 5:41cb6fa198f3 77 ** to implement new security features
screamer 0:c5e2f793b59a 78 **
screamer 0:c5e2f793b59a 79 ** ###################################################################
screamer 0:c5e2f793b59a 80 */
screamer 0:c5e2f793b59a 81
screamer 0:c5e2f793b59a 82 /*
screamer 0:c5e2f793b59a 83 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 84 *
screamer 0:c5e2f793b59a 85 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 86 */
screamer 0:c5e2f793b59a 87 #ifndef __HW_SMC_REGISTERS_H__
screamer 0:c5e2f793b59a 88 #define __HW_SMC_REGISTERS_H__
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90 #include "MK64F12.h"
screamer 0:c5e2f793b59a 91 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 92
screamer 0:c5e2f793b59a 93 /*
screamer 0:c5e2f793b59a 94 * MK64F12 SMC
screamer 0:c5e2f793b59a 95 *
screamer 0:c5e2f793b59a 96 * System Mode Controller
screamer 0:c5e2f793b59a 97 *
screamer 0:c5e2f793b59a 98 * Registers defined in this header file:
screamer 0:c5e2f793b59a 99 * - HW_SMC_PMPROT - Power Mode Protection register
screamer 0:c5e2f793b59a 100 * - HW_SMC_PMCTRL - Power Mode Control register
screamer 0:c5e2f793b59a 101 * - HW_SMC_VLLSCTRL - VLLS Control register
screamer 0:c5e2f793b59a 102 * - HW_SMC_PMSTAT - Power Mode Status register
screamer 0:c5e2f793b59a 103 *
screamer 0:c5e2f793b59a 104 * - hw_smc_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 105 */
screamer 0:c5e2f793b59a 106
screamer 0:c5e2f793b59a 107 #define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
screamer 0:c5e2f793b59a 108
screamer 0:c5e2f793b59a 109 /*******************************************************************************
screamer 0:c5e2f793b59a 110 * HW_SMC_PMPROT - Power Mode Protection register
screamer 0:c5e2f793b59a 111 ******************************************************************************/
screamer 0:c5e2f793b59a 112
screamer 0:c5e2f793b59a 113 /*!
screamer 0:c5e2f793b59a 114 * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
screamer 0:c5e2f793b59a 115 *
screamer 0:c5e2f793b59a 116 * Reset value: 0x00U
screamer 0:c5e2f793b59a 117 *
screamer 0:c5e2f793b59a 118 * This register provides protection for entry into any low-power run or stop
screamer 0:c5e2f793b59a 119 * mode. The enabling of the low-power run or stop mode occurs by configuring the
screamer 0:c5e2f793b59a 120 * Power Mode Control register (PMCTRL). The PMPROT register can be written only
screamer 0:c5e2f793b59a 121 * once after any system reset. If the MCU is configured for a disallowed or
screamer 0:c5e2f793b59a 122 * reserved power mode, the MCU remains in its current power mode. For example, if the
screamer 0:c5e2f793b59a 123 * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
screamer 0:c5e2f793b59a 124 * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
screamer 0:c5e2f793b59a 125 * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
screamer 0:c5e2f793b59a 126 * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
screamer 0:c5e2f793b59a 127 * that do not trigger Chip Reset not VLLS. See the Reset section details for more
screamer 0:c5e2f793b59a 128 * information.
screamer 0:c5e2f793b59a 129 */
screamer 0:c5e2f793b59a 130 typedef union _hw_smc_pmprot
screamer 0:c5e2f793b59a 131 {
screamer 0:c5e2f793b59a 132 uint8_t U;
screamer 0:c5e2f793b59a 133 struct _hw_smc_pmprot_bitfields
screamer 0:c5e2f793b59a 134 {
screamer 0:c5e2f793b59a 135 uint8_t RESERVED0 : 1; /*!< [0] */
screamer 0:c5e2f793b59a 136 uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */
screamer 0:c5e2f793b59a 137 uint8_t RESERVED1 : 1; /*!< [2] */
screamer 0:c5e2f793b59a 138 uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */
screamer 0:c5e2f793b59a 139 uint8_t RESERVED2 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 140 uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */
screamer 0:c5e2f793b59a 141 uint8_t RESERVED3 : 2; /*!< [7:6] */
screamer 0:c5e2f793b59a 142 } B;
screamer 0:c5e2f793b59a 143 } hw_smc_pmprot_t;
screamer 0:c5e2f793b59a 144
screamer 0:c5e2f793b59a 145 /*!
screamer 0:c5e2f793b59a 146 * @name Constants and macros for entire SMC_PMPROT register
screamer 0:c5e2f793b59a 147 */
screamer 0:c5e2f793b59a 148 /*@{*/
screamer 0:c5e2f793b59a 149 #define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 150
screamer 0:c5e2f793b59a 151 #define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 152 #define HW_SMC_PMPROT_RD(x) (ADDRESS_READ(hw_smc_pmprot_t, HW_SMC_PMPROT_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 153 #define HW_SMC_PMPROT_WR(x, v) (ADDRESS_WRITE(hw_smc_pmprot_t, HW_SMC_PMPROT_ADDR(x), v))
screamer 0:c5e2f793b59a 154 #define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v)))
screamer 0:c5e2f793b59a 155 #define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 156 #define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 157 /*@}*/
screamer 0:c5e2f793b59a 158
screamer 0:c5e2f793b59a 159 /*
screamer 0:c5e2f793b59a 160 * Constants & macros for individual SMC_PMPROT bitfields
screamer 0:c5e2f793b59a 161 */
screamer 0:c5e2f793b59a 162
screamer 0:c5e2f793b59a 163 /*!
screamer 0:c5e2f793b59a 164 * @name Register SMC_PMPROT, field AVLLS[1] (RW)
screamer 0:c5e2f793b59a 165 *
screamer 0:c5e2f793b59a 166 * Provided the appropriate control bits are set up in PMCTRL, this write once
screamer 0:c5e2f793b59a 167 * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
screamer 0:c5e2f793b59a 168 *
screamer 0:c5e2f793b59a 169 * Values:
screamer 0:c5e2f793b59a 170 * - 0 - Any VLLSx mode is not allowed
screamer 0:c5e2f793b59a 171 * - 1 - Any VLLSx mode is allowed
screamer 0:c5e2f793b59a 172 */
screamer 0:c5e2f793b59a 173 /*@{*/
screamer 0:c5e2f793b59a 174 #define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */
screamer 0:c5e2f793b59a 175 #define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */
screamer 0:c5e2f793b59a 176 #define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
screamer 0:c5e2f793b59a 177
screamer 0:c5e2f793b59a 178 /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
Alessandro Angelino 5:41cb6fa198f3 179 #define BR_SMC_PMPROT_AVLLS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS)))
screamer 0:c5e2f793b59a 180
screamer 0:c5e2f793b59a 181 /*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
screamer 0:c5e2f793b59a 182 #define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
screamer 0:c5e2f793b59a 183
screamer 0:c5e2f793b59a 184 /*! @brief Set the AVLLS field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 185 #define BW_SMC_PMPROT_AVLLS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS), v))
screamer 0:c5e2f793b59a 186 /*@}*/
screamer 0:c5e2f793b59a 187
screamer 0:c5e2f793b59a 188 /*!
screamer 0:c5e2f793b59a 189 * @name Register SMC_PMPROT, field ALLS[3] (RW)
screamer 0:c5e2f793b59a 190 *
screamer 0:c5e2f793b59a 191 * Provided the appropriate control bits are set up in PMCTRL, this write-once
screamer 0:c5e2f793b59a 192 * field allows the MCU to enter any low-leakage stop mode (LLS).
screamer 0:c5e2f793b59a 193 *
screamer 0:c5e2f793b59a 194 * Values:
screamer 0:c5e2f793b59a 195 * - 0 - LLS is not allowed
screamer 0:c5e2f793b59a 196 * - 1 - LLS is allowed
screamer 0:c5e2f793b59a 197 */
screamer 0:c5e2f793b59a 198 /*@{*/
screamer 0:c5e2f793b59a 199 #define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */
screamer 0:c5e2f793b59a 200 #define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */
screamer 0:c5e2f793b59a 201 #define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
screamer 0:c5e2f793b59a 202
screamer 0:c5e2f793b59a 203 /*! @brief Read current value of the SMC_PMPROT_ALLS field. */
Alessandro Angelino 5:41cb6fa198f3 204 #define BR_SMC_PMPROT_ALLS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS)))
screamer 0:c5e2f793b59a 205
screamer 0:c5e2f793b59a 206 /*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
screamer 0:c5e2f793b59a 207 #define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
screamer 0:c5e2f793b59a 208
screamer 0:c5e2f793b59a 209 /*! @brief Set the ALLS field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 210 #define BW_SMC_PMPROT_ALLS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS), v))
screamer 0:c5e2f793b59a 211 /*@}*/
screamer 0:c5e2f793b59a 212
screamer 0:c5e2f793b59a 213 /*!
screamer 0:c5e2f793b59a 214 * @name Register SMC_PMPROT, field AVLP[5] (RW)
screamer 0:c5e2f793b59a 215 *
screamer 0:c5e2f793b59a 216 * Provided the appropriate control bits are set up in PMCTRL, this write-once
screamer 0:c5e2f793b59a 217 * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
screamer 0:c5e2f793b59a 218 *
screamer 0:c5e2f793b59a 219 * Values:
screamer 0:c5e2f793b59a 220 * - 0 - VLPR, VLPW, and VLPS are not allowed.
screamer 0:c5e2f793b59a 221 * - 1 - VLPR, VLPW, and VLPS are allowed.
screamer 0:c5e2f793b59a 222 */
screamer 0:c5e2f793b59a 223 /*@{*/
screamer 0:c5e2f793b59a 224 #define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */
screamer 0:c5e2f793b59a 225 #define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */
screamer 0:c5e2f793b59a 226 #define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
screamer 0:c5e2f793b59a 227
screamer 0:c5e2f793b59a 228 /*! @brief Read current value of the SMC_PMPROT_AVLP field. */
Alessandro Angelino 5:41cb6fa198f3 229 #define BR_SMC_PMPROT_AVLP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP)))
screamer 0:c5e2f793b59a 230
screamer 0:c5e2f793b59a 231 /*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
screamer 0:c5e2f793b59a 232 #define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
screamer 0:c5e2f793b59a 233
screamer 0:c5e2f793b59a 234 /*! @brief Set the AVLP field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 235 #define BW_SMC_PMPROT_AVLP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP), v))
screamer 0:c5e2f793b59a 236 /*@}*/
screamer 0:c5e2f793b59a 237
screamer 0:c5e2f793b59a 238 /*******************************************************************************
screamer 0:c5e2f793b59a 239 * HW_SMC_PMCTRL - Power Mode Control register
screamer 0:c5e2f793b59a 240 ******************************************************************************/
screamer 0:c5e2f793b59a 241
screamer 0:c5e2f793b59a 242 /*!
screamer 0:c5e2f793b59a 243 * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
screamer 0:c5e2f793b59a 244 *
screamer 0:c5e2f793b59a 245 * Reset value: 0x00U
screamer 0:c5e2f793b59a 246 *
screamer 0:c5e2f793b59a 247 * The PMCTRL register controls entry into low-power Run and Stop modes,
screamer 0:c5e2f793b59a 248 * provided that the selected power mode is allowed via an appropriate setting of the
screamer 0:c5e2f793b59a 249 * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
screamer 0:c5e2f793b59a 250 * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
screamer 0:c5e2f793b59a 251 * that do not trigger Chip POR not VLLS. See the Reset section details for more
screamer 0:c5e2f793b59a 252 * information.
screamer 0:c5e2f793b59a 253 */
screamer 0:c5e2f793b59a 254 typedef union _hw_smc_pmctrl
screamer 0:c5e2f793b59a 255 {
screamer 0:c5e2f793b59a 256 uint8_t U;
screamer 0:c5e2f793b59a 257 struct _hw_smc_pmctrl_bitfields
screamer 0:c5e2f793b59a 258 {
screamer 0:c5e2f793b59a 259 uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */
screamer 0:c5e2f793b59a 260 uint8_t STOPA : 1; /*!< [3] Stop Aborted */
screamer 0:c5e2f793b59a 261 uint8_t RESERVED0 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 262 uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */
screamer 0:c5e2f793b59a 263 uint8_t LPWUI : 1; /*!< [7] Low-Power Wake Up On Interrupt */
screamer 0:c5e2f793b59a 264 } B;
screamer 0:c5e2f793b59a 265 } hw_smc_pmctrl_t;
screamer 0:c5e2f793b59a 266
screamer 0:c5e2f793b59a 267 /*!
screamer 0:c5e2f793b59a 268 * @name Constants and macros for entire SMC_PMCTRL register
screamer 0:c5e2f793b59a 269 */
screamer 0:c5e2f793b59a 270 /*@{*/
screamer 0:c5e2f793b59a 271 #define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U)
screamer 0:c5e2f793b59a 272
screamer 0:c5e2f793b59a 273 #define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 274 #define HW_SMC_PMCTRL_RD(x) (ADDRESS_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 275 #define HW_SMC_PMCTRL_WR(x, v) (ADDRESS_WRITE(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), v))
screamer 0:c5e2f793b59a 276 #define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 277 #define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 278 #define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 279 /*@}*/
screamer 0:c5e2f793b59a 280
screamer 0:c5e2f793b59a 281 /*
screamer 0:c5e2f793b59a 282 * Constants & macros for individual SMC_PMCTRL bitfields
screamer 0:c5e2f793b59a 283 */
screamer 0:c5e2f793b59a 284
screamer 0:c5e2f793b59a 285 /*!
screamer 0:c5e2f793b59a 286 * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
screamer 0:c5e2f793b59a 287 *
screamer 0:c5e2f793b59a 288 * When written, controls entry into the selected stop mode when Sleep-Now or
screamer 0:c5e2f793b59a 289 * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
screamer 0:c5e2f793b59a 290 * blocked if the protection level has not been enabled using the PMPROT register.
screamer 0:c5e2f793b59a 291 * After any system reset, this field is cleared by hardware on any successful write
screamer 0:c5e2f793b59a 292 * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
screamer 0:c5e2f793b59a 293 * register is used to further select the particular VLLS submode which will be
screamer 0:c5e2f793b59a 294 * entered.
screamer 0:c5e2f793b59a 295 *
screamer 0:c5e2f793b59a 296 * Values:
screamer 0:c5e2f793b59a 297 * - 000 - Normal Stop (STOP)
screamer 0:c5e2f793b59a 298 * - 001 - Reserved
screamer 0:c5e2f793b59a 299 * - 010 - Very-Low-Power Stop (VLPS)
screamer 0:c5e2f793b59a 300 * - 011 - Low-Leakage Stop (LLS)
screamer 0:c5e2f793b59a 301 * - 100 - Very-Low-Leakage Stop (VLLSx)
screamer 0:c5e2f793b59a 302 * - 101 - Reserved
screamer 0:c5e2f793b59a 303 * - 110 - Reseved
screamer 0:c5e2f793b59a 304 * - 111 - Reserved
screamer 0:c5e2f793b59a 305 */
screamer 0:c5e2f793b59a 306 /*@{*/
screamer 0:c5e2f793b59a 307 #define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */
screamer 0:c5e2f793b59a 308 #define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */
screamer 0:c5e2f793b59a 309 #define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
screamer 0:c5e2f793b59a 310
screamer 0:c5e2f793b59a 311 /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
Alessandro Angelino 5:41cb6fa198f3 312 #define BR_SMC_PMCTRL_STOPM(x) (UNION_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), U, B.STOPM))
screamer 0:c5e2f793b59a 313
screamer 0:c5e2f793b59a 314 /*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
screamer 0:c5e2f793b59a 315 #define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
screamer 0:c5e2f793b59a 316
screamer 0:c5e2f793b59a 317 /*! @brief Set the STOPM field to a new value. */
screamer 0:c5e2f793b59a 318 #define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
screamer 0:c5e2f793b59a 319 /*@}*/
screamer 0:c5e2f793b59a 320
screamer 0:c5e2f793b59a 321 /*!
screamer 0:c5e2f793b59a 322 * @name Register SMC_PMCTRL, field STOPA[3] (RO)
screamer 0:c5e2f793b59a 323 *
screamer 0:c5e2f793b59a 324 * When set, this read-only status bit indicates an interrupt or reset occured
screamer 0:c5e2f793b59a 325 * during the previous stop mode entry sequence, preventing the system from
screamer 0:c5e2f793b59a 326 * entering that mode. This field is cleared by hardware at the beginning of any stop
screamer 0:c5e2f793b59a 327 * mode entry sequence and is set if the sequence was aborted.
screamer 0:c5e2f793b59a 328 *
screamer 0:c5e2f793b59a 329 * Values:
screamer 0:c5e2f793b59a 330 * - 0 - The previous stop mode entry was successsful.
screamer 0:c5e2f793b59a 331 * - 1 - The previous stop mode entry was aborted.
screamer 0:c5e2f793b59a 332 */
screamer 0:c5e2f793b59a 333 /*@{*/
screamer 0:c5e2f793b59a 334 #define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */
screamer 0:c5e2f793b59a 335 #define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */
screamer 0:c5e2f793b59a 336 #define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
screamer 0:c5e2f793b59a 337
screamer 0:c5e2f793b59a 338 /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
Alessandro Angelino 5:41cb6fa198f3 339 #define BR_SMC_PMCTRL_STOPA(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA)))
screamer 0:c5e2f793b59a 340 /*@}*/
screamer 0:c5e2f793b59a 341
screamer 0:c5e2f793b59a 342 /*!
screamer 0:c5e2f793b59a 343 * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
screamer 0:c5e2f793b59a 344 *
screamer 0:c5e2f793b59a 345 * When written, causes entry into the selected run mode. Writes to this field
screamer 0:c5e2f793b59a 346 * are blocked if the protection level has not been enabled using the PMPROT
screamer 0:c5e2f793b59a 347 * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
screamer 0:c5e2f793b59a 348 * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
screamer 0:c5e2f793b59a 349 *
screamer 0:c5e2f793b59a 350 * Values:
screamer 0:c5e2f793b59a 351 * - 00 - Normal Run mode (RUN)
screamer 0:c5e2f793b59a 352 * - 01 - Reserved
screamer 0:c5e2f793b59a 353 * - 10 - Very-Low-Power Run mode (VLPR)
screamer 0:c5e2f793b59a 354 * - 11 - Reserved
screamer 0:c5e2f793b59a 355 */
screamer 0:c5e2f793b59a 356 /*@{*/
screamer 0:c5e2f793b59a 357 #define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */
screamer 0:c5e2f793b59a 358 #define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */
screamer 0:c5e2f793b59a 359 #define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
screamer 0:c5e2f793b59a 360
screamer 0:c5e2f793b59a 361 /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
Alessandro Angelino 5:41cb6fa198f3 362 #define BR_SMC_PMCTRL_RUNM(x) (UNION_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), U, B.RUNM))
screamer 0:c5e2f793b59a 363
screamer 0:c5e2f793b59a 364 /*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
screamer 0:c5e2f793b59a 365 #define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
screamer 0:c5e2f793b59a 366
screamer 0:c5e2f793b59a 367 /*! @brief Set the RUNM field to a new value. */
screamer 0:c5e2f793b59a 368 #define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
screamer 0:c5e2f793b59a 369 /*@}*/
screamer 0:c5e2f793b59a 370
screamer 0:c5e2f793b59a 371 /*!
screamer 0:c5e2f793b59a 372 * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
screamer 0:c5e2f793b59a 373 *
screamer 0:c5e2f793b59a 374 * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
screamer 0:c5e2f793b59a 375 * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
screamer 0:c5e2f793b59a 376 * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
screamer 0:c5e2f793b59a 377 * the LPWUI setting. LPWUI must be modified only while the system is in RUN
screamer 0:c5e2f793b59a 378 * mode, that is, when PMSTAT=RUN.
screamer 0:c5e2f793b59a 379 *
screamer 0:c5e2f793b59a 380 * Values:
screamer 0:c5e2f793b59a 381 * - 0 - The system remains in a VLP mode on an interrupt
screamer 0:c5e2f793b59a 382 * - 1 - The system exits to Normal RUN mode on an interrupt
screamer 0:c5e2f793b59a 383 */
screamer 0:c5e2f793b59a 384 /*@{*/
screamer 0:c5e2f793b59a 385 #define BP_SMC_PMCTRL_LPWUI (7U) /*!< Bit position for SMC_PMCTRL_LPWUI. */
screamer 0:c5e2f793b59a 386 #define BM_SMC_PMCTRL_LPWUI (0x80U) /*!< Bit mask for SMC_PMCTRL_LPWUI. */
screamer 0:c5e2f793b59a 387 #define BS_SMC_PMCTRL_LPWUI (1U) /*!< Bit field size in bits for SMC_PMCTRL_LPWUI. */
screamer 0:c5e2f793b59a 388
screamer 0:c5e2f793b59a 389 /*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
Alessandro Angelino 5:41cb6fa198f3 390 #define BR_SMC_PMCTRL_LPWUI(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI)))
screamer 0:c5e2f793b59a 391
screamer 0:c5e2f793b59a 392 /*! @brief Format value for bitfield SMC_PMCTRL_LPWUI. */
screamer 0:c5e2f793b59a 393 #define BF_SMC_PMCTRL_LPWUI(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_LPWUI) & BM_SMC_PMCTRL_LPWUI)
screamer 0:c5e2f793b59a 394
screamer 0:c5e2f793b59a 395 /*! @brief Set the LPWUI field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 396 #define BW_SMC_PMCTRL_LPWUI(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI), v))
screamer 0:c5e2f793b59a 397 /*@}*/
screamer 0:c5e2f793b59a 398
screamer 0:c5e2f793b59a 399 /*******************************************************************************
screamer 0:c5e2f793b59a 400 * HW_SMC_VLLSCTRL - VLLS Control register
screamer 0:c5e2f793b59a 401 ******************************************************************************/
screamer 0:c5e2f793b59a 402
screamer 0:c5e2f793b59a 403 /*!
screamer 0:c5e2f793b59a 404 * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
screamer 0:c5e2f793b59a 405 *
screamer 0:c5e2f793b59a 406 * Reset value: 0x03U
screamer 0:c5e2f793b59a 407 *
screamer 0:c5e2f793b59a 408 * The VLLSCTRL register controls features related to VLLS modes. This register
screamer 0:c5e2f793b59a 409 * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
screamer 0:c5e2f793b59a 410 * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
screamer 0:c5e2f793b59a 411 * the Reset section details for more information.
screamer 0:c5e2f793b59a 412 */
screamer 0:c5e2f793b59a 413 typedef union _hw_smc_vllsctrl
screamer 0:c5e2f793b59a 414 {
screamer 0:c5e2f793b59a 415 uint8_t U;
screamer 0:c5e2f793b59a 416 struct _hw_smc_vllsctrl_bitfields
screamer 0:c5e2f793b59a 417 {
screamer 0:c5e2f793b59a 418 uint8_t VLLSM : 3; /*!< [2:0] VLLS Mode Control */
screamer 0:c5e2f793b59a 419 uint8_t RESERVED0 : 2; /*!< [4:3] */
screamer 0:c5e2f793b59a 420 uint8_t PORPO : 1; /*!< [5] POR Power Option */
screamer 0:c5e2f793b59a 421 uint8_t RESERVED1 : 2; /*!< [7:6] */
screamer 0:c5e2f793b59a 422 } B;
screamer 0:c5e2f793b59a 423 } hw_smc_vllsctrl_t;
screamer 0:c5e2f793b59a 424
screamer 0:c5e2f793b59a 425 /*!
screamer 0:c5e2f793b59a 426 * @name Constants and macros for entire SMC_VLLSCTRL register
screamer 0:c5e2f793b59a 427 */
screamer 0:c5e2f793b59a 428 /*@{*/
screamer 0:c5e2f793b59a 429 #define HW_SMC_VLLSCTRL_ADDR(x) ((x) + 0x2U)
screamer 0:c5e2f793b59a 430
screamer 0:c5e2f793b59a 431 #define HW_SMC_VLLSCTRL(x) (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 432 #define HW_SMC_VLLSCTRL_RD(x) (ADDRESS_READ(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 433 #define HW_SMC_VLLSCTRL_WR(x, v) (ADDRESS_WRITE(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x), v))
screamer 0:c5e2f793b59a 434 #define HW_SMC_VLLSCTRL_SET(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) | (v)))
screamer 0:c5e2f793b59a 435 #define HW_SMC_VLLSCTRL_CLR(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 436 #define HW_SMC_VLLSCTRL_TOG(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 437 /*@}*/
screamer 0:c5e2f793b59a 438
screamer 0:c5e2f793b59a 439 /*
screamer 0:c5e2f793b59a 440 * Constants & macros for individual SMC_VLLSCTRL bitfields
screamer 0:c5e2f793b59a 441 */
screamer 0:c5e2f793b59a 442
screamer 0:c5e2f793b59a 443 /*!
screamer 0:c5e2f793b59a 444 * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
screamer 0:c5e2f793b59a 445 *
screamer 0:c5e2f793b59a 446 * Controls which VLLS sub-mode to enter if STOPM=VLLS.
screamer 0:c5e2f793b59a 447 *
screamer 0:c5e2f793b59a 448 * Values:
screamer 0:c5e2f793b59a 449 * - 000 - VLLS0
screamer 0:c5e2f793b59a 450 * - 001 - VLLS1
screamer 0:c5e2f793b59a 451 * - 010 - VLLS2
screamer 0:c5e2f793b59a 452 * - 011 - VLLS3
screamer 0:c5e2f793b59a 453 * - 100 - Reserved
screamer 0:c5e2f793b59a 454 * - 101 - Reserved
screamer 0:c5e2f793b59a 455 * - 110 - Reserved
screamer 0:c5e2f793b59a 456 * - 111 - Reserved
screamer 0:c5e2f793b59a 457 */
screamer 0:c5e2f793b59a 458 /*@{*/
screamer 0:c5e2f793b59a 459 #define BP_SMC_VLLSCTRL_VLLSM (0U) /*!< Bit position for SMC_VLLSCTRL_VLLSM. */
screamer 0:c5e2f793b59a 460 #define BM_SMC_VLLSCTRL_VLLSM (0x07U) /*!< Bit mask for SMC_VLLSCTRL_VLLSM. */
screamer 0:c5e2f793b59a 461 #define BS_SMC_VLLSCTRL_VLLSM (3U) /*!< Bit field size in bits for SMC_VLLSCTRL_VLLSM. */
screamer 0:c5e2f793b59a 462
screamer 0:c5e2f793b59a 463 /*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
Alessandro Angelino 5:41cb6fa198f3 464 #define BR_SMC_VLLSCTRL_VLLSM(x) (UNION_READ(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x), U, B.VLLSM))
screamer 0:c5e2f793b59a 465
screamer 0:c5e2f793b59a 466 /*! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM. */
screamer 0:c5e2f793b59a 467 #define BF_SMC_VLLSCTRL_VLLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_VLLSM) & BM_SMC_VLLSCTRL_VLLSM)
screamer 0:c5e2f793b59a 468
screamer 0:c5e2f793b59a 469 /*! @brief Set the VLLSM field to a new value. */
screamer 0:c5e2f793b59a 470 #define BW_SMC_VLLSCTRL_VLLSM(x, v) (HW_SMC_VLLSCTRL_WR(x, (HW_SMC_VLLSCTRL_RD(x) & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
screamer 0:c5e2f793b59a 471 /*@}*/
screamer 0:c5e2f793b59a 472
screamer 0:c5e2f793b59a 473 /*!
screamer 0:c5e2f793b59a 474 * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
screamer 0:c5e2f793b59a 475 *
screamer 0:c5e2f793b59a 476 * Controls whether the POR detect circuit (for brown-out detection) is enabled
screamer 0:c5e2f793b59a 477 * in VLLS0 mode.
screamer 0:c5e2f793b59a 478 *
screamer 0:c5e2f793b59a 479 * Values:
screamer 0:c5e2f793b59a 480 * - 0 - POR detect circuit is enabled in VLLS0.
screamer 0:c5e2f793b59a 481 * - 1 - POR detect circuit is disabled in VLLS0.
screamer 0:c5e2f793b59a 482 */
screamer 0:c5e2f793b59a 483 /*@{*/
screamer 0:c5e2f793b59a 484 #define BP_SMC_VLLSCTRL_PORPO (5U) /*!< Bit position for SMC_VLLSCTRL_PORPO. */
screamer 0:c5e2f793b59a 485 #define BM_SMC_VLLSCTRL_PORPO (0x20U) /*!< Bit mask for SMC_VLLSCTRL_PORPO. */
screamer 0:c5e2f793b59a 486 #define BS_SMC_VLLSCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_VLLSCTRL_PORPO. */
screamer 0:c5e2f793b59a 487
screamer 0:c5e2f793b59a 488 /*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
Alessandro Angelino 5:41cb6fa198f3 489 #define BR_SMC_VLLSCTRL_PORPO(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO)))
screamer 0:c5e2f793b59a 490
screamer 0:c5e2f793b59a 491 /*! @brief Format value for bitfield SMC_VLLSCTRL_PORPO. */
screamer 0:c5e2f793b59a 492 #define BF_SMC_VLLSCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_PORPO) & BM_SMC_VLLSCTRL_PORPO)
screamer 0:c5e2f793b59a 493
screamer 0:c5e2f793b59a 494 /*! @brief Set the PORPO field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 495 #define BW_SMC_VLLSCTRL_PORPO(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO), v))
screamer 0:c5e2f793b59a 496 /*@}*/
screamer 0:c5e2f793b59a 497
screamer 0:c5e2f793b59a 498 /*******************************************************************************
screamer 0:c5e2f793b59a 499 * HW_SMC_PMSTAT - Power Mode Status register
screamer 0:c5e2f793b59a 500 ******************************************************************************/
screamer 0:c5e2f793b59a 501
screamer 0:c5e2f793b59a 502 /*!
screamer 0:c5e2f793b59a 503 * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
screamer 0:c5e2f793b59a 504 *
screamer 0:c5e2f793b59a 505 * Reset value: 0x01U
screamer 0:c5e2f793b59a 506 *
screamer 0:c5e2f793b59a 507 * PMSTAT is a read-only, one-hot register which indicates the current power
screamer 0:c5e2f793b59a 508 * mode of the system. This register is reset on Chip POR not VLLS and by reset
screamer 0:c5e2f793b59a 509 * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
screamer 0:c5e2f793b59a 510 * trigger Chip POR not VLLS. See the Reset section details for more information.
screamer 0:c5e2f793b59a 511 */
screamer 0:c5e2f793b59a 512 typedef union _hw_smc_pmstat
screamer 0:c5e2f793b59a 513 {
screamer 0:c5e2f793b59a 514 uint8_t U;
screamer 0:c5e2f793b59a 515 struct _hw_smc_pmstat_bitfields
screamer 0:c5e2f793b59a 516 {
screamer 0:c5e2f793b59a 517 uint8_t PMSTAT : 7; /*!< [6:0] */
screamer 0:c5e2f793b59a 518 uint8_t RESERVED0 : 1; /*!< [7] */
screamer 0:c5e2f793b59a 519 } B;
screamer 0:c5e2f793b59a 520 } hw_smc_pmstat_t;
screamer 0:c5e2f793b59a 521
screamer 0:c5e2f793b59a 522 /*!
screamer 0:c5e2f793b59a 523 * @name Constants and macros for entire SMC_PMSTAT register
screamer 0:c5e2f793b59a 524 */
screamer 0:c5e2f793b59a 525 /*@{*/
screamer 0:c5e2f793b59a 526 #define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U)
screamer 0:c5e2f793b59a 527
screamer 0:c5e2f793b59a 528 #define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 529 #define HW_SMC_PMSTAT_RD(x) (ADDRESS_READ(hw_smc_pmstat_t, HW_SMC_PMSTAT_ADDR(x)))
screamer 0:c5e2f793b59a 530 /*@}*/
screamer 0:c5e2f793b59a 531
screamer 0:c5e2f793b59a 532 /*
screamer 0:c5e2f793b59a 533 * Constants & macros for individual SMC_PMSTAT bitfields
screamer 0:c5e2f793b59a 534 */
screamer 0:c5e2f793b59a 535
screamer 0:c5e2f793b59a 536 /*!
screamer 0:c5e2f793b59a 537 * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
screamer 0:c5e2f793b59a 538 *
screamer 0:c5e2f793b59a 539 * When debug is enabled, the PMSTAT will not update to STOP or VLPS
screamer 0:c5e2f793b59a 540 */
screamer 0:c5e2f793b59a 541 /*@{*/
screamer 0:c5e2f793b59a 542 #define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */
screamer 0:c5e2f793b59a 543 #define BM_SMC_PMSTAT_PMSTAT (0x7FU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
screamer 0:c5e2f793b59a 544 #define BS_SMC_PMSTAT_PMSTAT (7U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
screamer 0:c5e2f793b59a 545
screamer 0:c5e2f793b59a 546 /*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
Alessandro Angelino 5:41cb6fa198f3 547 #define BR_SMC_PMSTAT_PMSTAT(x) (UNION_READ(hw_smc_pmstat_t, HW_SMC_PMSTAT_ADDR(x), U, B.PMSTAT))
screamer 0:c5e2f793b59a 548 /*@}*/
screamer 0:c5e2f793b59a 549
screamer 0:c5e2f793b59a 550 /*******************************************************************************
screamer 0:c5e2f793b59a 551 * hw_smc_t - module struct
screamer 0:c5e2f793b59a 552 ******************************************************************************/
screamer 0:c5e2f793b59a 553 /*!
screamer 0:c5e2f793b59a 554 * @brief All SMC module registers.
screamer 0:c5e2f793b59a 555 */
screamer 0:c5e2f793b59a 556 #pragma pack(1)
screamer 0:c5e2f793b59a 557 typedef struct _hw_smc
screamer 0:c5e2f793b59a 558 {
screamer 0:c5e2f793b59a 559 __IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */
screamer 0:c5e2f793b59a 560 __IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */
screamer 0:c5e2f793b59a 561 __IO hw_smc_vllsctrl_t VLLSCTRL; /*!< [0x2] VLLS Control register */
screamer 0:c5e2f793b59a 562 __I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */
screamer 0:c5e2f793b59a 563 } hw_smc_t;
screamer 0:c5e2f793b59a 564 #pragma pack()
screamer 0:c5e2f793b59a 565
screamer 0:c5e2f793b59a 566 /*! @brief Macro to access all SMC registers. */
screamer 0:c5e2f793b59a 567 /*! @param x SMC module instance base address. */
screamer 0:c5e2f793b59a 568 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 569 * use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
screamer 0:c5e2f793b59a 570 #define HW_SMC(x) (*(hw_smc_t *)(x))
screamer 0:c5e2f793b59a 571
screamer 0:c5e2f793b59a 572 #endif /* __HW_SMC_REGISTERS_H__ */
screamer 0:c5e2f793b59a 573 /* EOF */