Alessandro Angelino / target-mcu-k64f

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Fork of target-mcu-k64f by Morpheus

hal/device/device/MK64F12/MK64F12_pdb.h@5:41cb6fa198f3, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:09:12 2016 +0100
Revision:
5:41cb6fa198f3
Parent:
0:c5e2f793b59a 
Mirror huge PR from mbed OS



The following PRs have been mirrored:

https://github.com/ARMmbed/mbed-hal-k64f/pull/6  "All Freescale macros for memory access replaced"

https://github.com/ARMmbed/mbed-hal-k64f/pull/7  "Fix bug in union access macros"

https://github.com/ARMmbed/mbed-hal-k64f/pull/8  "Simpler and more universal macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/9  "Fixed bug in fallback macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/10 "Added volatile keyword to address for union read"

https://github.com/ARMmbed/mbed-hal-k64f/pull/14 "Removing copyright and revision from unmodified file"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
Alessandro Angelino 5:41cb6fa198f3 18 ** (C) COPYRIGHT 2015-2015 ARM Limited
Alessandro Angelino 5:41cb6fa198f3 19 ** ALL RIGHTS RESERVED
Alessandro Angelino 5:41cb6fa198f3 20 **
screamer 0:c5e2f793b59a 21 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 22 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 25 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 26 **
screamer 0:c5e2f793b59a 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 28 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 29 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 30 **
screamer 0:c5e2f793b59a 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 32 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 33 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 34 **
screamer 0:c5e2f793b59a 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** http: www.freescale.com
screamer 0:c5e2f793b59a 47 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 48 **
screamer 0:c5e2f793b59a 49 ** Revisions:
screamer 0:c5e2f793b59a 50 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 51 ** Initial version.
screamer 0:c5e2f793b59a 52 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 53 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 55 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 56 ** System initialization updated.
screamer 0:c5e2f793b59a 57 ** MCG - registers updated.
screamer 0:c5e2f793b59a 58 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 59 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 61 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 62 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 63 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 64 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 65 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 66 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 67 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 73 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Alessandro Angelino 5:41cb6fa198f3 74 ** - rev. 2.6 (2015-08-03) (ARM)
Alessandro Angelino 5:41cb6fa198f3 75 ** All accesses to memory are replaced by equivalent macros; this allows
Alessandro Angelino 5:41cb6fa198f3 76 ** memory read/write operations to be re-defined if needed (for example,
Alessandro Angelino 5:41cb6fa198f3 77 ** to implement new security features
screamer 0:c5e2f793b59a 78 **
screamer 0:c5e2f793b59a 79 ** ###################################################################
screamer 0:c5e2f793b59a 80 */
screamer 0:c5e2f793b59a 81
screamer 0:c5e2f793b59a 82 /*
screamer 0:c5e2f793b59a 83 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 84 *
screamer 0:c5e2f793b59a 85 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 86 */
screamer 0:c5e2f793b59a 87 #ifndef __HW_PDB_REGISTERS_H__
screamer 0:c5e2f793b59a 88 #define __HW_PDB_REGISTERS_H__
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90 #include "MK64F12.h"
screamer 0:c5e2f793b59a 91 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 92
screamer 0:c5e2f793b59a 93 /*
screamer 0:c5e2f793b59a 94 * MK64F12 PDB
screamer 0:c5e2f793b59a 95 *
screamer 0:c5e2f793b59a 96 * Programmable Delay Block
screamer 0:c5e2f793b59a 97 *
screamer 0:c5e2f793b59a 98 * Registers defined in this header file:
screamer 0:c5e2f793b59a 99 * - HW_PDB_SC - Status and Control register
screamer 0:c5e2f793b59a 100 * - HW_PDB_MOD - Modulus register
screamer 0:c5e2f793b59a 101 * - HW_PDB_CNT - Counter register
screamer 0:c5e2f793b59a 102 * - HW_PDB_IDLY - Interrupt Delay register
screamer 0:c5e2f793b59a 103 * - HW_PDB_CHnC1 - Channel n Control register 1
screamer 0:c5e2f793b59a 104 * - HW_PDB_CHnS - Channel n Status register
screamer 0:c5e2f793b59a 105 * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
screamer 0:c5e2f793b59a 106 * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
screamer 0:c5e2f793b59a 107 * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
screamer 0:c5e2f793b59a 108 * - HW_PDB_DACINTn - DAC Interval n register
screamer 0:c5e2f793b59a 109 * - HW_PDB_POEN - Pulse-Out n Enable register
screamer 0:c5e2f793b59a 110 * - HW_PDB_POnDLY - Pulse-Out n Delay register
screamer 0:c5e2f793b59a 111 *
screamer 0:c5e2f793b59a 112 * - hw_pdb_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 113 */
screamer 0:c5e2f793b59a 114
screamer 0:c5e2f793b59a 115 #define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
screamer 0:c5e2f793b59a 116
screamer 0:c5e2f793b59a 117 /*******************************************************************************
screamer 0:c5e2f793b59a 118 * HW_PDB_SC - Status and Control register
screamer 0:c5e2f793b59a 119 ******************************************************************************/
screamer 0:c5e2f793b59a 120
screamer 0:c5e2f793b59a 121 /*!
screamer 0:c5e2f793b59a 122 * @brief HW_PDB_SC - Status and Control register (RW)
screamer 0:c5e2f793b59a 123 *
screamer 0:c5e2f793b59a 124 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 125 */
screamer 0:c5e2f793b59a 126 typedef union _hw_pdb_sc
screamer 0:c5e2f793b59a 127 {
screamer 0:c5e2f793b59a 128 uint32_t U;
screamer 0:c5e2f793b59a 129 struct _hw_pdb_sc_bitfields
screamer 0:c5e2f793b59a 130 {
screamer 0:c5e2f793b59a 131 uint32_t LDOK : 1; /*!< [0] Load OK */
screamer 0:c5e2f793b59a 132 uint32_t CONT : 1; /*!< [1] Continuous Mode Enable */
screamer 0:c5e2f793b59a 133 uint32_t MULT : 2; /*!< [3:2] Multiplication Factor Select for
screamer 0:c5e2f793b59a 134 * Prescaler */
screamer 0:c5e2f793b59a 135 uint32_t RESERVED0 : 1; /*!< [4] */
screamer 0:c5e2f793b59a 136 uint32_t PDBIE : 1; /*!< [5] PDB Interrupt Enable */
screamer 0:c5e2f793b59a 137 uint32_t PDBIF : 1; /*!< [6] PDB Interrupt Flag */
screamer 0:c5e2f793b59a 138 uint32_t PDBEN : 1; /*!< [7] PDB Enable */
screamer 0:c5e2f793b59a 139 uint32_t TRGSEL : 4; /*!< [11:8] Trigger Input Source Select */
screamer 0:c5e2f793b59a 140 uint32_t PRESCALER : 3; /*!< [14:12] Prescaler Divider Select */
screamer 0:c5e2f793b59a 141 uint32_t DMAEN : 1; /*!< [15] DMA Enable */
screamer 0:c5e2f793b59a 142 uint32_t SWTRIG : 1; /*!< [16] Software Trigger */
screamer 0:c5e2f793b59a 143 uint32_t PDBEIE : 1; /*!< [17] PDB Sequence Error Interrupt Enable */
screamer 0:c5e2f793b59a 144 uint32_t LDMOD : 2; /*!< [19:18] Load Mode Select */
screamer 0:c5e2f793b59a 145 uint32_t RESERVED1 : 12; /*!< [31:20] */
screamer 0:c5e2f793b59a 146 } B;
screamer 0:c5e2f793b59a 147 } hw_pdb_sc_t;
screamer 0:c5e2f793b59a 148
screamer 0:c5e2f793b59a 149 /*!
screamer 0:c5e2f793b59a 150 * @name Constants and macros for entire PDB_SC register
screamer 0:c5e2f793b59a 151 */
screamer 0:c5e2f793b59a 152 /*@{*/
screamer 0:c5e2f793b59a 153 #define HW_PDB_SC_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 154
screamer 0:c5e2f793b59a 155 #define HW_PDB_SC(x) (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 156 #define HW_PDB_SC_RD(x) (ADDRESS_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 157 #define HW_PDB_SC_WR(x, v) (ADDRESS_WRITE(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), v))
screamer 0:c5e2f793b59a 158 #define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) | (v)))
screamer 0:c5e2f793b59a 159 #define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 160 #define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 161 /*@}*/
screamer 0:c5e2f793b59a 162
screamer 0:c5e2f793b59a 163 /*
screamer 0:c5e2f793b59a 164 * Constants & macros for individual PDB_SC bitfields
screamer 0:c5e2f793b59a 165 */
screamer 0:c5e2f793b59a 166
screamer 0:c5e2f793b59a 167 /*!
screamer 0:c5e2f793b59a 168 * @name Register PDB_SC, field LDOK[0] (RW)
screamer 0:c5e2f793b59a 169 *
screamer 0:c5e2f793b59a 170 * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
screamer 0:c5e2f793b59a 171 * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
screamer 0:c5e2f793b59a 172 * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
screamer 0:c5e2f793b59a 173 * written to the LDOK field, the values in the buffers of above registers are
screamer 0:c5e2f793b59a 174 * not effective and the buffers cannot be written until the values in buffers are
screamer 0:c5e2f793b59a 175 * loaded into their internal registers. LDOK can be written only when PDBEN is
screamer 0:c5e2f793b59a 176 * set or it can be written at the same time with PDBEN being written to 1. It is
screamer 0:c5e2f793b59a 177 * automatically cleared when the values in buffers are loaded into the internal
screamer 0:c5e2f793b59a 178 * registers or the PDBEN is cleared. Writing 0 to it has no effect.
screamer 0:c5e2f793b59a 179 */
screamer 0:c5e2f793b59a 180 /*@{*/
screamer 0:c5e2f793b59a 181 #define BP_PDB_SC_LDOK (0U) /*!< Bit position for PDB_SC_LDOK. */
screamer 0:c5e2f793b59a 182 #define BM_PDB_SC_LDOK (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */
screamer 0:c5e2f793b59a 183 #define BS_PDB_SC_LDOK (1U) /*!< Bit field size in bits for PDB_SC_LDOK. */
screamer 0:c5e2f793b59a 184
screamer 0:c5e2f793b59a 185 /*! @brief Read current value of the PDB_SC_LDOK field. */
Alessandro Angelino 5:41cb6fa198f3 186 #define BR_PDB_SC_LDOK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK)))
screamer 0:c5e2f793b59a 187
screamer 0:c5e2f793b59a 188 /*! @brief Format value for bitfield PDB_SC_LDOK. */
screamer 0:c5e2f793b59a 189 #define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
screamer 0:c5e2f793b59a 190
screamer 0:c5e2f793b59a 191 /*! @brief Set the LDOK field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 192 #define BW_PDB_SC_LDOK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK), v))
screamer 0:c5e2f793b59a 193 /*@}*/
screamer 0:c5e2f793b59a 194
screamer 0:c5e2f793b59a 195 /*!
screamer 0:c5e2f793b59a 196 * @name Register PDB_SC, field CONT[1] (RW)
screamer 0:c5e2f793b59a 197 *
screamer 0:c5e2f793b59a 198 * Enables the PDB operation in Continuous mode.
screamer 0:c5e2f793b59a 199 *
screamer 0:c5e2f793b59a 200 * Values:
screamer 0:c5e2f793b59a 201 * - 0 - PDB operation in One-Shot mode
screamer 0:c5e2f793b59a 202 * - 1 - PDB operation in Continuous mode
screamer 0:c5e2f793b59a 203 */
screamer 0:c5e2f793b59a 204 /*@{*/
screamer 0:c5e2f793b59a 205 #define BP_PDB_SC_CONT (1U) /*!< Bit position for PDB_SC_CONT. */
screamer 0:c5e2f793b59a 206 #define BM_PDB_SC_CONT (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */
screamer 0:c5e2f793b59a 207 #define BS_PDB_SC_CONT (1U) /*!< Bit field size in bits for PDB_SC_CONT. */
screamer 0:c5e2f793b59a 208
screamer 0:c5e2f793b59a 209 /*! @brief Read current value of the PDB_SC_CONT field. */
Alessandro Angelino 5:41cb6fa198f3 210 #define BR_PDB_SC_CONT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT)))
screamer 0:c5e2f793b59a 211
screamer 0:c5e2f793b59a 212 /*! @brief Format value for bitfield PDB_SC_CONT. */
screamer 0:c5e2f793b59a 213 #define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
screamer 0:c5e2f793b59a 214
screamer 0:c5e2f793b59a 215 /*! @brief Set the CONT field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 216 #define BW_PDB_SC_CONT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT), v))
screamer 0:c5e2f793b59a 217 /*@}*/
screamer 0:c5e2f793b59a 218
screamer 0:c5e2f793b59a 219 /*!
screamer 0:c5e2f793b59a 220 * @name Register PDB_SC, field MULT[3:2] (RW)
screamer 0:c5e2f793b59a 221 *
screamer 0:c5e2f793b59a 222 * Selects the multiplication factor of the prescaler divider for the counter
screamer 0:c5e2f793b59a 223 * clock.
screamer 0:c5e2f793b59a 224 *
screamer 0:c5e2f793b59a 225 * Values:
screamer 0:c5e2f793b59a 226 * - 00 - Multiplication factor is 1.
screamer 0:c5e2f793b59a 227 * - 01 - Multiplication factor is 10.
screamer 0:c5e2f793b59a 228 * - 10 - Multiplication factor is 20.
screamer 0:c5e2f793b59a 229 * - 11 - Multiplication factor is 40.
screamer 0:c5e2f793b59a 230 */
screamer 0:c5e2f793b59a 231 /*@{*/
screamer 0:c5e2f793b59a 232 #define BP_PDB_SC_MULT (2U) /*!< Bit position for PDB_SC_MULT. */
screamer 0:c5e2f793b59a 233 #define BM_PDB_SC_MULT (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */
screamer 0:c5e2f793b59a 234 #define BS_PDB_SC_MULT (2U) /*!< Bit field size in bits for PDB_SC_MULT. */
screamer 0:c5e2f793b59a 235
screamer 0:c5e2f793b59a 236 /*! @brief Read current value of the PDB_SC_MULT field. */
Alessandro Angelino 5:41cb6fa198f3 237 #define BR_PDB_SC_MULT(x) (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.MULT))
screamer 0:c5e2f793b59a 238
screamer 0:c5e2f793b59a 239 /*! @brief Format value for bitfield PDB_SC_MULT. */
screamer 0:c5e2f793b59a 240 #define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
screamer 0:c5e2f793b59a 241
screamer 0:c5e2f793b59a 242 /*! @brief Set the MULT field to a new value. */
screamer 0:c5e2f793b59a 243 #define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
screamer 0:c5e2f793b59a 244 /*@}*/
screamer 0:c5e2f793b59a 245
screamer 0:c5e2f793b59a 246 /*!
screamer 0:c5e2f793b59a 247 * @name Register PDB_SC, field PDBIE[5] (RW)
screamer 0:c5e2f793b59a 248 *
screamer 0:c5e2f793b59a 249 * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
screamer 0:c5e2f793b59a 250 * generates a PDB interrupt.
screamer 0:c5e2f793b59a 251 *
screamer 0:c5e2f793b59a 252 * Values:
screamer 0:c5e2f793b59a 253 * - 0 - PDB interrupt disabled.
screamer 0:c5e2f793b59a 254 * - 1 - PDB interrupt enabled.
screamer 0:c5e2f793b59a 255 */
screamer 0:c5e2f793b59a 256 /*@{*/
screamer 0:c5e2f793b59a 257 #define BP_PDB_SC_PDBIE (5U) /*!< Bit position for PDB_SC_PDBIE. */
screamer 0:c5e2f793b59a 258 #define BM_PDB_SC_PDBIE (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */
screamer 0:c5e2f793b59a 259 #define BS_PDB_SC_PDBIE (1U) /*!< Bit field size in bits for PDB_SC_PDBIE. */
screamer 0:c5e2f793b59a 260
screamer 0:c5e2f793b59a 261 /*! @brief Read current value of the PDB_SC_PDBIE field. */
Alessandro Angelino 5:41cb6fa198f3 262 #define BR_PDB_SC_PDBIE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE)))
screamer 0:c5e2f793b59a 263
screamer 0:c5e2f793b59a 264 /*! @brief Format value for bitfield PDB_SC_PDBIE. */
screamer 0:c5e2f793b59a 265 #define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
screamer 0:c5e2f793b59a 266
screamer 0:c5e2f793b59a 267 /*! @brief Set the PDBIE field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 268 #define BW_PDB_SC_PDBIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE), v))
screamer 0:c5e2f793b59a 269 /*@}*/
screamer 0:c5e2f793b59a 270
screamer 0:c5e2f793b59a 271 /*!
screamer 0:c5e2f793b59a 272 * @name Register PDB_SC, field PDBIF[6] (RW)
screamer 0:c5e2f793b59a 273 *
screamer 0:c5e2f793b59a 274 * This field is set when the counter value is equal to the IDLY register.
screamer 0:c5e2f793b59a 275 * Writing zero clears this field.
screamer 0:c5e2f793b59a 276 */
screamer 0:c5e2f793b59a 277 /*@{*/
screamer 0:c5e2f793b59a 278 #define BP_PDB_SC_PDBIF (6U) /*!< Bit position for PDB_SC_PDBIF. */
screamer 0:c5e2f793b59a 279 #define BM_PDB_SC_PDBIF (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */
screamer 0:c5e2f793b59a 280 #define BS_PDB_SC_PDBIF (1U) /*!< Bit field size in bits for PDB_SC_PDBIF. */
screamer 0:c5e2f793b59a 281
screamer 0:c5e2f793b59a 282 /*! @brief Read current value of the PDB_SC_PDBIF field. */
Alessandro Angelino 5:41cb6fa198f3 283 #define BR_PDB_SC_PDBIF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF)))
screamer 0:c5e2f793b59a 284
screamer 0:c5e2f793b59a 285 /*! @brief Format value for bitfield PDB_SC_PDBIF. */
screamer 0:c5e2f793b59a 286 #define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
screamer 0:c5e2f793b59a 287
screamer 0:c5e2f793b59a 288 /*! @brief Set the PDBIF field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 289 #define BW_PDB_SC_PDBIF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF), v))
screamer 0:c5e2f793b59a 290 /*@}*/
screamer 0:c5e2f793b59a 291
screamer 0:c5e2f793b59a 292 /*!
screamer 0:c5e2f793b59a 293 * @name Register PDB_SC, field PDBEN[7] (RW)
screamer 0:c5e2f793b59a 294 *
screamer 0:c5e2f793b59a 295 * Values:
screamer 0:c5e2f793b59a 296 * - 0 - PDB disabled. Counter is off.
screamer 0:c5e2f793b59a 297 * - 1 - PDB enabled.
screamer 0:c5e2f793b59a 298 */
screamer 0:c5e2f793b59a 299 /*@{*/
screamer 0:c5e2f793b59a 300 #define BP_PDB_SC_PDBEN (7U) /*!< Bit position for PDB_SC_PDBEN. */
screamer 0:c5e2f793b59a 301 #define BM_PDB_SC_PDBEN (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */
screamer 0:c5e2f793b59a 302 #define BS_PDB_SC_PDBEN (1U) /*!< Bit field size in bits for PDB_SC_PDBEN. */
screamer 0:c5e2f793b59a 303
screamer 0:c5e2f793b59a 304 /*! @brief Read current value of the PDB_SC_PDBEN field. */
Alessandro Angelino 5:41cb6fa198f3 305 #define BR_PDB_SC_PDBEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN)))
screamer 0:c5e2f793b59a 306
screamer 0:c5e2f793b59a 307 /*! @brief Format value for bitfield PDB_SC_PDBEN. */
screamer 0:c5e2f793b59a 308 #define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
screamer 0:c5e2f793b59a 309
screamer 0:c5e2f793b59a 310 /*! @brief Set the PDBEN field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 311 #define BW_PDB_SC_PDBEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN), v))
screamer 0:c5e2f793b59a 312 /*@}*/
screamer 0:c5e2f793b59a 313
screamer 0:c5e2f793b59a 314 /*!
screamer 0:c5e2f793b59a 315 * @name Register PDB_SC, field TRGSEL[11:8] (RW)
screamer 0:c5e2f793b59a 316 *
screamer 0:c5e2f793b59a 317 * Selects the trigger input source for the PDB. The trigger input source can be
screamer 0:c5e2f793b59a 318 * internal or external (EXTRG pin), or the software trigger. Refer to chip
screamer 0:c5e2f793b59a 319 * configuration details for the actual PDB input trigger connections.
screamer 0:c5e2f793b59a 320 *
screamer 0:c5e2f793b59a 321 * Values:
screamer 0:c5e2f793b59a 322 * - 0000 - Trigger-In 0 is selected.
screamer 0:c5e2f793b59a 323 * - 0001 - Trigger-In 1 is selected.
screamer 0:c5e2f793b59a 324 * - 0010 - Trigger-In 2 is selected.
screamer 0:c5e2f793b59a 325 * - 0011 - Trigger-In 3 is selected.
screamer 0:c5e2f793b59a 326 * - 0100 - Trigger-In 4 is selected.
screamer 0:c5e2f793b59a 327 * - 0101 - Trigger-In 5 is selected.
screamer 0:c5e2f793b59a 328 * - 0110 - Trigger-In 6 is selected.
screamer 0:c5e2f793b59a 329 * - 0111 - Trigger-In 7 is selected.
screamer 0:c5e2f793b59a 330 * - 1000 - Trigger-In 8 is selected.
screamer 0:c5e2f793b59a 331 * - 1001 - Trigger-In 9 is selected.
screamer 0:c5e2f793b59a 332 * - 1010 - Trigger-In 10 is selected.
screamer 0:c5e2f793b59a 333 * - 1011 - Trigger-In 11 is selected.
screamer 0:c5e2f793b59a 334 * - 1100 - Trigger-In 12 is selected.
screamer 0:c5e2f793b59a 335 * - 1101 - Trigger-In 13 is selected.
screamer 0:c5e2f793b59a 336 * - 1110 - Trigger-In 14 is selected.
screamer 0:c5e2f793b59a 337 * - 1111 - Software trigger is selected.
screamer 0:c5e2f793b59a 338 */
screamer 0:c5e2f793b59a 339 /*@{*/
screamer 0:c5e2f793b59a 340 #define BP_PDB_SC_TRGSEL (8U) /*!< Bit position for PDB_SC_TRGSEL. */
screamer 0:c5e2f793b59a 341 #define BM_PDB_SC_TRGSEL (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */
screamer 0:c5e2f793b59a 342 #define BS_PDB_SC_TRGSEL (4U) /*!< Bit field size in bits for PDB_SC_TRGSEL. */
screamer 0:c5e2f793b59a 343
screamer 0:c5e2f793b59a 344 /*! @brief Read current value of the PDB_SC_TRGSEL field. */
Alessandro Angelino 5:41cb6fa198f3 345 #define BR_PDB_SC_TRGSEL(x) (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.TRGSEL))
screamer 0:c5e2f793b59a 346
screamer 0:c5e2f793b59a 347 /*! @brief Format value for bitfield PDB_SC_TRGSEL. */
screamer 0:c5e2f793b59a 348 #define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
screamer 0:c5e2f793b59a 349
screamer 0:c5e2f793b59a 350 /*! @brief Set the TRGSEL field to a new value. */
screamer 0:c5e2f793b59a 351 #define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
screamer 0:c5e2f793b59a 352 /*@}*/
screamer 0:c5e2f793b59a 353
screamer 0:c5e2f793b59a 354 /*!
screamer 0:c5e2f793b59a 355 * @name Register PDB_SC, field PRESCALER[14:12] (RW)
screamer 0:c5e2f793b59a 356 *
screamer 0:c5e2f793b59a 357 * Values:
screamer 0:c5e2f793b59a 358 * - 000 - Counting uses the peripheral clock divided by multiplication factor
screamer 0:c5e2f793b59a 359 * selected by MULT.
screamer 0:c5e2f793b59a 360 * - 001 - Counting uses the peripheral clock divided by twice of the
screamer 0:c5e2f793b59a 361 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 362 * - 010 - Counting uses the peripheral clock divided by four times of the
screamer 0:c5e2f793b59a 363 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 364 * - 011 - Counting uses the peripheral clock divided by eight times of the
screamer 0:c5e2f793b59a 365 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 366 * - 100 - Counting uses the peripheral clock divided by 16 times of the
screamer 0:c5e2f793b59a 367 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 368 * - 101 - Counting uses the peripheral clock divided by 32 times of the
screamer 0:c5e2f793b59a 369 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 370 * - 110 - Counting uses the peripheral clock divided by 64 times of the
screamer 0:c5e2f793b59a 371 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 372 * - 111 - Counting uses the peripheral clock divided by 128 times of the
screamer 0:c5e2f793b59a 373 * multiplication factor selected by MULT.
screamer 0:c5e2f793b59a 374 */
screamer 0:c5e2f793b59a 375 /*@{*/
screamer 0:c5e2f793b59a 376 #define BP_PDB_SC_PRESCALER (12U) /*!< Bit position for PDB_SC_PRESCALER. */
screamer 0:c5e2f793b59a 377 #define BM_PDB_SC_PRESCALER (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */
screamer 0:c5e2f793b59a 378 #define BS_PDB_SC_PRESCALER (3U) /*!< Bit field size in bits for PDB_SC_PRESCALER. */
screamer 0:c5e2f793b59a 379
screamer 0:c5e2f793b59a 380 /*! @brief Read current value of the PDB_SC_PRESCALER field. */
Alessandro Angelino 5:41cb6fa198f3 381 #define BR_PDB_SC_PRESCALER(x) (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.PRESCALER))
screamer 0:c5e2f793b59a 382
screamer 0:c5e2f793b59a 383 /*! @brief Format value for bitfield PDB_SC_PRESCALER. */
screamer 0:c5e2f793b59a 384 #define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
screamer 0:c5e2f793b59a 385
screamer 0:c5e2f793b59a 386 /*! @brief Set the PRESCALER field to a new value. */
screamer 0:c5e2f793b59a 387 #define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
screamer 0:c5e2f793b59a 388 /*@}*/
screamer 0:c5e2f793b59a 389
screamer 0:c5e2f793b59a 390 /*!
screamer 0:c5e2f793b59a 391 * @name Register PDB_SC, field DMAEN[15] (RW)
screamer 0:c5e2f793b59a 392 *
screamer 0:c5e2f793b59a 393 * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
screamer 0:c5e2f793b59a 394 * interrupt.
screamer 0:c5e2f793b59a 395 *
screamer 0:c5e2f793b59a 396 * Values:
screamer 0:c5e2f793b59a 397 * - 0 - DMA disabled.
screamer 0:c5e2f793b59a 398 * - 1 - DMA enabled.
screamer 0:c5e2f793b59a 399 */
screamer 0:c5e2f793b59a 400 /*@{*/
screamer 0:c5e2f793b59a 401 #define BP_PDB_SC_DMAEN (15U) /*!< Bit position for PDB_SC_DMAEN. */
screamer 0:c5e2f793b59a 402 #define BM_PDB_SC_DMAEN (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */
screamer 0:c5e2f793b59a 403 #define BS_PDB_SC_DMAEN (1U) /*!< Bit field size in bits for PDB_SC_DMAEN. */
screamer 0:c5e2f793b59a 404
screamer 0:c5e2f793b59a 405 /*! @brief Read current value of the PDB_SC_DMAEN field. */
Alessandro Angelino 5:41cb6fa198f3 406 #define BR_PDB_SC_DMAEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN)))
screamer 0:c5e2f793b59a 407
screamer 0:c5e2f793b59a 408 /*! @brief Format value for bitfield PDB_SC_DMAEN. */
screamer 0:c5e2f793b59a 409 #define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
screamer 0:c5e2f793b59a 410
screamer 0:c5e2f793b59a 411 /*! @brief Set the DMAEN field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 412 #define BW_PDB_SC_DMAEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN), v))
screamer 0:c5e2f793b59a 413 /*@}*/
screamer 0:c5e2f793b59a 414
screamer 0:c5e2f793b59a 415 /*!
screamer 0:c5e2f793b59a 416 * @name Register PDB_SC, field SWTRIG[16] (WORZ)
screamer 0:c5e2f793b59a 417 *
screamer 0:c5e2f793b59a 418 * When PDB is enabled and the software trigger is selected as the trigger input
screamer 0:c5e2f793b59a 419 * source, writing 1 to this field resets and restarts the counter. Writing 0 to
screamer 0:c5e2f793b59a 420 * this field has no effect. Reading this field results 0.
screamer 0:c5e2f793b59a 421 */
screamer 0:c5e2f793b59a 422 /*@{*/
screamer 0:c5e2f793b59a 423 #define BP_PDB_SC_SWTRIG (16U) /*!< Bit position for PDB_SC_SWTRIG. */
screamer 0:c5e2f793b59a 424 #define BM_PDB_SC_SWTRIG (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */
screamer 0:c5e2f793b59a 425 #define BS_PDB_SC_SWTRIG (1U) /*!< Bit field size in bits for PDB_SC_SWTRIG. */
screamer 0:c5e2f793b59a 426
screamer 0:c5e2f793b59a 427 /*! @brief Format value for bitfield PDB_SC_SWTRIG. */
screamer 0:c5e2f793b59a 428 #define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
screamer 0:c5e2f793b59a 429
screamer 0:c5e2f793b59a 430 /*! @brief Set the SWTRIG field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 431 #define BW_PDB_SC_SWTRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG), v))
screamer 0:c5e2f793b59a 432 /*@}*/
screamer 0:c5e2f793b59a 433
screamer 0:c5e2f793b59a 434 /*!
screamer 0:c5e2f793b59a 435 * @name Register PDB_SC, field PDBEIE[17] (RW)
screamer 0:c5e2f793b59a 436 *
screamer 0:c5e2f793b59a 437 * Enables the PDB sequence error interrupt. When this field is set, any of the
screamer 0:c5e2f793b59a 438 * PDB channel sequence error flags generates a PDB sequence error interrupt.
screamer 0:c5e2f793b59a 439 *
screamer 0:c5e2f793b59a 440 * Values:
screamer 0:c5e2f793b59a 441 * - 0 - PDB sequence error interrupt disabled.
screamer 0:c5e2f793b59a 442 * - 1 - PDB sequence error interrupt enabled.
screamer 0:c5e2f793b59a 443 */
screamer 0:c5e2f793b59a 444 /*@{*/
screamer 0:c5e2f793b59a 445 #define BP_PDB_SC_PDBEIE (17U) /*!< Bit position for PDB_SC_PDBEIE. */
screamer 0:c5e2f793b59a 446 #define BM_PDB_SC_PDBEIE (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */
screamer 0:c5e2f793b59a 447 #define BS_PDB_SC_PDBEIE (1U) /*!< Bit field size in bits for PDB_SC_PDBEIE. */
screamer 0:c5e2f793b59a 448
screamer 0:c5e2f793b59a 449 /*! @brief Read current value of the PDB_SC_PDBEIE field. */
Alessandro Angelino 5:41cb6fa198f3 450 #define BR_PDB_SC_PDBEIE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE)))
screamer 0:c5e2f793b59a 451
screamer 0:c5e2f793b59a 452 /*! @brief Format value for bitfield PDB_SC_PDBEIE. */
screamer 0:c5e2f793b59a 453 #define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
screamer 0:c5e2f793b59a 454
screamer 0:c5e2f793b59a 455 /*! @brief Set the PDBEIE field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 456 #define BW_PDB_SC_PDBEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE), v))
screamer 0:c5e2f793b59a 457 /*@}*/
screamer 0:c5e2f793b59a 458
screamer 0:c5e2f793b59a 459 /*!
screamer 0:c5e2f793b59a 460 * @name Register PDB_SC, field LDMOD[19:18] (RW)
screamer 0:c5e2f793b59a 461 *
screamer 0:c5e2f793b59a 462 * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
screamer 0:c5e2f793b59a 463 * after 1 is written to LDOK.
screamer 0:c5e2f793b59a 464 *
screamer 0:c5e2f793b59a 465 * Values:
screamer 0:c5e2f793b59a 466 * - 00 - The internal registers are loaded with the values from their buffers
screamer 0:c5e2f793b59a 467 * immediately after 1 is written to LDOK.
screamer 0:c5e2f793b59a 468 * - 01 - The internal registers are loaded with the values from their buffers
screamer 0:c5e2f793b59a 469 * when the PDB counter reaches the MOD register value after 1 is written to
screamer 0:c5e2f793b59a 470 * LDOK.
screamer 0:c5e2f793b59a 471 * - 10 - The internal registers are loaded with the values from their buffers
screamer 0:c5e2f793b59a 472 * when a trigger input event is detected after 1 is written to LDOK.
screamer 0:c5e2f793b59a 473 * - 11 - The internal registers are loaded with the values from their buffers
screamer 0:c5e2f793b59a 474 * when either the PDB counter reaches the MOD register value or a trigger
screamer 0:c5e2f793b59a 475 * input event is detected, after 1 is written to LDOK.
screamer 0:c5e2f793b59a 476 */
screamer 0:c5e2f793b59a 477 /*@{*/
screamer 0:c5e2f793b59a 478 #define BP_PDB_SC_LDMOD (18U) /*!< Bit position for PDB_SC_LDMOD. */
screamer 0:c5e2f793b59a 479 #define BM_PDB_SC_LDMOD (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */
screamer 0:c5e2f793b59a 480 #define BS_PDB_SC_LDMOD (2U) /*!< Bit field size in bits for PDB_SC_LDMOD. */
screamer 0:c5e2f793b59a 481
screamer 0:c5e2f793b59a 482 /*! @brief Read current value of the PDB_SC_LDMOD field. */
Alessandro Angelino 5:41cb6fa198f3 483 #define BR_PDB_SC_LDMOD(x) (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.LDMOD))
screamer 0:c5e2f793b59a 484
screamer 0:c5e2f793b59a 485 /*! @brief Format value for bitfield PDB_SC_LDMOD. */
screamer 0:c5e2f793b59a 486 #define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
screamer 0:c5e2f793b59a 487
screamer 0:c5e2f793b59a 488 /*! @brief Set the LDMOD field to a new value. */
screamer 0:c5e2f793b59a 489 #define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
screamer 0:c5e2f793b59a 490 /*@}*/
screamer 0:c5e2f793b59a 491
screamer 0:c5e2f793b59a 492 /*******************************************************************************
screamer 0:c5e2f793b59a 493 * HW_PDB_MOD - Modulus register
screamer 0:c5e2f793b59a 494 ******************************************************************************/
screamer 0:c5e2f793b59a 495
screamer 0:c5e2f793b59a 496 /*!
screamer 0:c5e2f793b59a 497 * @brief HW_PDB_MOD - Modulus register (RW)
screamer 0:c5e2f793b59a 498 *
screamer 0:c5e2f793b59a 499 * Reset value: 0x0000FFFFU
screamer 0:c5e2f793b59a 500 */
screamer 0:c5e2f793b59a 501 typedef union _hw_pdb_mod
screamer 0:c5e2f793b59a 502 {
screamer 0:c5e2f793b59a 503 uint32_t U;
screamer 0:c5e2f793b59a 504 struct _hw_pdb_mod_bitfields
screamer 0:c5e2f793b59a 505 {
screamer 0:c5e2f793b59a 506 uint32_t MOD : 16; /*!< [15:0] PDB Modulus */
screamer 0:c5e2f793b59a 507 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 508 } B;
screamer 0:c5e2f793b59a 509 } hw_pdb_mod_t;
screamer 0:c5e2f793b59a 510
screamer 0:c5e2f793b59a 511 /*!
screamer 0:c5e2f793b59a 512 * @name Constants and macros for entire PDB_MOD register
screamer 0:c5e2f793b59a 513 */
screamer 0:c5e2f793b59a 514 /*@{*/
screamer 0:c5e2f793b59a 515 #define HW_PDB_MOD_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 516
screamer 0:c5e2f793b59a 517 #define HW_PDB_MOD(x) (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 518 #define HW_PDB_MOD_RD(x) (ADDRESS_READ(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 519 #define HW_PDB_MOD_WR(x, v) (ADDRESS_WRITE(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x), v))
screamer 0:c5e2f793b59a 520 #define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) | (v)))
screamer 0:c5e2f793b59a 521 #define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 522 #define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 523 /*@}*/
screamer 0:c5e2f793b59a 524
screamer 0:c5e2f793b59a 525 /*
screamer 0:c5e2f793b59a 526 * Constants & macros for individual PDB_MOD bitfields
screamer 0:c5e2f793b59a 527 */
screamer 0:c5e2f793b59a 528
screamer 0:c5e2f793b59a 529 /*!
screamer 0:c5e2f793b59a 530 * @name Register PDB_MOD, field MOD[15:0] (RW)
screamer 0:c5e2f793b59a 531 *
screamer 0:c5e2f793b59a 532 * Specifies the period of the counter. When the counter reaches this value, it
screamer 0:c5e2f793b59a 533 * will be reset back to zero. If the PDB is in Continuous mode, the count begins
screamer 0:c5e2f793b59a 534 * anew. Reading this field returns the value of the internal register that is
screamer 0:c5e2f793b59a 535 * effective for the current cycle of PDB.
screamer 0:c5e2f793b59a 536 */
screamer 0:c5e2f793b59a 537 /*@{*/
screamer 0:c5e2f793b59a 538 #define BP_PDB_MOD_MOD (0U) /*!< Bit position for PDB_MOD_MOD. */
screamer 0:c5e2f793b59a 539 #define BM_PDB_MOD_MOD (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */
screamer 0:c5e2f793b59a 540 #define BS_PDB_MOD_MOD (16U) /*!< Bit field size in bits for PDB_MOD_MOD. */
screamer 0:c5e2f793b59a 541
screamer 0:c5e2f793b59a 542 /*! @brief Read current value of the PDB_MOD_MOD field. */
Alessandro Angelino 5:41cb6fa198f3 543 #define BR_PDB_MOD_MOD(x) (UNION_READ(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x), U, B.MOD))
screamer 0:c5e2f793b59a 544
screamer 0:c5e2f793b59a 545 /*! @brief Format value for bitfield PDB_MOD_MOD. */
screamer 0:c5e2f793b59a 546 #define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
screamer 0:c5e2f793b59a 547
screamer 0:c5e2f793b59a 548 /*! @brief Set the MOD field to a new value. */
screamer 0:c5e2f793b59a 549 #define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
screamer 0:c5e2f793b59a 550 /*@}*/
screamer 0:c5e2f793b59a 551
screamer 0:c5e2f793b59a 552 /*******************************************************************************
screamer 0:c5e2f793b59a 553 * HW_PDB_CNT - Counter register
screamer 0:c5e2f793b59a 554 ******************************************************************************/
screamer 0:c5e2f793b59a 555
screamer 0:c5e2f793b59a 556 /*!
screamer 0:c5e2f793b59a 557 * @brief HW_PDB_CNT - Counter register (RO)
screamer 0:c5e2f793b59a 558 *
screamer 0:c5e2f793b59a 559 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 560 */
screamer 0:c5e2f793b59a 561 typedef union _hw_pdb_cnt
screamer 0:c5e2f793b59a 562 {
screamer 0:c5e2f793b59a 563 uint32_t U;
screamer 0:c5e2f793b59a 564 struct _hw_pdb_cnt_bitfields
screamer 0:c5e2f793b59a 565 {
screamer 0:c5e2f793b59a 566 uint32_t CNT : 16; /*!< [15:0] PDB Counter */
screamer 0:c5e2f793b59a 567 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 568 } B;
screamer 0:c5e2f793b59a 569 } hw_pdb_cnt_t;
screamer 0:c5e2f793b59a 570
screamer 0:c5e2f793b59a 571 /*!
screamer 0:c5e2f793b59a 572 * @name Constants and macros for entire PDB_CNT register
screamer 0:c5e2f793b59a 573 */
screamer 0:c5e2f793b59a 574 /*@{*/
screamer 0:c5e2f793b59a 575 #define HW_PDB_CNT_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 576
screamer 0:c5e2f793b59a 577 #define HW_PDB_CNT(x) (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 578 #define HW_PDB_CNT_RD(x) (ADDRESS_READ(hw_pdb_cnt_t, HW_PDB_CNT_ADDR(x)))
screamer 0:c5e2f793b59a 579 /*@}*/
screamer 0:c5e2f793b59a 580
screamer 0:c5e2f793b59a 581 /*
screamer 0:c5e2f793b59a 582 * Constants & macros for individual PDB_CNT bitfields
screamer 0:c5e2f793b59a 583 */
screamer 0:c5e2f793b59a 584
screamer 0:c5e2f793b59a 585 /*!
screamer 0:c5e2f793b59a 586 * @name Register PDB_CNT, field CNT[15:0] (RO)
screamer 0:c5e2f793b59a 587 *
screamer 0:c5e2f793b59a 588 * Contains the current value of the counter.
screamer 0:c5e2f793b59a 589 */
screamer 0:c5e2f793b59a 590 /*@{*/
screamer 0:c5e2f793b59a 591 #define BP_PDB_CNT_CNT (0U) /*!< Bit position for PDB_CNT_CNT. */
screamer 0:c5e2f793b59a 592 #define BM_PDB_CNT_CNT (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */
screamer 0:c5e2f793b59a 593 #define BS_PDB_CNT_CNT (16U) /*!< Bit field size in bits for PDB_CNT_CNT. */
screamer 0:c5e2f793b59a 594
screamer 0:c5e2f793b59a 595 /*! @brief Read current value of the PDB_CNT_CNT field. */
Alessandro Angelino 5:41cb6fa198f3 596 #define BR_PDB_CNT_CNT(x) (UNION_READ(hw_pdb_cnt_t, HW_PDB_CNT_ADDR(x), U, B.CNT))
screamer 0:c5e2f793b59a 597 /*@}*/
screamer 0:c5e2f793b59a 598
screamer 0:c5e2f793b59a 599 /*******************************************************************************
screamer 0:c5e2f793b59a 600 * HW_PDB_IDLY - Interrupt Delay register
screamer 0:c5e2f793b59a 601 ******************************************************************************/
screamer 0:c5e2f793b59a 602
screamer 0:c5e2f793b59a 603 /*!
screamer 0:c5e2f793b59a 604 * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
screamer 0:c5e2f793b59a 605 *
screamer 0:c5e2f793b59a 606 * Reset value: 0x0000FFFFU
screamer 0:c5e2f793b59a 607 */
screamer 0:c5e2f793b59a 608 typedef union _hw_pdb_idly
screamer 0:c5e2f793b59a 609 {
screamer 0:c5e2f793b59a 610 uint32_t U;
screamer 0:c5e2f793b59a 611 struct _hw_pdb_idly_bitfields
screamer 0:c5e2f793b59a 612 {
screamer 0:c5e2f793b59a 613 uint32_t IDLY : 16; /*!< [15:0] PDB Interrupt Delay */
screamer 0:c5e2f793b59a 614 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 615 } B;
screamer 0:c5e2f793b59a 616 } hw_pdb_idly_t;
screamer 0:c5e2f793b59a 617
screamer 0:c5e2f793b59a 618 /*!
screamer 0:c5e2f793b59a 619 * @name Constants and macros for entire PDB_IDLY register
screamer 0:c5e2f793b59a 620 */
screamer 0:c5e2f793b59a 621 /*@{*/
screamer 0:c5e2f793b59a 622 #define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU)
screamer 0:c5e2f793b59a 623
screamer 0:c5e2f793b59a 624 #define HW_PDB_IDLY(x) (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 625 #define HW_PDB_IDLY_RD(x) (ADDRESS_READ(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 626 #define HW_PDB_IDLY_WR(x, v) (ADDRESS_WRITE(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x), v))
screamer 0:c5e2f793b59a 627 #define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) | (v)))
screamer 0:c5e2f793b59a 628 #define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 629 #define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 630 /*@}*/
screamer 0:c5e2f793b59a 631
screamer 0:c5e2f793b59a 632 /*
screamer 0:c5e2f793b59a 633 * Constants & macros for individual PDB_IDLY bitfields
screamer 0:c5e2f793b59a 634 */
screamer 0:c5e2f793b59a 635
screamer 0:c5e2f793b59a 636 /*!
screamer 0:c5e2f793b59a 637 * @name Register PDB_IDLY, field IDLY[15:0] (RW)
screamer 0:c5e2f793b59a 638 *
screamer 0:c5e2f793b59a 639 * Specifies the delay value to schedule the PDB interrupt. It can be used to
screamer 0:c5e2f793b59a 640 * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
screamer 0:c5e2f793b59a 641 * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
screamer 0:c5e2f793b59a 642 * this field returns the value of internal register that is effective for the
screamer 0:c5e2f793b59a 643 * current cycle of the PDB.
screamer 0:c5e2f793b59a 644 */
screamer 0:c5e2f793b59a 645 /*@{*/
screamer 0:c5e2f793b59a 646 #define BP_PDB_IDLY_IDLY (0U) /*!< Bit position for PDB_IDLY_IDLY. */
screamer 0:c5e2f793b59a 647 #define BM_PDB_IDLY_IDLY (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */
screamer 0:c5e2f793b59a 648 #define BS_PDB_IDLY_IDLY (16U) /*!< Bit field size in bits for PDB_IDLY_IDLY. */
screamer 0:c5e2f793b59a 649
screamer 0:c5e2f793b59a 650 /*! @brief Read current value of the PDB_IDLY_IDLY field. */
Alessandro Angelino 5:41cb6fa198f3 651 #define BR_PDB_IDLY_IDLY(x) (UNION_READ(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x), U, B.IDLY))
screamer 0:c5e2f793b59a 652
screamer 0:c5e2f793b59a 653 /*! @brief Format value for bitfield PDB_IDLY_IDLY. */
screamer 0:c5e2f793b59a 654 #define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
screamer 0:c5e2f793b59a 655
screamer 0:c5e2f793b59a 656 /*! @brief Set the IDLY field to a new value. */
screamer 0:c5e2f793b59a 657 #define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
screamer 0:c5e2f793b59a 658 /*@}*/
screamer 0:c5e2f793b59a 659
screamer 0:c5e2f793b59a 660 /*******************************************************************************
screamer 0:c5e2f793b59a 661 * HW_PDB_CHnC1 - Channel n Control register 1
screamer 0:c5e2f793b59a 662 ******************************************************************************/
screamer 0:c5e2f793b59a 663
screamer 0:c5e2f793b59a 664 /*!
screamer 0:c5e2f793b59a 665 * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
screamer 0:c5e2f793b59a 666 *
screamer 0:c5e2f793b59a 667 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 668 *
screamer 0:c5e2f793b59a 669 * Each PDB channel has one control register, CHnC1. The bits in this register
screamer 0:c5e2f793b59a 670 * control the functionality of each PDB channel operation.
screamer 0:c5e2f793b59a 671 */
screamer 0:c5e2f793b59a 672 typedef union _hw_pdb_chnc1
screamer 0:c5e2f793b59a 673 {
screamer 0:c5e2f793b59a 674 uint32_t U;
screamer 0:c5e2f793b59a 675 struct _hw_pdb_chnc1_bitfields
screamer 0:c5e2f793b59a 676 {
screamer 0:c5e2f793b59a 677 uint32_t EN : 8; /*!< [7:0] PDB Channel Pre-Trigger Enable */
screamer 0:c5e2f793b59a 678 uint32_t TOS : 8; /*!< [15:8] PDB Channel Pre-Trigger Output Select */
screamer 0:c5e2f793b59a 679 uint32_t BB : 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
screamer 0:c5e2f793b59a 680 * Operation Enable */
screamer 0:c5e2f793b59a 681 uint32_t RESERVED0 : 8; /*!< [31:24] */
screamer 0:c5e2f793b59a 682 } B;
screamer 0:c5e2f793b59a 683 } hw_pdb_chnc1_t;
screamer 0:c5e2f793b59a 684
screamer 0:c5e2f793b59a 685 /*!
screamer 0:c5e2f793b59a 686 * @name Constants and macros for entire PDB_CHnC1 register
screamer 0:c5e2f793b59a 687 */
screamer 0:c5e2f793b59a 688 /*@{*/
screamer 0:c5e2f793b59a 689 #define HW_PDB_CHnC1_COUNT (2U)
screamer 0:c5e2f793b59a 690
screamer 0:c5e2f793b59a 691 #define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n)))
screamer 0:c5e2f793b59a 692
screamer 0:c5e2f793b59a 693 #define HW_PDB_CHnC1(x, n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 694 #define HW_PDB_CHnC1_RD(x, n) (ADDRESS_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 695 #define HW_PDB_CHnC1_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), v))
screamer 0:c5e2f793b59a 696 #define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 697 #define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 698 #define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 699 /*@}*/
screamer 0:c5e2f793b59a 700
screamer 0:c5e2f793b59a 701 /*
screamer 0:c5e2f793b59a 702 * Constants & macros for individual PDB_CHnC1 bitfields
screamer 0:c5e2f793b59a 703 */
screamer 0:c5e2f793b59a 704
screamer 0:c5e2f793b59a 705 /*!
screamer 0:c5e2f793b59a 706 * @name Register PDB_CHnC1, field EN[7:0] (RW)
screamer 0:c5e2f793b59a 707 *
screamer 0:c5e2f793b59a 708 * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
screamer 0:c5e2f793b59a 709 * bits are implemented in this MCU.
screamer 0:c5e2f793b59a 710 *
screamer 0:c5e2f793b59a 711 * Values:
screamer 0:c5e2f793b59a 712 * - 0 - PDB channel's corresponding pre-trigger disabled.
screamer 0:c5e2f793b59a 713 * - 1 - PDB channel's corresponding pre-trigger enabled.
screamer 0:c5e2f793b59a 714 */
screamer 0:c5e2f793b59a 715 /*@{*/
screamer 0:c5e2f793b59a 716 #define BP_PDB_CHnC1_EN (0U) /*!< Bit position for PDB_CHnC1_EN. */
screamer 0:c5e2f793b59a 717 #define BM_PDB_CHnC1_EN (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */
screamer 0:c5e2f793b59a 718 #define BS_PDB_CHnC1_EN (8U) /*!< Bit field size in bits for PDB_CHnC1_EN. */
screamer 0:c5e2f793b59a 719
screamer 0:c5e2f793b59a 720 /*! @brief Read current value of the PDB_CHnC1_EN field. */
Alessandro Angelino 5:41cb6fa198f3 721 #define BR_PDB_CHnC1_EN(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.EN))
screamer 0:c5e2f793b59a 722
screamer 0:c5e2f793b59a 723 /*! @brief Format value for bitfield PDB_CHnC1_EN. */
screamer 0:c5e2f793b59a 724 #define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
screamer 0:c5e2f793b59a 725
screamer 0:c5e2f793b59a 726 /*! @brief Set the EN field to a new value. */
screamer 0:c5e2f793b59a 727 #define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
screamer 0:c5e2f793b59a 728 /*@}*/
screamer 0:c5e2f793b59a 729
screamer 0:c5e2f793b59a 730 /*!
screamer 0:c5e2f793b59a 731 * @name Register PDB_CHnC1, field TOS[15:8] (RW)
screamer 0:c5e2f793b59a 732 *
screamer 0:c5e2f793b59a 733 * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
screamer 0:c5e2f793b59a 734 * implemented in this MCU.
screamer 0:c5e2f793b59a 735 *
screamer 0:c5e2f793b59a 736 * Values:
screamer 0:c5e2f793b59a 737 * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
screamer 0:c5e2f793b59a 738 * pre-trigger asserts one peripheral clock cycle after a rising edge is detected
screamer 0:c5e2f793b59a 739 * on selected trigger input source or software trigger is selected and SWTRIG
screamer 0:c5e2f793b59a 740 * is written with 1.
screamer 0:c5e2f793b59a 741 * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
screamer 0:c5e2f793b59a 742 * reaches the channel delay register and one peripheral clock cycle after a rising
screamer 0:c5e2f793b59a 743 * edge is detected on selected trigger input source or software trigger is
screamer 0:c5e2f793b59a 744 * selected and SETRIG is written with 1.
screamer 0:c5e2f793b59a 745 */
screamer 0:c5e2f793b59a 746 /*@{*/
screamer 0:c5e2f793b59a 747 #define BP_PDB_CHnC1_TOS (8U) /*!< Bit position for PDB_CHnC1_TOS. */
screamer 0:c5e2f793b59a 748 #define BM_PDB_CHnC1_TOS (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */
screamer 0:c5e2f793b59a 749 #define BS_PDB_CHnC1_TOS (8U) /*!< Bit field size in bits for PDB_CHnC1_TOS. */
screamer 0:c5e2f793b59a 750
screamer 0:c5e2f793b59a 751 /*! @brief Read current value of the PDB_CHnC1_TOS field. */
Alessandro Angelino 5:41cb6fa198f3 752 #define BR_PDB_CHnC1_TOS(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.TOS))
screamer 0:c5e2f793b59a 753
screamer 0:c5e2f793b59a 754 /*! @brief Format value for bitfield PDB_CHnC1_TOS. */
screamer 0:c5e2f793b59a 755 #define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
screamer 0:c5e2f793b59a 756
screamer 0:c5e2f793b59a 757 /*! @brief Set the TOS field to a new value. */
screamer 0:c5e2f793b59a 758 #define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
screamer 0:c5e2f793b59a 759 /*@}*/
screamer 0:c5e2f793b59a 760
screamer 0:c5e2f793b59a 761 /*!
screamer 0:c5e2f793b59a 762 * @name Register PDB_CHnC1, field BB[23:16] (RW)
screamer 0:c5e2f793b59a 763 *
screamer 0:c5e2f793b59a 764 * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
screamer 0:c5e2f793b59a 765 * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
screamer 0:c5e2f793b59a 766 * enables the ADC conversions complete to trigger the next PDB channel
screamer 0:c5e2f793b59a 767 * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
screamer 0:c5e2f793b59a 768 * set of configuration and results registers. Application code must only enable
screamer 0:c5e2f793b59a 769 * the back-to-back operation of the PDB pre-triggers at the leading of the
screamer 0:c5e2f793b59a 770 * back-to-back connection chain.
screamer 0:c5e2f793b59a 771 *
screamer 0:c5e2f793b59a 772 * Values:
screamer 0:c5e2f793b59a 773 * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
screamer 0:c5e2f793b59a 774 * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
screamer 0:c5e2f793b59a 775 */
screamer 0:c5e2f793b59a 776 /*@{*/
screamer 0:c5e2f793b59a 777 #define BP_PDB_CHnC1_BB (16U) /*!< Bit position for PDB_CHnC1_BB. */
screamer 0:c5e2f793b59a 778 #define BM_PDB_CHnC1_BB (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */
screamer 0:c5e2f793b59a 779 #define BS_PDB_CHnC1_BB (8U) /*!< Bit field size in bits for PDB_CHnC1_BB. */
screamer 0:c5e2f793b59a 780
screamer 0:c5e2f793b59a 781 /*! @brief Read current value of the PDB_CHnC1_BB field. */
Alessandro Angelino 5:41cb6fa198f3 782 #define BR_PDB_CHnC1_BB(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.BB))
screamer 0:c5e2f793b59a 783
screamer 0:c5e2f793b59a 784 /*! @brief Format value for bitfield PDB_CHnC1_BB. */
screamer 0:c5e2f793b59a 785 #define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
screamer 0:c5e2f793b59a 786
screamer 0:c5e2f793b59a 787 /*! @brief Set the BB field to a new value. */
screamer 0:c5e2f793b59a 788 #define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
screamer 0:c5e2f793b59a 789 /*@}*/
screamer 0:c5e2f793b59a 790 /*******************************************************************************
screamer 0:c5e2f793b59a 791 * HW_PDB_CHnS - Channel n Status register
screamer 0:c5e2f793b59a 792 ******************************************************************************/
screamer 0:c5e2f793b59a 793
screamer 0:c5e2f793b59a 794 /*!
screamer 0:c5e2f793b59a 795 * @brief HW_PDB_CHnS - Channel n Status register (RW)
screamer 0:c5e2f793b59a 796 *
screamer 0:c5e2f793b59a 797 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 798 */
screamer 0:c5e2f793b59a 799 typedef union _hw_pdb_chns
screamer 0:c5e2f793b59a 800 {
screamer 0:c5e2f793b59a 801 uint32_t U;
screamer 0:c5e2f793b59a 802 struct _hw_pdb_chns_bitfields
screamer 0:c5e2f793b59a 803 {
screamer 0:c5e2f793b59a 804 uint32_t ERR : 8; /*!< [7:0] PDB Channel Sequence Error Flags */
screamer 0:c5e2f793b59a 805 uint32_t RESERVED0 : 8; /*!< [15:8] */
screamer 0:c5e2f793b59a 806 uint32_t CF : 8; /*!< [23:16] PDB Channel Flags */
screamer 0:c5e2f793b59a 807 uint32_t RESERVED1 : 8; /*!< [31:24] */
screamer 0:c5e2f793b59a 808 } B;
screamer 0:c5e2f793b59a 809 } hw_pdb_chns_t;
screamer 0:c5e2f793b59a 810
screamer 0:c5e2f793b59a 811 /*!
screamer 0:c5e2f793b59a 812 * @name Constants and macros for entire PDB_CHnS register
screamer 0:c5e2f793b59a 813 */
screamer 0:c5e2f793b59a 814 /*@{*/
screamer 0:c5e2f793b59a 815 #define HW_PDB_CHnS_COUNT (2U)
screamer 0:c5e2f793b59a 816
screamer 0:c5e2f793b59a 817 #define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n)))
screamer 0:c5e2f793b59a 818
screamer 0:c5e2f793b59a 819 #define HW_PDB_CHnS(x, n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 820 #define HW_PDB_CHnS_RD(x, n) (ADDRESS_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 821 #define HW_PDB_CHnS_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), v))
screamer 0:c5e2f793b59a 822 #define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 823 #define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 824 #define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 825 /*@}*/
screamer 0:c5e2f793b59a 826
screamer 0:c5e2f793b59a 827 /*
screamer 0:c5e2f793b59a 828 * Constants & macros for individual PDB_CHnS bitfields
screamer 0:c5e2f793b59a 829 */
screamer 0:c5e2f793b59a 830
screamer 0:c5e2f793b59a 831 /*!
screamer 0:c5e2f793b59a 832 * @name Register PDB_CHnS, field ERR[7:0] (RW)
screamer 0:c5e2f793b59a 833 *
screamer 0:c5e2f793b59a 834 * Only the lower M bits are implemented in this MCU.
screamer 0:c5e2f793b59a 835 *
screamer 0:c5e2f793b59a 836 * Values:
screamer 0:c5e2f793b59a 837 * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
screamer 0:c5e2f793b59a 838 * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
screamer 0:c5e2f793b59a 839 * ADCn block can be triggered for a conversion by one pre-trigger from PDB
screamer 0:c5e2f793b59a 840 * channel n. When one conversion, which is triggered by one of the pre-triggers
screamer 0:c5e2f793b59a 841 * from PDB channel n, is in progress, new trigger from PDB channel's
screamer 0:c5e2f793b59a 842 * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
screamer 0:c5e2f793b59a 843 * Writing 0's to clear the sequence error flags.
screamer 0:c5e2f793b59a 844 */
screamer 0:c5e2f793b59a 845 /*@{*/
screamer 0:c5e2f793b59a 846 #define BP_PDB_CHnS_ERR (0U) /*!< Bit position for PDB_CHnS_ERR. */
screamer 0:c5e2f793b59a 847 #define BM_PDB_CHnS_ERR (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */
screamer 0:c5e2f793b59a 848 #define BS_PDB_CHnS_ERR (8U) /*!< Bit field size in bits for PDB_CHnS_ERR. */
screamer 0:c5e2f793b59a 849
screamer 0:c5e2f793b59a 850 /*! @brief Read current value of the PDB_CHnS_ERR field. */
Alessandro Angelino 5:41cb6fa198f3 851 #define BR_PDB_CHnS_ERR(x, n) (UNION_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), U, B.ERR))
screamer 0:c5e2f793b59a 852
screamer 0:c5e2f793b59a 853 /*! @brief Format value for bitfield PDB_CHnS_ERR. */
screamer 0:c5e2f793b59a 854 #define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
screamer 0:c5e2f793b59a 855
screamer 0:c5e2f793b59a 856 /*! @brief Set the ERR field to a new value. */
screamer 0:c5e2f793b59a 857 #define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
screamer 0:c5e2f793b59a 858 /*@}*/
screamer 0:c5e2f793b59a 859
screamer 0:c5e2f793b59a 860 /*!
screamer 0:c5e2f793b59a 861 * @name Register PDB_CHnS, field CF[23:16] (RW)
screamer 0:c5e2f793b59a 862 *
screamer 0:c5e2f793b59a 863 * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
screamer 0:c5e2f793b59a 864 * clear these bits.
screamer 0:c5e2f793b59a 865 */
screamer 0:c5e2f793b59a 866 /*@{*/
screamer 0:c5e2f793b59a 867 #define BP_PDB_CHnS_CF (16U) /*!< Bit position for PDB_CHnS_CF. */
screamer 0:c5e2f793b59a 868 #define BM_PDB_CHnS_CF (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */
screamer 0:c5e2f793b59a 869 #define BS_PDB_CHnS_CF (8U) /*!< Bit field size in bits for PDB_CHnS_CF. */
screamer 0:c5e2f793b59a 870
screamer 0:c5e2f793b59a 871 /*! @brief Read current value of the PDB_CHnS_CF field. */
Alessandro Angelino 5:41cb6fa198f3 872 #define BR_PDB_CHnS_CF(x, n) (UNION_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), U, B.CF))
screamer 0:c5e2f793b59a 873
screamer 0:c5e2f793b59a 874 /*! @brief Format value for bitfield PDB_CHnS_CF. */
screamer 0:c5e2f793b59a 875 #define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
screamer 0:c5e2f793b59a 876
screamer 0:c5e2f793b59a 877 /*! @brief Set the CF field to a new value. */
screamer 0:c5e2f793b59a 878 #define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
screamer 0:c5e2f793b59a 879 /*@}*/
screamer 0:c5e2f793b59a 880 /*******************************************************************************
screamer 0:c5e2f793b59a 881 * HW_PDB_CHnDLY0 - Channel n Delay 0 register
screamer 0:c5e2f793b59a 882 ******************************************************************************/
screamer 0:c5e2f793b59a 883
screamer 0:c5e2f793b59a 884 /*!
screamer 0:c5e2f793b59a 885 * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
screamer 0:c5e2f793b59a 886 *
screamer 0:c5e2f793b59a 887 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 888 */
screamer 0:c5e2f793b59a 889 typedef union _hw_pdb_chndly0
screamer 0:c5e2f793b59a 890 {
screamer 0:c5e2f793b59a 891 uint32_t U;
screamer 0:c5e2f793b59a 892 struct _hw_pdb_chndly0_bitfields
screamer 0:c5e2f793b59a 893 {
screamer 0:c5e2f793b59a 894 uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */
screamer 0:c5e2f793b59a 895 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 896 } B;
screamer 0:c5e2f793b59a 897 } hw_pdb_chndly0_t;
screamer 0:c5e2f793b59a 898
screamer 0:c5e2f793b59a 899 /*!
screamer 0:c5e2f793b59a 900 * @name Constants and macros for entire PDB_CHnDLY0 register
screamer 0:c5e2f793b59a 901 */
screamer 0:c5e2f793b59a 902 /*@{*/
screamer 0:c5e2f793b59a 903 #define HW_PDB_CHnDLY0_COUNT (2U)
screamer 0:c5e2f793b59a 904
screamer 0:c5e2f793b59a 905 #define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
screamer 0:c5e2f793b59a 906
screamer 0:c5e2f793b59a 907 #define HW_PDB_CHnDLY0(x, n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 908 #define HW_PDB_CHnDLY0_RD(x, n) (ADDRESS_READ(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 909 #define HW_PDB_CHnDLY0_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n), v))
screamer 0:c5e2f793b59a 910 #define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 911 #define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 912 #define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 913 /*@}*/
screamer 0:c5e2f793b59a 914
screamer 0:c5e2f793b59a 915 /*
screamer 0:c5e2f793b59a 916 * Constants & macros for individual PDB_CHnDLY0 bitfields
screamer 0:c5e2f793b59a 917 */
screamer 0:c5e2f793b59a 918
screamer 0:c5e2f793b59a 919 /*!
screamer 0:c5e2f793b59a 920 * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
screamer 0:c5e2f793b59a 921 *
screamer 0:c5e2f793b59a 922 * Specifies the delay value for the channel's corresponding pre-trigger. The
screamer 0:c5e2f793b59a 923 * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
screamer 0:c5e2f793b59a 924 * the value of internal register that is effective for the current PDB cycle.
screamer 0:c5e2f793b59a 925 */
screamer 0:c5e2f793b59a 926 /*@{*/
screamer 0:c5e2f793b59a 927 #define BP_PDB_CHnDLY0_DLY (0U) /*!< Bit position for PDB_CHnDLY0_DLY. */
screamer 0:c5e2f793b59a 928 #define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */
screamer 0:c5e2f793b59a 929 #define BS_PDB_CHnDLY0_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */
screamer 0:c5e2f793b59a 930
screamer 0:c5e2f793b59a 931 /*! @brief Read current value of the PDB_CHnDLY0_DLY field. */
Alessandro Angelino 5:41cb6fa198f3 932 #define BR_PDB_CHnDLY0_DLY(x, n) (UNION_READ(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n), U, B.DLY))
screamer 0:c5e2f793b59a 933
screamer 0:c5e2f793b59a 934 /*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */
screamer 0:c5e2f793b59a 935 #define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
screamer 0:c5e2f793b59a 936
screamer 0:c5e2f793b59a 937 /*! @brief Set the DLY field to a new value. */
screamer 0:c5e2f793b59a 938 #define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
screamer 0:c5e2f793b59a 939 /*@}*/
screamer 0:c5e2f793b59a 940 /*******************************************************************************
screamer 0:c5e2f793b59a 941 * HW_PDB_CHnDLY1 - Channel n Delay 1 register
screamer 0:c5e2f793b59a 942 ******************************************************************************/
screamer 0:c5e2f793b59a 943
screamer 0:c5e2f793b59a 944 /*!
screamer 0:c5e2f793b59a 945 * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
screamer 0:c5e2f793b59a 946 *
screamer 0:c5e2f793b59a 947 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 948 */
screamer 0:c5e2f793b59a 949 typedef union _hw_pdb_chndly1
screamer 0:c5e2f793b59a 950 {
screamer 0:c5e2f793b59a 951 uint32_t U;
screamer 0:c5e2f793b59a 952 struct _hw_pdb_chndly1_bitfields
screamer 0:c5e2f793b59a 953 {
screamer 0:c5e2f793b59a 954 uint32_t DLY : 16; /*!< [15:0] PDB Channel Delay */
screamer 0:c5e2f793b59a 955 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 956 } B;
screamer 0:c5e2f793b59a 957 } hw_pdb_chndly1_t;
screamer 0:c5e2f793b59a 958
screamer 0:c5e2f793b59a 959 /*!
screamer 0:c5e2f793b59a 960 * @name Constants and macros for entire PDB_CHnDLY1 register
screamer 0:c5e2f793b59a 961 */
screamer 0:c5e2f793b59a 962 /*@{*/
screamer 0:c5e2f793b59a 963 #define HW_PDB_CHnDLY1_COUNT (2U)
screamer 0:c5e2f793b59a 964
screamer 0:c5e2f793b59a 965 #define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
screamer 0:c5e2f793b59a 966
screamer 0:c5e2f793b59a 967 #define HW_PDB_CHnDLY1(x, n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 968 #define HW_PDB_CHnDLY1_RD(x, n) (ADDRESS_READ(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 969 #define HW_PDB_CHnDLY1_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n), v))
screamer 0:c5e2f793b59a 970 #define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 971 #define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 972 #define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 973 /*@}*/
screamer 0:c5e2f793b59a 974
screamer 0:c5e2f793b59a 975 /*
screamer 0:c5e2f793b59a 976 * Constants & macros for individual PDB_CHnDLY1 bitfields
screamer 0:c5e2f793b59a 977 */
screamer 0:c5e2f793b59a 978
screamer 0:c5e2f793b59a 979 /*!
screamer 0:c5e2f793b59a 980 * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
screamer 0:c5e2f793b59a 981 *
screamer 0:c5e2f793b59a 982 * These bits specify the delay value for the channel's corresponding
screamer 0:c5e2f793b59a 983 * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
screamer 0:c5e2f793b59a 984 * bits returns the value of internal register that is effective for the current PDB
screamer 0:c5e2f793b59a 985 * cycle.
screamer 0:c5e2f793b59a 986 */
screamer 0:c5e2f793b59a 987 /*@{*/
screamer 0:c5e2f793b59a 988 #define BP_PDB_CHnDLY1_DLY (0U) /*!< Bit position for PDB_CHnDLY1_DLY. */
screamer 0:c5e2f793b59a 989 #define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */
screamer 0:c5e2f793b59a 990 #define BS_PDB_CHnDLY1_DLY (16U) /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */
screamer 0:c5e2f793b59a 991
screamer 0:c5e2f793b59a 992 /*! @brief Read current value of the PDB_CHnDLY1_DLY field. */
Alessandro Angelino 5:41cb6fa198f3 993 #define BR_PDB_CHnDLY1_DLY(x, n) (UNION_READ(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n), U, B.DLY))
screamer 0:c5e2f793b59a 994
screamer 0:c5e2f793b59a 995 /*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */
screamer 0:c5e2f793b59a 996 #define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
screamer 0:c5e2f793b59a 997
screamer 0:c5e2f793b59a 998 /*! @brief Set the DLY field to a new value. */
screamer 0:c5e2f793b59a 999 #define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
screamer 0:c5e2f793b59a 1000 /*@}*/
screamer 0:c5e2f793b59a 1001
screamer 0:c5e2f793b59a 1002 /*******************************************************************************
screamer 0:c5e2f793b59a 1003 * HW_PDB_DACINTCn - DAC Interval Trigger n Control register
screamer 0:c5e2f793b59a 1004 ******************************************************************************/
screamer 0:c5e2f793b59a 1005
screamer 0:c5e2f793b59a 1006 /*!
screamer 0:c5e2f793b59a 1007 * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
screamer 0:c5e2f793b59a 1008 *
screamer 0:c5e2f793b59a 1009 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1010 */
screamer 0:c5e2f793b59a 1011 typedef union _hw_pdb_dacintcn
screamer 0:c5e2f793b59a 1012 {
screamer 0:c5e2f793b59a 1013 uint32_t U;
screamer 0:c5e2f793b59a 1014 struct _hw_pdb_dacintcn_bitfields
screamer 0:c5e2f793b59a 1015 {
screamer 0:c5e2f793b59a 1016 uint32_t TOE : 1; /*!< [0] DAC Interval Trigger Enable */
screamer 0:c5e2f793b59a 1017 uint32_t EXT : 1; /*!< [1] DAC External Trigger Input Enable */
screamer 0:c5e2f793b59a 1018 uint32_t RESERVED0 : 30; /*!< [31:2] */
screamer 0:c5e2f793b59a 1019 } B;
screamer 0:c5e2f793b59a 1020 } hw_pdb_dacintcn_t;
screamer 0:c5e2f793b59a 1021
screamer 0:c5e2f793b59a 1022 /*!
screamer 0:c5e2f793b59a 1023 * @name Constants and macros for entire PDB_DACINTCn register
screamer 0:c5e2f793b59a 1024 */
screamer 0:c5e2f793b59a 1025 /*@{*/
screamer 0:c5e2f793b59a 1026 #define HW_PDB_DACINTCn_COUNT (2U)
screamer 0:c5e2f793b59a 1027
screamer 0:c5e2f793b59a 1028 #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
screamer 0:c5e2f793b59a 1029
screamer 0:c5e2f793b59a 1030 #define HW_PDB_DACINTCn(x, n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 1031 #define HW_PDB_DACINTCn_RD(x, n) (ADDRESS_READ(hw_pdb_dacintcn_t, HW_PDB_DACINTCn_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 1032 #define HW_PDB_DACINTCn_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_dacintcn_t, HW_PDB_DACINTCn_ADDR(x, n), v))
screamer 0:c5e2f793b59a 1033 #define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 1034 #define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 1035 #define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 1036 /*@}*/
screamer 0:c5e2f793b59a 1037
screamer 0:c5e2f793b59a 1038 /*
screamer 0:c5e2f793b59a 1039 * Constants & macros for individual PDB_DACINTCn bitfields
screamer 0:c5e2f793b59a 1040 */
screamer 0:c5e2f793b59a 1041
screamer 0:c5e2f793b59a 1042 /*!
screamer 0:c5e2f793b59a 1043 * @name Register PDB_DACINTCn, field TOE[0] (RW)
screamer 0:c5e2f793b59a 1044 *
screamer 0:c5e2f793b59a 1045 * This bit enables the DAC interval trigger.
screamer 0:c5e2f793b59a 1046 *
screamer 0:c5e2f793b59a 1047 * Values:
screamer 0:c5e2f793b59a 1048 * - 0 - DAC interval trigger disabled.
screamer 0:c5e2f793b59a 1049 * - 1 - DAC interval trigger enabled.
screamer 0:c5e2f793b59a 1050 */
screamer 0:c5e2f793b59a 1051 /*@{*/
screamer 0:c5e2f793b59a 1052 #define BP_PDB_DACINTCn_TOE (0U) /*!< Bit position for PDB_DACINTCn_TOE. */
screamer 0:c5e2f793b59a 1053 #define BM_PDB_DACINTCn_TOE (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */
screamer 0:c5e2f793b59a 1054 #define BS_PDB_DACINTCn_TOE (1U) /*!< Bit field size in bits for PDB_DACINTCn_TOE. */
screamer 0:c5e2f793b59a 1055
screamer 0:c5e2f793b59a 1056 /*! @brief Read current value of the PDB_DACINTCn_TOE field. */
Alessandro Angelino 5:41cb6fa198f3 1057 #define BR_PDB_DACINTCn_TOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE)))
screamer 0:c5e2f793b59a 1058
screamer 0:c5e2f793b59a 1059 /*! @brief Format value for bitfield PDB_DACINTCn_TOE. */
screamer 0:c5e2f793b59a 1060 #define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
screamer 0:c5e2f793b59a 1061
screamer 0:c5e2f793b59a 1062 /*! @brief Set the TOE field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 1063 #define BW_PDB_DACINTCn_TOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE), v))
screamer 0:c5e2f793b59a 1064 /*@}*/
screamer 0:c5e2f793b59a 1065
screamer 0:c5e2f793b59a 1066 /*!
screamer 0:c5e2f793b59a 1067 * @name Register PDB_DACINTCn, field EXT[1] (RW)
screamer 0:c5e2f793b59a 1068 *
screamer 0:c5e2f793b59a 1069 * Enables the external trigger for DAC interval counter.
screamer 0:c5e2f793b59a 1070 *
screamer 0:c5e2f793b59a 1071 * Values:
screamer 0:c5e2f793b59a 1072 * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
screamer 0:c5e2f793b59a 1073 * counting starts when a rising edge is detected on selected trigger input
screamer 0:c5e2f793b59a 1074 * source or software trigger is selected and SWTRIG is written with 1.
screamer 0:c5e2f793b59a 1075 * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
screamer 0:c5e2f793b59a 1076 * and DAC external trigger input triggers the DAC interval trigger.
screamer 0:c5e2f793b59a 1077 */
screamer 0:c5e2f793b59a 1078 /*@{*/
screamer 0:c5e2f793b59a 1079 #define BP_PDB_DACINTCn_EXT (1U) /*!< Bit position for PDB_DACINTCn_EXT. */
screamer 0:c5e2f793b59a 1080 #define BM_PDB_DACINTCn_EXT (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */
screamer 0:c5e2f793b59a 1081 #define BS_PDB_DACINTCn_EXT (1U) /*!< Bit field size in bits for PDB_DACINTCn_EXT. */
screamer 0:c5e2f793b59a 1082
screamer 0:c5e2f793b59a 1083 /*! @brief Read current value of the PDB_DACINTCn_EXT field. */
Alessandro Angelino 5:41cb6fa198f3 1084 #define BR_PDB_DACINTCn_EXT(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT)))
screamer 0:c5e2f793b59a 1085
screamer 0:c5e2f793b59a 1086 /*! @brief Format value for bitfield PDB_DACINTCn_EXT. */
screamer 0:c5e2f793b59a 1087 #define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
screamer 0:c5e2f793b59a 1088
screamer 0:c5e2f793b59a 1089 /*! @brief Set the EXT field to a new value. */
Alessandro Angelino 5:41cb6fa198f3 1090 #define BW_PDB_DACINTCn_EXT(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT), v))
screamer 0:c5e2f793b59a 1091 /*@}*/
screamer 0:c5e2f793b59a 1092 /*******************************************************************************
screamer 0:c5e2f793b59a 1093 * HW_PDB_DACINTn - DAC Interval n register
screamer 0:c5e2f793b59a 1094 ******************************************************************************/
screamer 0:c5e2f793b59a 1095
screamer 0:c5e2f793b59a 1096 /*!
screamer 0:c5e2f793b59a 1097 * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
screamer 0:c5e2f793b59a 1098 *
screamer 0:c5e2f793b59a 1099 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1100 */
screamer 0:c5e2f793b59a 1101 typedef union _hw_pdb_dacintn
screamer 0:c5e2f793b59a 1102 {
screamer 0:c5e2f793b59a 1103 uint32_t U;
screamer 0:c5e2f793b59a 1104 struct _hw_pdb_dacintn_bitfields
screamer 0:c5e2f793b59a 1105 {
screamer 0:c5e2f793b59a 1106 uint32_t INT : 16; /*!< [15:0] DAC Interval */
screamer 0:c5e2f793b59a 1107 uint32_t RESERVED0 : 16; /*!< [31:16] */
screamer 0:c5e2f793b59a 1108 } B;
screamer 0:c5e2f793b59a 1109 } hw_pdb_dacintn_t;
screamer 0:c5e2f793b59a 1110
screamer 0:c5e2f793b59a 1111 /*!
screamer 0:c5e2f793b59a 1112 * @name Constants and macros for entire PDB_DACINTn register
screamer 0:c5e2f793b59a 1113 */
screamer 0:c5e2f793b59a 1114 /*@{*/
screamer 0:c5e2f793b59a 1115 #define HW_PDB_DACINTn_COUNT (2U)
screamer 0:c5e2f793b59a 1116
screamer 0:c5e2f793b59a 1117 #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
screamer 0:c5e2f793b59a 1118
screamer 0:c5e2f793b59a 1119 #define HW_PDB_DACINTn(x, n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 1120 #define HW_PDB_DACINTn_RD(x, n) (ADDRESS_READ(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 1121 #define HW_PDB_DACINTn_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n), v))
screamer 0:c5e2f793b59a 1122 #define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 1123 #define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 1124 #define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 1125 /*@}*/
screamer 0:c5e2f793b59a 1126
screamer 0:c5e2f793b59a 1127 /*
screamer 0:c5e2f793b59a 1128 * Constants & macros for individual PDB_DACINTn bitfields
screamer 0:c5e2f793b59a 1129 */
screamer 0:c5e2f793b59a 1130
screamer 0:c5e2f793b59a 1131 /*!
screamer 0:c5e2f793b59a 1132 * @name Register PDB_DACINTn, field INT[15:0] (RW)
screamer 0:c5e2f793b59a 1133 *
screamer 0:c5e2f793b59a 1134 * Specifies the interval value for DAC interval trigger. DAC interval trigger
screamer 0:c5e2f793b59a 1135 * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
screamer 0:c5e2f793b59a 1136 * Reading this field returns the value of internal register that is effective
screamer 0:c5e2f793b59a 1137 * for the current PDB cycle.
screamer 0:c5e2f793b59a 1138 */
screamer 0:c5e2f793b59a 1139 /*@{*/
screamer 0:c5e2f793b59a 1140 #define BP_PDB_DACINTn_INT (0U) /*!< Bit position for PDB_DACINTn_INT. */
screamer 0:c5e2f793b59a 1141 #define BM_PDB_DACINTn_INT (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */
screamer 0:c5e2f793b59a 1142 #define BS_PDB_DACINTn_INT (16U) /*!< Bit field size in bits for PDB_DACINTn_INT. */
screamer 0:c5e2f793b59a 1143
screamer 0:c5e2f793b59a 1144 /*! @brief Read current value of the PDB_DACINTn_INT field. */
Alessandro Angelino 5:41cb6fa198f3 1145 #define BR_PDB_DACINTn_INT(x, n) (UNION_READ(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n), U, B.INT))
screamer 0:c5e2f793b59a 1146
screamer 0:c5e2f793b59a 1147 /*! @brief Format value for bitfield PDB_DACINTn_INT. */
screamer 0:c5e2f793b59a 1148 #define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
screamer 0:c5e2f793b59a 1149
screamer 0:c5e2f793b59a 1150 /*! @brief Set the INT field to a new value. */
screamer 0:c5e2f793b59a 1151 #define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
screamer 0:c5e2f793b59a 1152 /*@}*/
screamer 0:c5e2f793b59a 1153
screamer 0:c5e2f793b59a 1154 /*******************************************************************************
screamer 0:c5e2f793b59a 1155 * HW_PDB_POEN - Pulse-Out n Enable register
screamer 0:c5e2f793b59a 1156 ******************************************************************************/
screamer 0:c5e2f793b59a 1157
screamer 0:c5e2f793b59a 1158 /*!
screamer 0:c5e2f793b59a 1159 * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
screamer 0:c5e2f793b59a 1160 *
screamer 0:c5e2f793b59a 1161 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1162 */
screamer 0:c5e2f793b59a 1163 typedef union _hw_pdb_poen
screamer 0:c5e2f793b59a 1164 {
screamer 0:c5e2f793b59a 1165 uint32_t U;
screamer 0:c5e2f793b59a 1166 struct _hw_pdb_poen_bitfields
screamer 0:c5e2f793b59a 1167 {
screamer 0:c5e2f793b59a 1168 uint32_t POEN : 8; /*!< [7:0] PDB Pulse-Out Enable */
screamer 0:c5e2f793b59a 1169 uint32_t RESERVED0 : 24; /*!< [31:8] */
screamer 0:c5e2f793b59a 1170 } B;
screamer 0:c5e2f793b59a 1171 } hw_pdb_poen_t;
screamer 0:c5e2f793b59a 1172
screamer 0:c5e2f793b59a 1173 /*!
screamer 0:c5e2f793b59a 1174 * @name Constants and macros for entire PDB_POEN register
screamer 0:c5e2f793b59a 1175 */
screamer 0:c5e2f793b59a 1176 /*@{*/
screamer 0:c5e2f793b59a 1177 #define HW_PDB_POEN_ADDR(x) ((x) + 0x190U)
screamer 0:c5e2f793b59a 1178
screamer 0:c5e2f793b59a 1179 #define HW_PDB_POEN(x) (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 1180 #define HW_PDB_POEN_RD(x) (ADDRESS_READ(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 1181 #define HW_PDB_POEN_WR(x, v) (ADDRESS_WRITE(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x), v))
screamer 0:c5e2f793b59a 1182 #define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) | (v)))
screamer 0:c5e2f793b59a 1183 #define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 1184 #define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 1185 /*@}*/
screamer 0:c5e2f793b59a 1186
screamer 0:c5e2f793b59a 1187 /*
screamer 0:c5e2f793b59a 1188 * Constants & macros for individual PDB_POEN bitfields
screamer 0:c5e2f793b59a 1189 */
screamer 0:c5e2f793b59a 1190
screamer 0:c5e2f793b59a 1191 /*!
screamer 0:c5e2f793b59a 1192 * @name Register PDB_POEN, field POEN[7:0] (RW)
screamer 0:c5e2f793b59a 1193 *
screamer 0:c5e2f793b59a 1194 * Enables the pulse output. Only lower Y bits are implemented in this MCU.
screamer 0:c5e2f793b59a 1195 *
screamer 0:c5e2f793b59a 1196 * Values:
screamer 0:c5e2f793b59a 1197 * - 0 - PDB Pulse-Out disabled
screamer 0:c5e2f793b59a 1198 * - 1 - PDB Pulse-Out enabled
screamer 0:c5e2f793b59a 1199 */
screamer 0:c5e2f793b59a 1200 /*@{*/
screamer 0:c5e2f793b59a 1201 #define BP_PDB_POEN_POEN (0U) /*!< Bit position for PDB_POEN_POEN. */
screamer 0:c5e2f793b59a 1202 #define BM_PDB_POEN_POEN (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */
screamer 0:c5e2f793b59a 1203 #define BS_PDB_POEN_POEN (8U) /*!< Bit field size in bits for PDB_POEN_POEN. */
screamer 0:c5e2f793b59a 1204
screamer 0:c5e2f793b59a 1205 /*! @brief Read current value of the PDB_POEN_POEN field. */
Alessandro Angelino 5:41cb6fa198f3 1206 #define BR_PDB_POEN_POEN(x) (UNION_READ(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x), U, B.POEN))
screamer 0:c5e2f793b59a 1207
screamer 0:c5e2f793b59a 1208 /*! @brief Format value for bitfield PDB_POEN_POEN. */
screamer 0:c5e2f793b59a 1209 #define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
screamer 0:c5e2f793b59a 1210
screamer 0:c5e2f793b59a 1211 /*! @brief Set the POEN field to a new value. */
screamer 0:c5e2f793b59a 1212 #define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
screamer 0:c5e2f793b59a 1213 /*@}*/
screamer 0:c5e2f793b59a 1214
screamer 0:c5e2f793b59a 1215 /*******************************************************************************
screamer 0:c5e2f793b59a 1216 * HW_PDB_POnDLY - Pulse-Out n Delay register
screamer 0:c5e2f793b59a 1217 ******************************************************************************/
screamer 0:c5e2f793b59a 1218
screamer 0:c5e2f793b59a 1219 /*!
screamer 0:c5e2f793b59a 1220 * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
screamer 0:c5e2f793b59a 1221 *
screamer 0:c5e2f793b59a 1222 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 1223 */
screamer 0:c5e2f793b59a 1224 typedef union _hw_pdb_pondly
screamer 0:c5e2f793b59a 1225 {
screamer 0:c5e2f793b59a 1226 uint32_t U;
screamer 0:c5e2f793b59a 1227 struct _hw_pdb_pondly_bitfields
screamer 0:c5e2f793b59a 1228 {
screamer 0:c5e2f793b59a 1229 uint32_t DLY2 : 16; /*!< [15:0] PDB Pulse-Out Delay 2 */
screamer 0:c5e2f793b59a 1230 uint32_t DLY1 : 16; /*!< [31:16] PDB Pulse-Out Delay 1 */
screamer 0:c5e2f793b59a 1231 } B;
screamer 0:c5e2f793b59a 1232 } hw_pdb_pondly_t;
screamer 0:c5e2f793b59a 1233
screamer 0:c5e2f793b59a 1234 /*!
screamer 0:c5e2f793b59a 1235 * @name Constants and macros for entire PDB_POnDLY register
screamer 0:c5e2f793b59a 1236 */
screamer 0:c5e2f793b59a 1237 /*@{*/
screamer 0:c5e2f793b59a 1238 #define HW_PDB_POnDLY_COUNT (3U)
screamer 0:c5e2f793b59a 1239
screamer 0:c5e2f793b59a 1240 #define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
screamer 0:c5e2f793b59a 1241
screamer 0:c5e2f793b59a 1242 #define HW_PDB_POnDLY(x, n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n))
Alessandro Angelino 5:41cb6fa198f3 1243 #define HW_PDB_POnDLY_RD(x, n) (ADDRESS_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n)))
Alessandro Angelino 5:41cb6fa198f3 1244 #define HW_PDB_POnDLY_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), v))
screamer 0:c5e2f793b59a 1245 #define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) | (v)))
screamer 0:c5e2f793b59a 1246 #define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
screamer 0:c5e2f793b59a 1247 #define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v)))
screamer 0:c5e2f793b59a 1248 /*@}*/
screamer 0:c5e2f793b59a 1249
screamer 0:c5e2f793b59a 1250 /*
screamer 0:c5e2f793b59a 1251 * Constants & macros for individual PDB_POnDLY bitfields
screamer 0:c5e2f793b59a 1252 */
screamer 0:c5e2f793b59a 1253
screamer 0:c5e2f793b59a 1254 /*!
screamer 0:c5e2f793b59a 1255 * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
screamer 0:c5e2f793b59a 1256 *
screamer 0:c5e2f793b59a 1257 * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
screamer 0:c5e2f793b59a 1258 * low when the PDB counter is equal to the DLY2. Reading these bits returns the
screamer 0:c5e2f793b59a 1259 * value of internal register that is effective for the current PDB cycle.
screamer 0:c5e2f793b59a 1260 */
screamer 0:c5e2f793b59a 1261 /*@{*/
screamer 0:c5e2f793b59a 1262 #define BP_PDB_POnDLY_DLY2 (0U) /*!< Bit position for PDB_POnDLY_DLY2. */
screamer 0:c5e2f793b59a 1263 #define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */
screamer 0:c5e2f793b59a 1264 #define BS_PDB_POnDLY_DLY2 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY2. */
screamer 0:c5e2f793b59a 1265
screamer 0:c5e2f793b59a 1266 /*! @brief Read current value of the PDB_POnDLY_DLY2 field. */
Alessandro Angelino 5:41cb6fa198f3 1267 #define BR_PDB_POnDLY_DLY2(x, n) (UNION_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), U, B.DLY2))
screamer 0:c5e2f793b59a 1268
screamer 0:c5e2f793b59a 1269 /*! @brief Format value for bitfield PDB_POnDLY_DLY2. */
screamer 0:c5e2f793b59a 1270 #define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
screamer 0:c5e2f793b59a 1271
screamer 0:c5e2f793b59a 1272 /*! @brief Set the DLY2 field to a new value. */
screamer 0:c5e2f793b59a 1273 #define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
screamer 0:c5e2f793b59a 1274 /*@}*/
screamer 0:c5e2f793b59a 1275
screamer 0:c5e2f793b59a 1276 /*!
screamer 0:c5e2f793b59a 1277 * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
screamer 0:c5e2f793b59a 1278 *
screamer 0:c5e2f793b59a 1279 * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
screamer 0:c5e2f793b59a 1280 * high when the PDB counter is equal to the DLY1. Reading these bits returns the
screamer 0:c5e2f793b59a 1281 * value of internal register that is effective for the current PDB cycle.
screamer 0:c5e2f793b59a 1282 */
screamer 0:c5e2f793b59a 1283 /*@{*/
screamer 0:c5e2f793b59a 1284 #define BP_PDB_POnDLY_DLY1 (16U) /*!< Bit position for PDB_POnDLY_DLY1. */
screamer 0:c5e2f793b59a 1285 #define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */
screamer 0:c5e2f793b59a 1286 #define BS_PDB_POnDLY_DLY1 (16U) /*!< Bit field size in bits for PDB_POnDLY_DLY1. */
screamer 0:c5e2f793b59a 1287
screamer 0:c5e2f793b59a 1288 /*! @brief Read current value of the PDB_POnDLY_DLY1 field. */
Alessandro Angelino 5:41cb6fa198f3 1289 #define BR_PDB_POnDLY_DLY1(x, n) (UNION_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), U, B.DLY1))
screamer 0:c5e2f793b59a 1290
screamer 0:c5e2f793b59a 1291 /*! @brief Format value for bitfield PDB_POnDLY_DLY1. */
screamer 0:c5e2f793b59a 1292 #define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
screamer 0:c5e2f793b59a 1293
screamer 0:c5e2f793b59a 1294 /*! @brief Set the DLY1 field to a new value. */
screamer 0:c5e2f793b59a 1295 #define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
screamer 0:c5e2f793b59a 1296 /*@}*/
screamer 0:c5e2f793b59a 1297
screamer 0:c5e2f793b59a 1298 /*******************************************************************************
screamer 0:c5e2f793b59a 1299 * hw_pdb_t - module struct
screamer 0:c5e2f793b59a 1300 ******************************************************************************/
screamer 0:c5e2f793b59a 1301 /*!
screamer 0:c5e2f793b59a 1302 * @brief All PDB module registers.
screamer 0:c5e2f793b59a 1303 */
screamer 0:c5e2f793b59a 1304 #pragma pack(1)
screamer 0:c5e2f793b59a 1305 typedef struct _hw_pdb
screamer 0:c5e2f793b59a 1306 {
screamer 0:c5e2f793b59a 1307 __IO hw_pdb_sc_t SC; /*!< [0x0] Status and Control register */
screamer 0:c5e2f793b59a 1308 __IO hw_pdb_mod_t MOD; /*!< [0x4] Modulus register */
screamer 0:c5e2f793b59a 1309 __I hw_pdb_cnt_t CNT; /*!< [0x8] Counter register */
screamer 0:c5e2f793b59a 1310 __IO hw_pdb_idly_t IDLY; /*!< [0xC] Interrupt Delay register */
screamer 0:c5e2f793b59a 1311 struct {
screamer 0:c5e2f793b59a 1312 __IO hw_pdb_chnc1_t CHnC1; /*!< [0x10] Channel n Control register 1 */
screamer 0:c5e2f793b59a 1313 __IO hw_pdb_chns_t CHnS; /*!< [0x14] Channel n Status register */
screamer 0:c5e2f793b59a 1314 __IO hw_pdb_chndly0_t CHnDLY0; /*!< [0x18] Channel n Delay 0 register */
screamer 0:c5e2f793b59a 1315 __IO hw_pdb_chndly1_t CHnDLY1; /*!< [0x1C] Channel n Delay 1 register */
screamer 0:c5e2f793b59a 1316 uint8_t _reserved0[24];
screamer 0:c5e2f793b59a 1317 } CH[2];
screamer 0:c5e2f793b59a 1318 uint8_t _reserved0[240];
screamer 0:c5e2f793b59a 1319 struct {
screamer 0:c5e2f793b59a 1320 __IO hw_pdb_dacintcn_t DACINTCn; /*!< [0x150] DAC Interval Trigger n Control register */
screamer 0:c5e2f793b59a 1321 __IO hw_pdb_dacintn_t DACINTn; /*!< [0x154] DAC Interval n register */
screamer 0:c5e2f793b59a 1322 } DAC[2];
screamer 0:c5e2f793b59a 1323 uint8_t _reserved1[48];
screamer 0:c5e2f793b59a 1324 __IO hw_pdb_poen_t POEN; /*!< [0x190] Pulse-Out n Enable register */
screamer 0:c5e2f793b59a 1325 __IO hw_pdb_pondly_t POnDLY[3]; /*!< [0x194] Pulse-Out n Delay register */
screamer 0:c5e2f793b59a 1326 } hw_pdb_t;
screamer 0:c5e2f793b59a 1327 #pragma pack()
screamer 0:c5e2f793b59a 1328
screamer 0:c5e2f793b59a 1329 /*! @brief Macro to access all PDB registers. */
screamer 0:c5e2f793b59a 1330 /*! @param x PDB module instance base address. */
screamer 0:c5e2f793b59a 1331 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 1332 * use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
screamer 0:c5e2f793b59a 1333 #define HW_PDB(x) (*(hw_pdb_t *)(x))
screamer 0:c5e2f793b59a 1334
screamer 0:c5e2f793b59a 1335 #endif /* __HW_PDB_REGISTERS_H__ */
screamer 0:c5e2f793b59a 1336 /* EOF */