Alessandro Angelino / target-mcu-k64f

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Fork of target-mcu-k64f by Morpheus

hal/device/device/MK64F12/MK64F12_gpio.h@5:41cb6fa198f3, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:09:12 2016 +0100
Revision:
5:41cb6fa198f3
Parent:
0:c5e2f793b59a 
Mirror huge PR from mbed OS



The following PRs have been mirrored:

https://github.com/ARMmbed/mbed-hal-k64f/pull/6  "All Freescale macros for memory access replaced"

https://github.com/ARMmbed/mbed-hal-k64f/pull/7  "Fix bug in union access macros"

https://github.com/ARMmbed/mbed-hal-k64f/pull/8  "Simpler and more universal macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/9  "Fixed bug in fallback macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/10 "Added volatile keyword to address for union read"

https://github.com/ARMmbed/mbed-hal-k64f/pull/14 "Removing copyright and revision from unmodified file"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Compilers: Keil ARM C/C++ Compiler
screamer 0:c5e2f793b59a 4 ** Freescale C/C++ for Embedded ARM
screamer 0:c5e2f793b59a 5 ** GNU C Compiler
screamer 0:c5e2f793b59a 6 ** IAR ANSI C/C++ Compiler for ARM
screamer 0:c5e2f793b59a 7 **
screamer 0:c5e2f793b59a 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
screamer 0:c5e2f793b59a 9 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 10 ** Build: b140604
screamer 0:c5e2f793b59a 11 **
screamer 0:c5e2f793b59a 12 ** Abstract:
screamer 0:c5e2f793b59a 13 ** Extension to the CMSIS register access layer header.
screamer 0:c5e2f793b59a 14 **
screamer 0:c5e2f793b59a 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 16 ** All rights reserved.
screamer 0:c5e2f793b59a 17 **
Alessandro Angelino 5:41cb6fa198f3 18 ** (C) COPYRIGHT 2015-2015 ARM Limited
Alessandro Angelino 5:41cb6fa198f3 19 ** ALL RIGHTS RESERVED
Alessandro Angelino 5:41cb6fa198f3 20 **
screamer 0:c5e2f793b59a 21 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 22 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 23 **
screamer 0:c5e2f793b59a 24 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 25 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 26 **
screamer 0:c5e2f793b59a 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 28 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 29 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 30 **
screamer 0:c5e2f793b59a 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 32 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 33 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 34 **
screamer 0:c5e2f793b59a 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 45 **
screamer 0:c5e2f793b59a 46 ** http: www.freescale.com
screamer 0:c5e2f793b59a 47 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 48 **
screamer 0:c5e2f793b59a 49 ** Revisions:
screamer 0:c5e2f793b59a 50 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 51 ** Initial version.
screamer 0:c5e2f793b59a 52 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 53 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 55 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 56 ** System initialization updated.
screamer 0:c5e2f793b59a 57 ** MCG - registers updated.
screamer 0:c5e2f793b59a 58 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 59 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 61 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 62 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 63 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 64 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 65 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 66 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 67 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 70 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 73 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Alessandro Angelino 5:41cb6fa198f3 74 ** - rev. 2.6 (2015-08-03) (ARM)
Alessandro Angelino 5:41cb6fa198f3 75 ** All accesses to memory are replaced by equivalent macros; this allows
Alessandro Angelino 5:41cb6fa198f3 76 ** memory read/write operations to be re-defined if needed (for example,
Alessandro Angelino 5:41cb6fa198f3 77 ** to implement new security features
screamer 0:c5e2f793b59a 78 **
screamer 0:c5e2f793b59a 79 ** ###################################################################
screamer 0:c5e2f793b59a 80 */
screamer 0:c5e2f793b59a 81
screamer 0:c5e2f793b59a 82 /*
screamer 0:c5e2f793b59a 83 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
screamer 0:c5e2f793b59a 84 *
screamer 0:c5e2f793b59a 85 * This file was generated automatically and any changes may be lost.
screamer 0:c5e2f793b59a 86 */
screamer 0:c5e2f793b59a 87 #ifndef __HW_GPIO_REGISTERS_H__
screamer 0:c5e2f793b59a 88 #define __HW_GPIO_REGISTERS_H__
screamer 0:c5e2f793b59a 89
screamer 0:c5e2f793b59a 90 #include "MK64F12.h"
screamer 0:c5e2f793b59a 91 #include "fsl_bitaccess.h"
screamer 0:c5e2f793b59a 92
screamer 0:c5e2f793b59a 93 /*
screamer 0:c5e2f793b59a 94 * MK64F12 GPIO
screamer 0:c5e2f793b59a 95 *
screamer 0:c5e2f793b59a 96 * General Purpose Input/Output
screamer 0:c5e2f793b59a 97 *
screamer 0:c5e2f793b59a 98 * Registers defined in this header file:
screamer 0:c5e2f793b59a 99 * - HW_GPIO_PDOR - Port Data Output Register
screamer 0:c5e2f793b59a 100 * - HW_GPIO_PSOR - Port Set Output Register
screamer 0:c5e2f793b59a 101 * - HW_GPIO_PCOR - Port Clear Output Register
screamer 0:c5e2f793b59a 102 * - HW_GPIO_PTOR - Port Toggle Output Register
screamer 0:c5e2f793b59a 103 * - HW_GPIO_PDIR - Port Data Input Register
screamer 0:c5e2f793b59a 104 * - HW_GPIO_PDDR - Port Data Direction Register
screamer 0:c5e2f793b59a 105 *
screamer 0:c5e2f793b59a 106 * - hw_gpio_t - Struct containing all module registers.
screamer 0:c5e2f793b59a 107 */
screamer 0:c5e2f793b59a 108
screamer 0:c5e2f793b59a 109 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
screamer 0:c5e2f793b59a 110 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
screamer 0:c5e2f793b59a 111 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
screamer 0:c5e2f793b59a 112 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
screamer 0:c5e2f793b59a 113 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
screamer 0:c5e2f793b59a 114 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
screamer 0:c5e2f793b59a 115
screamer 0:c5e2f793b59a 116 /*******************************************************************************
screamer 0:c5e2f793b59a 117 * HW_GPIO_PDOR - Port Data Output Register
screamer 0:c5e2f793b59a 118 ******************************************************************************/
screamer 0:c5e2f793b59a 119
screamer 0:c5e2f793b59a 120 /*!
screamer 0:c5e2f793b59a 121 * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
screamer 0:c5e2f793b59a 122 *
screamer 0:c5e2f793b59a 123 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 124 *
screamer 0:c5e2f793b59a 125 * This register configures the logic levels that are driven on each
screamer 0:c5e2f793b59a 126 * general-purpose output pins. Do not modify pin configuration registers associated with
screamer 0:c5e2f793b59a 127 * pins not available in your selected package. All unbonded pins not available in
screamer 0:c5e2f793b59a 128 * your package will default to DISABLE state for lowest power consumption.
screamer 0:c5e2f793b59a 129 */
screamer 0:c5e2f793b59a 130 typedef union _hw_gpio_pdor
screamer 0:c5e2f793b59a 131 {
screamer 0:c5e2f793b59a 132 uint32_t U;
screamer 0:c5e2f793b59a 133 struct _hw_gpio_pdor_bitfields
screamer 0:c5e2f793b59a 134 {
screamer 0:c5e2f793b59a 135 uint32_t PDO : 32; /*!< [31:0] Port Data Output */
screamer 0:c5e2f793b59a 136 } B;
screamer 0:c5e2f793b59a 137 } hw_gpio_pdor_t;
screamer 0:c5e2f793b59a 138
screamer 0:c5e2f793b59a 139 /*!
screamer 0:c5e2f793b59a 140 * @name Constants and macros for entire GPIO_PDOR register
screamer 0:c5e2f793b59a 141 */
screamer 0:c5e2f793b59a 142 /*@{*/
screamer 0:c5e2f793b59a 143 #define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U)
screamer 0:c5e2f793b59a 144
screamer 0:c5e2f793b59a 145 #define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 146 #define HW_GPIO_PDOR_RD(x) (ADDRESS_READ(hw_gpio_pdor_t, HW_GPIO_PDOR_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 147 #define HW_GPIO_PDOR_WR(x, v) (ADDRESS_WRITE(hw_gpio_pdor_t, HW_GPIO_PDOR_ADDR(x), v))
screamer 0:c5e2f793b59a 148 #define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
screamer 0:c5e2f793b59a 149 #define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 150 #define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 151 /*@}*/
screamer 0:c5e2f793b59a 152
screamer 0:c5e2f793b59a 153 /*
screamer 0:c5e2f793b59a 154 * Constants & macros for individual GPIO_PDOR bitfields
screamer 0:c5e2f793b59a 155 */
screamer 0:c5e2f793b59a 156
screamer 0:c5e2f793b59a 157 /*!
screamer 0:c5e2f793b59a 158 * @name Register GPIO_PDOR, field PDO[31:0] (RW)
screamer 0:c5e2f793b59a 159 *
screamer 0:c5e2f793b59a 160 * Register bits for unbonded pins return a undefined value when read.
screamer 0:c5e2f793b59a 161 *
screamer 0:c5e2f793b59a 162 * Values:
screamer 0:c5e2f793b59a 163 * - 0 - Logic level 0 is driven on pin, provided pin is configured for
screamer 0:c5e2f793b59a 164 * general-purpose output.
screamer 0:c5e2f793b59a 165 * - 1 - Logic level 1 is driven on pin, provided pin is configured for
screamer 0:c5e2f793b59a 166 * general-purpose output.
screamer 0:c5e2f793b59a 167 */
screamer 0:c5e2f793b59a 168 /*@{*/
screamer 0:c5e2f793b59a 169 #define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */
screamer 0:c5e2f793b59a 170 #define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
screamer 0:c5e2f793b59a 171 #define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */
screamer 0:c5e2f793b59a 172
screamer 0:c5e2f793b59a 173 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
screamer 0:c5e2f793b59a 174 #define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
screamer 0:c5e2f793b59a 175
screamer 0:c5e2f793b59a 176 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
screamer 0:c5e2f793b59a 177 #define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
screamer 0:c5e2f793b59a 178
screamer 0:c5e2f793b59a 179 /*! @brief Set the PDO field to a new value. */
screamer 0:c5e2f793b59a 180 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
screamer 0:c5e2f793b59a 181 /*@}*/
screamer 0:c5e2f793b59a 182
screamer 0:c5e2f793b59a 183 /*******************************************************************************
screamer 0:c5e2f793b59a 184 * HW_GPIO_PSOR - Port Set Output Register
screamer 0:c5e2f793b59a 185 ******************************************************************************/
screamer 0:c5e2f793b59a 186
screamer 0:c5e2f793b59a 187 /*!
screamer 0:c5e2f793b59a 188 * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
screamer 0:c5e2f793b59a 189 *
screamer 0:c5e2f793b59a 190 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 191 *
screamer 0:c5e2f793b59a 192 * This register configures whether to set the fields of the PDOR.
screamer 0:c5e2f793b59a 193 */
screamer 0:c5e2f793b59a 194 typedef union _hw_gpio_psor
screamer 0:c5e2f793b59a 195 {
screamer 0:c5e2f793b59a 196 uint32_t U;
screamer 0:c5e2f793b59a 197 struct _hw_gpio_psor_bitfields
screamer 0:c5e2f793b59a 198 {
screamer 0:c5e2f793b59a 199 uint32_t PTSO : 32; /*!< [31:0] Port Set Output */
screamer 0:c5e2f793b59a 200 } B;
screamer 0:c5e2f793b59a 201 } hw_gpio_psor_t;
screamer 0:c5e2f793b59a 202
screamer 0:c5e2f793b59a 203 /*!
screamer 0:c5e2f793b59a 204 * @name Constants and macros for entire GPIO_PSOR register
screamer 0:c5e2f793b59a 205 */
screamer 0:c5e2f793b59a 206 /*@{*/
screamer 0:c5e2f793b59a 207 #define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U)
screamer 0:c5e2f793b59a 208
screamer 0:c5e2f793b59a 209 #define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 210 #define HW_GPIO_PSOR_RD(x) (ADDRESS_READ(hw_gpio_psor_t, HW_GPIO_PSOR_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 211 #define HW_GPIO_PSOR_WR(x, v) (ADDRESS_WRITE(hw_gpio_psor_t, HW_GPIO_PSOR_ADDR(x), v))
screamer 0:c5e2f793b59a 212 /*@}*/
screamer 0:c5e2f793b59a 213
screamer 0:c5e2f793b59a 214 /*
screamer 0:c5e2f793b59a 215 * Constants & macros for individual GPIO_PSOR bitfields
screamer 0:c5e2f793b59a 216 */
screamer 0:c5e2f793b59a 217
screamer 0:c5e2f793b59a 218 /*!
screamer 0:c5e2f793b59a 219 * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
screamer 0:c5e2f793b59a 220 *
screamer 0:c5e2f793b59a 221 * Writing to this register will update the contents of the corresponding bit in
screamer 0:c5e2f793b59a 222 * the PDOR as follows:
screamer 0:c5e2f793b59a 223 *
screamer 0:c5e2f793b59a 224 * Values:
screamer 0:c5e2f793b59a 225 * - 0 - Corresponding bit in PDORn does not change.
screamer 0:c5e2f793b59a 226 * - 1 - Corresponding bit in PDORn is set to logic 1.
screamer 0:c5e2f793b59a 227 */
screamer 0:c5e2f793b59a 228 /*@{*/
screamer 0:c5e2f793b59a 229 #define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */
screamer 0:c5e2f793b59a 230 #define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
screamer 0:c5e2f793b59a 231 #define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
screamer 0:c5e2f793b59a 232
screamer 0:c5e2f793b59a 233 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
screamer 0:c5e2f793b59a 234 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
screamer 0:c5e2f793b59a 235
screamer 0:c5e2f793b59a 236 /*! @brief Set the PTSO field to a new value. */
screamer 0:c5e2f793b59a 237 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
screamer 0:c5e2f793b59a 238 /*@}*/
screamer 0:c5e2f793b59a 239
screamer 0:c5e2f793b59a 240 /*******************************************************************************
screamer 0:c5e2f793b59a 241 * HW_GPIO_PCOR - Port Clear Output Register
screamer 0:c5e2f793b59a 242 ******************************************************************************/
screamer 0:c5e2f793b59a 243
screamer 0:c5e2f793b59a 244 /*!
screamer 0:c5e2f793b59a 245 * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
screamer 0:c5e2f793b59a 246 *
screamer 0:c5e2f793b59a 247 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 248 *
screamer 0:c5e2f793b59a 249 * This register configures whether to clear the fields of PDOR.
screamer 0:c5e2f793b59a 250 */
screamer 0:c5e2f793b59a 251 typedef union _hw_gpio_pcor
screamer 0:c5e2f793b59a 252 {
screamer 0:c5e2f793b59a 253 uint32_t U;
screamer 0:c5e2f793b59a 254 struct _hw_gpio_pcor_bitfields
screamer 0:c5e2f793b59a 255 {
screamer 0:c5e2f793b59a 256 uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */
screamer 0:c5e2f793b59a 257 } B;
screamer 0:c5e2f793b59a 258 } hw_gpio_pcor_t;
screamer 0:c5e2f793b59a 259
screamer 0:c5e2f793b59a 260 /*!
screamer 0:c5e2f793b59a 261 * @name Constants and macros for entire GPIO_PCOR register
screamer 0:c5e2f793b59a 262 */
screamer 0:c5e2f793b59a 263 /*@{*/
screamer 0:c5e2f793b59a 264 #define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U)
screamer 0:c5e2f793b59a 265
screamer 0:c5e2f793b59a 266 #define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 267 #define HW_GPIO_PCOR_RD(x) (ADDRESS_READ(hw_gpio_pcor_t, HW_GPIO_PCOR_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 268 #define HW_GPIO_PCOR_WR(x, v) (ADDRESS_WRITE(hw_gpio_pcor_t, HW_GPIO_PCOR_ADDR(x), v))
screamer 0:c5e2f793b59a 269 /*@}*/
screamer 0:c5e2f793b59a 270
screamer 0:c5e2f793b59a 271 /*
screamer 0:c5e2f793b59a 272 * Constants & macros for individual GPIO_PCOR bitfields
screamer 0:c5e2f793b59a 273 */
screamer 0:c5e2f793b59a 274
screamer 0:c5e2f793b59a 275 /*!
screamer 0:c5e2f793b59a 276 * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
screamer 0:c5e2f793b59a 277 *
screamer 0:c5e2f793b59a 278 * Writing to this register will update the contents of the corresponding bit in
screamer 0:c5e2f793b59a 279 * the Port Data Output Register (PDOR) as follows:
screamer 0:c5e2f793b59a 280 *
screamer 0:c5e2f793b59a 281 * Values:
screamer 0:c5e2f793b59a 282 * - 0 - Corresponding bit in PDORn does not change.
screamer 0:c5e2f793b59a 283 * - 1 - Corresponding bit in PDORn is cleared to logic 0.
screamer 0:c5e2f793b59a 284 */
screamer 0:c5e2f793b59a 285 /*@{*/
screamer 0:c5e2f793b59a 286 #define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */
screamer 0:c5e2f793b59a 287 #define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
screamer 0:c5e2f793b59a 288 #define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
screamer 0:c5e2f793b59a 289
screamer 0:c5e2f793b59a 290 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
screamer 0:c5e2f793b59a 291 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
screamer 0:c5e2f793b59a 292
screamer 0:c5e2f793b59a 293 /*! @brief Set the PTCO field to a new value. */
screamer 0:c5e2f793b59a 294 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
screamer 0:c5e2f793b59a 295 /*@}*/
screamer 0:c5e2f793b59a 296
screamer 0:c5e2f793b59a 297 /*******************************************************************************
screamer 0:c5e2f793b59a 298 * HW_GPIO_PTOR - Port Toggle Output Register
screamer 0:c5e2f793b59a 299 ******************************************************************************/
screamer 0:c5e2f793b59a 300
screamer 0:c5e2f793b59a 301 /*!
screamer 0:c5e2f793b59a 302 * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
screamer 0:c5e2f793b59a 303 *
screamer 0:c5e2f793b59a 304 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 305 */
screamer 0:c5e2f793b59a 306 typedef union _hw_gpio_ptor
screamer 0:c5e2f793b59a 307 {
screamer 0:c5e2f793b59a 308 uint32_t U;
screamer 0:c5e2f793b59a 309 struct _hw_gpio_ptor_bitfields
screamer 0:c5e2f793b59a 310 {
screamer 0:c5e2f793b59a 311 uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */
screamer 0:c5e2f793b59a 312 } B;
screamer 0:c5e2f793b59a 313 } hw_gpio_ptor_t;
screamer 0:c5e2f793b59a 314
screamer 0:c5e2f793b59a 315 /*!
screamer 0:c5e2f793b59a 316 * @name Constants and macros for entire GPIO_PTOR register
screamer 0:c5e2f793b59a 317 */
screamer 0:c5e2f793b59a 318 /*@{*/
screamer 0:c5e2f793b59a 319 #define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU)
screamer 0:c5e2f793b59a 320
screamer 0:c5e2f793b59a 321 #define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 322 #define HW_GPIO_PTOR_RD(x) (ADDRESS_READ(hw_gpio_ptor_t, HW_GPIO_PTOR_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 323 #define HW_GPIO_PTOR_WR(x, v) (ADDRESS_WRITE(hw_gpio_ptor_t, HW_GPIO_PTOR_ADDR(x), v))
screamer 0:c5e2f793b59a 324 /*@}*/
screamer 0:c5e2f793b59a 325
screamer 0:c5e2f793b59a 326 /*
screamer 0:c5e2f793b59a 327 * Constants & macros for individual GPIO_PTOR bitfields
screamer 0:c5e2f793b59a 328 */
screamer 0:c5e2f793b59a 329
screamer 0:c5e2f793b59a 330 /*!
screamer 0:c5e2f793b59a 331 * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
screamer 0:c5e2f793b59a 332 *
screamer 0:c5e2f793b59a 333 * Writing to this register will update the contents of the corresponding bit in
screamer 0:c5e2f793b59a 334 * the PDOR as follows:
screamer 0:c5e2f793b59a 335 *
screamer 0:c5e2f793b59a 336 * Values:
screamer 0:c5e2f793b59a 337 * - 0 - Corresponding bit in PDORn does not change.
screamer 0:c5e2f793b59a 338 * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
screamer 0:c5e2f793b59a 339 * state.
screamer 0:c5e2f793b59a 340 */
screamer 0:c5e2f793b59a 341 /*@{*/
screamer 0:c5e2f793b59a 342 #define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */
screamer 0:c5e2f793b59a 343 #define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
screamer 0:c5e2f793b59a 344 #define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
screamer 0:c5e2f793b59a 345
screamer 0:c5e2f793b59a 346 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
screamer 0:c5e2f793b59a 347 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
screamer 0:c5e2f793b59a 348
screamer 0:c5e2f793b59a 349 /*! @brief Set the PTTO field to a new value. */
screamer 0:c5e2f793b59a 350 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
screamer 0:c5e2f793b59a 351 /*@}*/
screamer 0:c5e2f793b59a 352
screamer 0:c5e2f793b59a 353 /*******************************************************************************
screamer 0:c5e2f793b59a 354 * HW_GPIO_PDIR - Port Data Input Register
screamer 0:c5e2f793b59a 355 ******************************************************************************/
screamer 0:c5e2f793b59a 356
screamer 0:c5e2f793b59a 357 /*!
screamer 0:c5e2f793b59a 358 * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
screamer 0:c5e2f793b59a 359 *
screamer 0:c5e2f793b59a 360 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 361 *
screamer 0:c5e2f793b59a 362 * Do not modify pin configuration registers associated with pins not available
screamer 0:c5e2f793b59a 363 * in your selected package. All unbonded pins not available in your package will
screamer 0:c5e2f793b59a 364 * default to DISABLE state for lowest power consumption.
screamer 0:c5e2f793b59a 365 */
screamer 0:c5e2f793b59a 366 typedef union _hw_gpio_pdir
screamer 0:c5e2f793b59a 367 {
screamer 0:c5e2f793b59a 368 uint32_t U;
screamer 0:c5e2f793b59a 369 struct _hw_gpio_pdir_bitfields
screamer 0:c5e2f793b59a 370 {
screamer 0:c5e2f793b59a 371 uint32_t PDI : 32; /*!< [31:0] Port Data Input */
screamer 0:c5e2f793b59a 372 } B;
screamer 0:c5e2f793b59a 373 } hw_gpio_pdir_t;
screamer 0:c5e2f793b59a 374
screamer 0:c5e2f793b59a 375 /*!
screamer 0:c5e2f793b59a 376 * @name Constants and macros for entire GPIO_PDIR register
screamer 0:c5e2f793b59a 377 */
screamer 0:c5e2f793b59a 378 /*@{*/
screamer 0:c5e2f793b59a 379 #define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U)
screamer 0:c5e2f793b59a 380
screamer 0:c5e2f793b59a 381 #define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 382 #define HW_GPIO_PDIR_RD(x) (ADDRESS_READ(hw_gpio_pdir_t, HW_GPIO_PDIR_ADDR(x)))
screamer 0:c5e2f793b59a 383 /*@}*/
screamer 0:c5e2f793b59a 384
screamer 0:c5e2f793b59a 385 /*
screamer 0:c5e2f793b59a 386 * Constants & macros for individual GPIO_PDIR bitfields
screamer 0:c5e2f793b59a 387 */
screamer 0:c5e2f793b59a 388
screamer 0:c5e2f793b59a 389 /*!
screamer 0:c5e2f793b59a 390 * @name Register GPIO_PDIR, field PDI[31:0] (RO)
screamer 0:c5e2f793b59a 391 *
screamer 0:c5e2f793b59a 392 * Reads 0 at the unimplemented pins for a particular device. Pins that are not
screamer 0:c5e2f793b59a 393 * configured for a digital function read 0. If the Port Control and Interrupt
screamer 0:c5e2f793b59a 394 * module is disabled, then the corresponding bit in PDIR does not update.
screamer 0:c5e2f793b59a 395 *
screamer 0:c5e2f793b59a 396 * Values:
screamer 0:c5e2f793b59a 397 * - 0 - Pin logic level is logic 0, or is not configured for use by digital
screamer 0:c5e2f793b59a 398 * function.
screamer 0:c5e2f793b59a 399 * - 1 - Pin logic level is logic 1.
screamer 0:c5e2f793b59a 400 */
screamer 0:c5e2f793b59a 401 /*@{*/
screamer 0:c5e2f793b59a 402 #define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */
screamer 0:c5e2f793b59a 403 #define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
screamer 0:c5e2f793b59a 404 #define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */
screamer 0:c5e2f793b59a 405
screamer 0:c5e2f793b59a 406 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
screamer 0:c5e2f793b59a 407 #define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
screamer 0:c5e2f793b59a 408 /*@}*/
screamer 0:c5e2f793b59a 409
screamer 0:c5e2f793b59a 410 /*******************************************************************************
screamer 0:c5e2f793b59a 411 * HW_GPIO_PDDR - Port Data Direction Register
screamer 0:c5e2f793b59a 412 ******************************************************************************/
screamer 0:c5e2f793b59a 413
screamer 0:c5e2f793b59a 414 /*!
screamer 0:c5e2f793b59a 415 * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
screamer 0:c5e2f793b59a 416 *
screamer 0:c5e2f793b59a 417 * Reset value: 0x00000000U
screamer 0:c5e2f793b59a 418 *
screamer 0:c5e2f793b59a 419 * The PDDR configures the individual port pins for input or output.
screamer 0:c5e2f793b59a 420 */
screamer 0:c5e2f793b59a 421 typedef union _hw_gpio_pddr
screamer 0:c5e2f793b59a 422 {
screamer 0:c5e2f793b59a 423 uint32_t U;
screamer 0:c5e2f793b59a 424 struct _hw_gpio_pddr_bitfields
screamer 0:c5e2f793b59a 425 {
screamer 0:c5e2f793b59a 426 uint32_t PDD : 32; /*!< [31:0] Port Data Direction */
screamer 0:c5e2f793b59a 427 } B;
screamer 0:c5e2f793b59a 428 } hw_gpio_pddr_t;
screamer 0:c5e2f793b59a 429
screamer 0:c5e2f793b59a 430 /*!
screamer 0:c5e2f793b59a 431 * @name Constants and macros for entire GPIO_PDDR register
screamer 0:c5e2f793b59a 432 */
screamer 0:c5e2f793b59a 433 /*@{*/
screamer 0:c5e2f793b59a 434 #define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U)
screamer 0:c5e2f793b59a 435
screamer 0:c5e2f793b59a 436 #define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
Alessandro Angelino 5:41cb6fa198f3 437 #define HW_GPIO_PDDR_RD(x) (ADDRESS_READ(hw_gpio_pddr_t, HW_GPIO_PDDR_ADDR(x)))
Alessandro Angelino 5:41cb6fa198f3 438 #define HW_GPIO_PDDR_WR(x, v) (ADDRESS_WRITE(hw_gpio_pddr_t, HW_GPIO_PDDR_ADDR(x), v))
screamer 0:c5e2f793b59a 439 #define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
screamer 0:c5e2f793b59a 440 #define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
screamer 0:c5e2f793b59a 441 #define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
screamer 0:c5e2f793b59a 442 /*@}*/
screamer 0:c5e2f793b59a 443
screamer 0:c5e2f793b59a 444 /*
screamer 0:c5e2f793b59a 445 * Constants & macros for individual GPIO_PDDR bitfields
screamer 0:c5e2f793b59a 446 */
screamer 0:c5e2f793b59a 447
screamer 0:c5e2f793b59a 448 /*!
screamer 0:c5e2f793b59a 449 * @name Register GPIO_PDDR, field PDD[31:0] (RW)
screamer 0:c5e2f793b59a 450 *
screamer 0:c5e2f793b59a 451 * Configures individual port pins for input or output.
screamer 0:c5e2f793b59a 452 *
screamer 0:c5e2f793b59a 453 * Values:
screamer 0:c5e2f793b59a 454 * - 0 - Pin is configured as general-purpose input, for the GPIO function.
screamer 0:c5e2f793b59a 455 * - 1 - Pin is configured as general-purpose output, for the GPIO function.
screamer 0:c5e2f793b59a 456 */
screamer 0:c5e2f793b59a 457 /*@{*/
screamer 0:c5e2f793b59a 458 #define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */
screamer 0:c5e2f793b59a 459 #define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
screamer 0:c5e2f793b59a 460 #define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */
screamer 0:c5e2f793b59a 461
screamer 0:c5e2f793b59a 462 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
screamer 0:c5e2f793b59a 463 #define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
screamer 0:c5e2f793b59a 464
screamer 0:c5e2f793b59a 465 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
screamer 0:c5e2f793b59a 466 #define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
screamer 0:c5e2f793b59a 467
screamer 0:c5e2f793b59a 468 /*! @brief Set the PDD field to a new value. */
screamer 0:c5e2f793b59a 469 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
screamer 0:c5e2f793b59a 470 /*@}*/
screamer 0:c5e2f793b59a 471
screamer 0:c5e2f793b59a 472 /*******************************************************************************
screamer 0:c5e2f793b59a 473 * hw_gpio_t - module struct
screamer 0:c5e2f793b59a 474 ******************************************************************************/
screamer 0:c5e2f793b59a 475 /*!
screamer 0:c5e2f793b59a 476 * @brief All GPIO module registers.
screamer 0:c5e2f793b59a 477 */
screamer 0:c5e2f793b59a 478 #pragma pack(1)
screamer 0:c5e2f793b59a 479 typedef struct _hw_gpio
screamer 0:c5e2f793b59a 480 {
screamer 0:c5e2f793b59a 481 __IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */
screamer 0:c5e2f793b59a 482 __O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */
screamer 0:c5e2f793b59a 483 __O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */
screamer 0:c5e2f793b59a 484 __O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */
screamer 0:c5e2f793b59a 485 __I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */
screamer 0:c5e2f793b59a 486 __IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */
screamer 0:c5e2f793b59a 487 } hw_gpio_t;
screamer 0:c5e2f793b59a 488 #pragma pack()
screamer 0:c5e2f793b59a 489
screamer 0:c5e2f793b59a 490 /*! @brief Macro to access all GPIO registers. */
screamer 0:c5e2f793b59a 491 /*! @param x GPIO module instance base address. */
screamer 0:c5e2f793b59a 492 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
screamer 0:c5e2f793b59a 493 * use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
screamer 0:c5e2f793b59a 494 #define HW_GPIO(x) (*(hw_gpio_t *)(x))
screamer 0:c5e2f793b59a 495
screamer 0:c5e2f793b59a 496 #endif /* __HW_GPIO_REGISTERS_H__ */
screamer 0:c5e2f793b59a 497 /* EOF */