Alessandro Angelino / target-mcu-k64f

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Fork of target-mcu-k64f by Morpheus

hal/device/MK64F12/fsl_bitaccess.h@5:41cb6fa198f3, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:09:12 2016 +0100
Revision:
5:41cb6fa198f3
Parent:
0:c5e2f793b59a 
Mirror huge PR from mbed OS



The following PRs have been mirrored:

https://github.com/ARMmbed/mbed-hal-k64f/pull/6  "All Freescale macros for memory access replaced"

https://github.com/ARMmbed/mbed-hal-k64f/pull/7  "Fix bug in union access macros"

https://github.com/ARMmbed/mbed-hal-k64f/pull/8  "Simpler and more universal macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/9  "Fixed bug in fallback macros for memory access"

https://github.com/ARMmbed/mbed-hal-k64f/pull/10 "Added volatile keyword to address for union read"

https://github.com/ARMmbed/mbed-hal-k64f/pull/14 "Removing copyright and revision from unmodified file"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:c5e2f793b59a 1 /*
screamer 0:c5e2f793b59a 2 ** ###################################################################
screamer 0:c5e2f793b59a 3 ** Version: rev. 2.5, 2014-02-10
screamer 0:c5e2f793b59a 4 ** Build: b140604
screamer 0:c5e2f793b59a 5 **
screamer 0:c5e2f793b59a 6 ** Abstract:
screamer 0:c5e2f793b59a 7 ** Register bit field access macros.
screamer 0:c5e2f793b59a 8 **
screamer 0:c5e2f793b59a 9 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
screamer 0:c5e2f793b59a 10 ** All rights reserved.
screamer 0:c5e2f793b59a 11 **
Alessandro Angelino 5:41cb6fa198f3 12 ** (C) COPYRIGHT 2015-2015 ARM Limited
Alessandro Angelino 5:41cb6fa198f3 13 ** ALL RIGHTS RESERVED
Alessandro Angelino 5:41cb6fa198f3 14 **
screamer 0:c5e2f793b59a 15 ** Redistribution and use in source and binary forms, with or without modification,
screamer 0:c5e2f793b59a 16 ** are permitted provided that the following conditions are met:
screamer 0:c5e2f793b59a 17 **
screamer 0:c5e2f793b59a 18 ** o Redistributions of source code must retain the above copyright notice, this list
screamer 0:c5e2f793b59a 19 ** of conditions and the following disclaimer.
screamer 0:c5e2f793b59a 20 **
screamer 0:c5e2f793b59a 21 ** o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:c5e2f793b59a 22 ** list of conditions and the following disclaimer in the documentation and/or
screamer 0:c5e2f793b59a 23 ** other materials provided with the distribution.
screamer 0:c5e2f793b59a 24 **
screamer 0:c5e2f793b59a 25 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:c5e2f793b59a 26 ** contributors may be used to endorse or promote products derived from this
screamer 0:c5e2f793b59a 27 ** software without specific prior written permission.
screamer 0:c5e2f793b59a 28 **
screamer 0:c5e2f793b59a 29 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:c5e2f793b59a 30 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:c5e2f793b59a 31 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:c5e2f793b59a 32 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:c5e2f793b59a 33 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:c5e2f793b59a 34 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:c5e2f793b59a 35 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:c5e2f793b59a 36 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:c5e2f793b59a 37 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:c5e2f793b59a 38 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:c5e2f793b59a 39 **
screamer 0:c5e2f793b59a 40 ** http: www.freescale.com
screamer 0:c5e2f793b59a 41 ** mail: support@freescale.com
screamer 0:c5e2f793b59a 42 **
screamer 0:c5e2f793b59a 43 ** Revisions:
screamer 0:c5e2f793b59a 44 ** - rev. 1.0 (2013-08-12)
screamer 0:c5e2f793b59a 45 ** Initial version.
screamer 0:c5e2f793b59a 46 ** - rev. 2.0 (2013-10-29)
screamer 0:c5e2f793b59a 47 ** Register accessor macros added to the memory map.
screamer 0:c5e2f793b59a 48 ** Symbols for Processor Expert memory map compatibility added to the memory map.
screamer 0:c5e2f793b59a 49 ** Startup file for gcc has been updated according to CMSIS 3.2.
screamer 0:c5e2f793b59a 50 ** System initialization updated.
screamer 0:c5e2f793b59a 51 ** MCG - registers updated.
screamer 0:c5e2f793b59a 52 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
screamer 0:c5e2f793b59a 53 ** - rev. 2.1 (2013-10-30)
screamer 0:c5e2f793b59a 54 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
screamer 0:c5e2f793b59a 55 ** - rev. 2.2 (2013-12-09)
screamer 0:c5e2f793b59a 56 ** DMA - EARS register removed.
screamer 0:c5e2f793b59a 57 ** AIPS0, AIPS1 - MPRA register updated.
screamer 0:c5e2f793b59a 58 ** - rev. 2.3 (2014-01-24)
screamer 0:c5e2f793b59a 59 ** Update according to reference manual rev. 2
screamer 0:c5e2f793b59a 60 ** ENET, MCG, MCM, SIM, USB - registers updated
screamer 0:c5e2f793b59a 61 ** - rev. 2.4 (2014-02-10)
screamer 0:c5e2f793b59a 62 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 63 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 64 ** - rev. 2.5 (2014-02-10)
screamer 0:c5e2f793b59a 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
screamer 0:c5e2f793b59a 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
screamer 0:c5e2f793b59a 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Alessandro Angelino 5:41cb6fa198f3 68 ** - rev. 2.6 (2015-07-30) (ARM)
Alessandro Angelino 5:41cb6fa198f3 69 ** Macros for bitband address calculation have been decoupled from the
Alessandro Angelino 5:41cb6fa198f3 70 ** actual address de-referencing in BITBAND_ACCESSxx macros;
Alessandro Angelino 5:41cb6fa198f3 71 ** Added fallback macros for default read/write operations
screamer 0:c5e2f793b59a 72 **
screamer 0:c5e2f793b59a 73 ** ###################################################################
screamer 0:c5e2f793b59a 74 */
screamer 0:c5e2f793b59a 75
screamer 0:c5e2f793b59a 76
screamer 0:c5e2f793b59a 77 #ifndef _FSL_BITACCESS_H
screamer 0:c5e2f793b59a 78 #define _FSL_BITACCESS_H 1
screamer 0:c5e2f793b59a 79
screamer 0:c5e2f793b59a 80 #include <stdint.h>
screamer 0:c5e2f793b59a 81 #include <stdlib.h>
Alessandro Angelino 5:41cb6fa198f3 82 #include "uvisor-lib/uvisor-lib.h"
Alessandro Angelino 5:41cb6fa198f3 83
Alessandro Angelino 5:41cb6fa198f3 84 /*
Alessandro Angelino 5:41cb6fa198f3 85 * Fallback macros for write/read operations
Alessandro Angelino 5:41cb6fa198f3 86 */
Alessandro Angelino 5:41cb6fa198f3 87 #ifndef ADDRESS_READ
Alessandro Angelino 5:41cb6fa198f3 88 /* the conditional statement will be optimised away since the compiler already
Alessandro Angelino 5:41cb6fa198f3 89 * knows the sizeof(type) */
Alessandro Angelino 5:41cb6fa198f3 90 #define ADDRESS_READ(type, addr) \
Alessandro Angelino 5:41cb6fa198f3 91 (sizeof(type) == 4 ? *((volatile uint32_t *) (addr)) : \
Alessandro Angelino 5:41cb6fa198f3 92 sizeof(type) == 2 ? *((volatile uint16_t *) (addr)) : \
Alessandro Angelino 5:41cb6fa198f3 93 sizeof(type) == 1 ? *((volatile uint8_t *) (addr)) : 0)
Alessandro Angelino 5:41cb6fa198f3 94 #endif
Alessandro Angelino 5:41cb6fa198f3 95
Alessandro Angelino 5:41cb6fa198f3 96 #ifndef ADDRESS_WRITE
Alessandro Angelino 5:41cb6fa198f3 97 /* the switch statement will be optimised away since the compiler already knows
Alessandro Angelino 5:41cb6fa198f3 98 * the sizeof(type) */
Alessandro Angelino 5:41cb6fa198f3 99 #define ADDRESS_WRITE(type, addr, val) \
Alessandro Angelino 5:41cb6fa198f3 100 { \
Alessandro Angelino 5:41cb6fa198f3 101 switch(sizeof(type)) \
Alessandro Angelino 5:41cb6fa198f3 102 { \
Alessandro Angelino 5:41cb6fa198f3 103 case 4: \
Alessandro Angelino 5:41cb6fa198f3 104 *((volatile uint32_t *) (addr)) = (uint32_t) (val); \
Alessandro Angelino 5:41cb6fa198f3 105 break; \
Alessandro Angelino 5:41cb6fa198f3 106 case 2: \
Alessandro Angelino 5:41cb6fa198f3 107 *((volatile uint16_t *) (addr)) = (uint16_t) (val); \
Alessandro Angelino 5:41cb6fa198f3 108 break; \
Alessandro Angelino 5:41cb6fa198f3 109 case 1: \
Alessandro Angelino 5:41cb6fa198f3 110 *((volatile uint8_t *) (addr)) = (uint8_t ) (val); \
Alessandro Angelino 5:41cb6fa198f3 111 break; \
Alessandro Angelino 5:41cb6fa198f3 112 } \
Alessandro Angelino 5:41cb6fa198f3 113 }
Alessandro Angelino 5:41cb6fa198f3 114 #endif
Alessandro Angelino 5:41cb6fa198f3 115
Alessandro Angelino 5:41cb6fa198f3 116 #ifndef UNION_READ
Alessandro Angelino 5:41cb6fa198f3 117 #define UNION_READ(type, addr, fieldU, fieldB) ((*((volatile type *) (addr))).fieldB)
Alessandro Angelino 5:41cb6fa198f3 118 #endif
Alessandro Angelino 5:41cb6fa198f3 119
Alessandro Angelino 5:41cb6fa198f3 120 /*
Alessandro Angelino 5:41cb6fa198f3 121 * Macros to translate a pair of regular address and bit to their bit band alias
Alessandro Angelino 5:41cb6fa198f3 122 */
Alessandro Angelino 5:41cb6fa198f3 123 #define BITBAND_ADDRESS(Reg,Bit) (0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
Alessandro Angelino 5:41cb6fa198f3 124 #define BITBAND_ADDRESS32(Reg,Bit) ((uint32_t volatile*)BITBAND_ADDRESS(Reg,Bit))
Alessandro Angelino 5:41cb6fa198f3 125 #define BITBAND_ADDRESS16(Reg,Bit) ((uint16_t volatile*)BITBAND_ADDRESS(Reg,Bit))
Alessandro Angelino 5:41cb6fa198f3 126 #define BITBAND_ADDRESS8(Reg,Bit) ((uint8_t volatile*)BITBAND_ADDRESS(Reg,Bit))
screamer 0:c5e2f793b59a 127
screamer 0:c5e2f793b59a 128 /**
screamer 0:c5e2f793b59a 129 * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 130 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 131 * @param Reg Register to access.
screamer 0:c5e2f793b59a 132 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 133 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 134 */
Alessandro Angelino 5:41cb6fa198f3 135 #define BITBAND_ACCESS32(Reg,Bit) (*BITBAND_ADDRESS32(Reg,Bit))
screamer 0:c5e2f793b59a 136
screamer 0:c5e2f793b59a 137 /**
screamer 0:c5e2f793b59a 138 * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 139 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 140 * @param Reg Register to access.
screamer 0:c5e2f793b59a 141 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 142 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 143 */
Alessandro Angelino 5:41cb6fa198f3 144 #define BITBAND_ACCESS16(Reg,Bit) (*BITBAND_ADDRESS16(Reg,Bit))
screamer 0:c5e2f793b59a 145
screamer 0:c5e2f793b59a 146 /**
screamer 0:c5e2f793b59a 147 * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
screamer 0:c5e2f793b59a 148 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
screamer 0:c5e2f793b59a 149 * @param Reg Register to access.
screamer 0:c5e2f793b59a 150 * @param Bit Bit number to access.
screamer 0:c5e2f793b59a 151 * @return Value of the targeted bit in the bit band region.
screamer 0:c5e2f793b59a 152 */
Alessandro Angelino 5:41cb6fa198f3 153 #define BITBAND_ACCESS8(Reg,Bit) (*BITBAND_ADDRESS8(Reg,Bit))
screamer 0:c5e2f793b59a 154
screamer 0:c5e2f793b59a 155 /*
screamer 0:c5e2f793b59a 156 * Macros for single instance registers
screamer 0:c5e2f793b59a 157 */
screamer 0:c5e2f793b59a 158
screamer 0:c5e2f793b59a 159 #define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
screamer 0:c5e2f793b59a 160 #define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
screamer 0:c5e2f793b59a 161 #define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
screamer 0:c5e2f793b59a 162
screamer 0:c5e2f793b59a 163 #define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 164 #define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 165 #define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 166
screamer 0:c5e2f793b59a 167 #define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 168 #define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 169
screamer 0:c5e2f793b59a 170 #define BF_RD(reg, field) HW_##reg.B.field
screamer 0:c5e2f793b59a 171 #define BF_WR(reg, field, v) BW_##reg##_##field(v)
screamer 0:c5e2f793b59a 172
screamer 0:c5e2f793b59a 173 #define BF_CS1(reg, f1, v1) \
screamer 0:c5e2f793b59a 174 (HW_##reg##_CLR(BM_##reg##_##f1), \
screamer 0:c5e2f793b59a 175 HW_##reg##_SET(BF_##reg##_##f1(v1)))
screamer 0:c5e2f793b59a 176
screamer 0:c5e2f793b59a 177 #define BF_CS2(reg, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 178 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 179 BM_##reg##_##f2), \
screamer 0:c5e2f793b59a 180 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 181 BF_##reg##_##f2(v2)))
screamer 0:c5e2f793b59a 182
screamer 0:c5e2f793b59a 183 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 184 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 185 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 186 BM_##reg##_##f3), \
screamer 0:c5e2f793b59a 187 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 188 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 189 BF_##reg##_##f3(v3)))
screamer 0:c5e2f793b59a 190
screamer 0:c5e2f793b59a 191 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 192 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 193 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 194 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 195 BM_##reg##_##f4), \
screamer 0:c5e2f793b59a 196 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 197 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 198 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 199 BF_##reg##_##f4(v4)))
screamer 0:c5e2f793b59a 200
screamer 0:c5e2f793b59a 201 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 202 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 203 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 204 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 205 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 206 BM_##reg##_##f5), \
screamer 0:c5e2f793b59a 207 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 208 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 209 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 210 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 211 BF_##reg##_##f5(v5)))
screamer 0:c5e2f793b59a 212
screamer 0:c5e2f793b59a 213 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 214 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 215 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 216 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 217 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 218 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 219 BM_##reg##_##f6), \
screamer 0:c5e2f793b59a 220 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 221 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 222 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 223 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 224 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 225 BF_##reg##_##f6(v6)))
screamer 0:c5e2f793b59a 226
screamer 0:c5e2f793b59a 227 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 228 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 229 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 230 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 231 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 232 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 233 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 234 BM_##reg##_##f7), \
screamer 0:c5e2f793b59a 235 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 236 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 237 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 238 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 239 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 240 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 241 BF_##reg##_##f7(v7)))
screamer 0:c5e2f793b59a 242
screamer 0:c5e2f793b59a 243 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 244 (HW_##reg##_CLR(BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 245 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 246 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 247 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 248 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 249 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 250 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 251 BM_##reg##_##f8), \
screamer 0:c5e2f793b59a 252 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 253 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 254 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 255 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 256 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 257 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 258 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 259 BF_##reg##_##f8(v8)))
screamer 0:c5e2f793b59a 260
screamer 0:c5e2f793b59a 261 /*
screamer 0:c5e2f793b59a 262 * Macros for multiple instance registers
screamer 0:c5e2f793b59a 263 */
screamer 0:c5e2f793b59a 264
screamer 0:c5e2f793b59a 265 #define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 266 #define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 267 #define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 268
screamer 0:c5e2f793b59a 269 #define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 270 #define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 271 #define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 272
screamer 0:c5e2f793b59a 273 #define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 274 #define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 275
screamer 0:c5e2f793b59a 276 #define BF_RDn(reg, n, field) HW_##reg(n).B.field
screamer 0:c5e2f793b59a 277 #define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
screamer 0:c5e2f793b59a 278
screamer 0:c5e2f793b59a 279 #define BF_CS1n(reg, n, f1, v1) \
screamer 0:c5e2f793b59a 280 (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
screamer 0:c5e2f793b59a 281 HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
screamer 0:c5e2f793b59a 282
screamer 0:c5e2f793b59a 283 #define BF_CS2n(reg, n, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 284 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 285 BM_##reg##_##f2)), \
screamer 0:c5e2f793b59a 286 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 287 BF_##reg##_##f2(v2))))
screamer 0:c5e2f793b59a 288
screamer 0:c5e2f793b59a 289 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 290 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 291 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 292 BM_##reg##_##f3)), \
screamer 0:c5e2f793b59a 293 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 294 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 295 BF_##reg##_##f3(v3))))
screamer 0:c5e2f793b59a 296
screamer 0:c5e2f793b59a 297 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 298 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 299 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 300 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 301 BM_##reg##_##f4)), \
screamer 0:c5e2f793b59a 302 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 303 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 304 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 305 BF_##reg##_##f4(v4))))
screamer 0:c5e2f793b59a 306
screamer 0:c5e2f793b59a 307 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 308 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 309 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 310 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 311 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 312 BM_##reg##_##f5)), \
screamer 0:c5e2f793b59a 313 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 314 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 315 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 316 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 317 BF_##reg##_##f5(v5))))
screamer 0:c5e2f793b59a 318
screamer 0:c5e2f793b59a 319 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 320 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 321 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 322 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 323 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 324 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 325 BM_##reg##_##f6)), \
screamer 0:c5e2f793b59a 326 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 327 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 328 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 329 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 330 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 331 BF_##reg##_##f6(v6))))
screamer 0:c5e2f793b59a 332
screamer 0:c5e2f793b59a 333 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 334 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 335 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 336 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 337 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 338 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 339 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 340 BM_##reg##_##f7)), \
screamer 0:c5e2f793b59a 341 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 342 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 343 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 344 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 345 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 346 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 347 BF_##reg##_##f7(v7))))
screamer 0:c5e2f793b59a 348
screamer 0:c5e2f793b59a 349 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 350 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 351 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 352 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 353 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 354 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 355 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 356 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 357 BM_##reg##_##f8)), \
screamer 0:c5e2f793b59a 358 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 359 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 360 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 361 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 362 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 363 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 364 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 365 BF_##reg##_##f8(v8))))
screamer 0:c5e2f793b59a 366
screamer 0:c5e2f793b59a 367 /*
screamer 0:c5e2f793b59a 368 * Macros for single instance MULTI-BLOCK registers
screamer 0:c5e2f793b59a 369 */
screamer 0:c5e2f793b59a 370
screamer 0:c5e2f793b59a 371 #define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 372 #define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 373 #define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
screamer 0:c5e2f793b59a 374
screamer 0:c5e2f793b59a 375 #define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 376 #define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 377 #define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 378
screamer 0:c5e2f793b59a 379 #define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 380 #define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 381
screamer 0:c5e2f793b59a 382 #define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
screamer 0:c5e2f793b59a 383 #define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
screamer 0:c5e2f793b59a 384
screamer 0:c5e2f793b59a 385 #define BFn_CS1(reg, blk, f1, v1) \
screamer 0:c5e2f793b59a 386 (HW_##reg##_CLR(blk, BM_##reg##_##f1), \
screamer 0:c5e2f793b59a 387 HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
screamer 0:c5e2f793b59a 388
screamer 0:c5e2f793b59a 389 #define BFn_CS2(reg, blk, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 390 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 391 BM_##reg##_##f2), \
screamer 0:c5e2f793b59a 392 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 393 BF_##reg##_##f2(v2)))
screamer 0:c5e2f793b59a 394
screamer 0:c5e2f793b59a 395 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 396 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 397 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 398 BM_##reg##_##f3), \
screamer 0:c5e2f793b59a 399 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 400 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 401 BF_##reg##_##f3(v3)))
screamer 0:c5e2f793b59a 402
screamer 0:c5e2f793b59a 403 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 404 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 405 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 406 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 407 BM_##reg##_##f4), \
screamer 0:c5e2f793b59a 408 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 409 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 410 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 411 BF_##reg##_##f4(v4)))
screamer 0:c5e2f793b59a 412
screamer 0:c5e2f793b59a 413 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 414 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 415 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 416 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 417 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 418 BM_##reg##_##f5), \
screamer 0:c5e2f793b59a 419 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 420 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 421 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 422 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 423 BF_##reg##_##f5(v5)))
screamer 0:c5e2f793b59a 424
screamer 0:c5e2f793b59a 425 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 426 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 427 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 428 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 429 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 430 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 431 BM_##reg##_##f6), \
screamer 0:c5e2f793b59a 432 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 433 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 434 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 435 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 436 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 437 BF_##reg##_##f6(v6)))
screamer 0:c5e2f793b59a 438
screamer 0:c5e2f793b59a 439 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 440 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 441 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 442 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 443 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 444 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 445 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 446 BM_##reg##_##f7), \
screamer 0:c5e2f793b59a 447 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 448 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 449 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 450 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 451 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 452 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 453 BF_##reg##_##f7(v7)))
screamer 0:c5e2f793b59a 454
screamer 0:c5e2f793b59a 455 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 456 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 457 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 458 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 459 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 460 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 461 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 462 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 463 BM_##reg##_##f8), \
screamer 0:c5e2f793b59a 464 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 465 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 466 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 467 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 468 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 469 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 470 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 471 BF_##reg##_##f8(v8)))
screamer 0:c5e2f793b59a 472
screamer 0:c5e2f793b59a 473 /*
screamer 0:c5e2f793b59a 474 * Macros for MULTI-BLOCK multiple instance registers
screamer 0:c5e2f793b59a 475 */
screamer 0:c5e2f793b59a 476
screamer 0:c5e2f793b59a 477 #define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 478 #define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 479 #define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
screamer 0:c5e2f793b59a 480
screamer 0:c5e2f793b59a 481 #define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 482 #define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 483 #define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
screamer 0:c5e2f793b59a 484
screamer 0:c5e2f793b59a 485 #define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
screamer 0:c5e2f793b59a 486 #define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
screamer 0:c5e2f793b59a 487
screamer 0:c5e2f793b59a 488 #define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
screamer 0:c5e2f793b59a 489 #define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
screamer 0:c5e2f793b59a 490
screamer 0:c5e2f793b59a 491 #define BFn_CS1n(reg, blk, n, f1, v1) \
screamer 0:c5e2f793b59a 492 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
screamer 0:c5e2f793b59a 493 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
screamer 0:c5e2f793b59a 494
screamer 0:c5e2f793b59a 495 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
screamer 0:c5e2f793b59a 496 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 497 BM_##reg##_##f2)), \
screamer 0:c5e2f793b59a 498 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 499 BF_##reg##_##f2(v2))))
screamer 0:c5e2f793b59a 500
screamer 0:c5e2f793b59a 501 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
screamer 0:c5e2f793b59a 502 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 503 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 504 BM_##reg##_##f3)), \
screamer 0:c5e2f793b59a 505 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 506 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 507 BF_##reg##_##f3(v3))))
screamer 0:c5e2f793b59a 508
screamer 0:c5e2f793b59a 509 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
screamer 0:c5e2f793b59a 510 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 511 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 512 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 513 BM_##reg##_##f4)), \
screamer 0:c5e2f793b59a 514 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 515 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 516 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 517 BF_##reg##_##f4(v4))))
screamer 0:c5e2f793b59a 518
screamer 0:c5e2f793b59a 519 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
screamer 0:c5e2f793b59a 520 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 521 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 522 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 523 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 524 BM_##reg##_##f5)), \
screamer 0:c5e2f793b59a 525 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 526 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 527 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 528 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 529 BF_##reg##_##f5(v5))))
screamer 0:c5e2f793b59a 530
screamer 0:c5e2f793b59a 531 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
screamer 0:c5e2f793b59a 532 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 533 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 534 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 535 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 536 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 537 BM_##reg##_##f6)), \
screamer 0:c5e2f793b59a 538 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 539 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 540 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 541 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 542 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 543 BF_##reg##_##f6(v6))))
screamer 0:c5e2f793b59a 544
screamer 0:c5e2f793b59a 545 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
screamer 0:c5e2f793b59a 546 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 547 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 548 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 549 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 550 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 551 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 552 BM_##reg##_##f7)), \
screamer 0:c5e2f793b59a 553 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 554 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 555 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 556 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 557 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 558 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 559 BF_##reg##_##f7(v7))))
screamer 0:c5e2f793b59a 560
screamer 0:c5e2f793b59a 561 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
screamer 0:c5e2f793b59a 562 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
screamer 0:c5e2f793b59a 563 BM_##reg##_##f2 | \
screamer 0:c5e2f793b59a 564 BM_##reg##_##f3 | \
screamer 0:c5e2f793b59a 565 BM_##reg##_##f4 | \
screamer 0:c5e2f793b59a 566 BM_##reg##_##f5 | \
screamer 0:c5e2f793b59a 567 BM_##reg##_##f6 | \
screamer 0:c5e2f793b59a 568 BM_##reg##_##f7 | \
screamer 0:c5e2f793b59a 569 BM_##reg##_##f8)), \
screamer 0:c5e2f793b59a 570 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
screamer 0:c5e2f793b59a 571 BF_##reg##_##f2(v2) | \
screamer 0:c5e2f793b59a 572 BF_##reg##_##f3(v3) | \
screamer 0:c5e2f793b59a 573 BF_##reg##_##f4(v4) | \
screamer 0:c5e2f793b59a 574 BF_##reg##_##f5(v5) | \
screamer 0:c5e2f793b59a 575 BF_##reg##_##f6(v6) | \
screamer 0:c5e2f793b59a 576 BF_##reg##_##f7(v7) | \
screamer 0:c5e2f793b59a 577 BF_##reg##_##f8(v8))))
screamer 0:c5e2f793b59a 578
screamer 0:c5e2f793b59a 579 #endif /* _FSL_BITACCESS_H */
screamer 0:c5e2f793b59a 580
screamer 0:c5e2f793b59a 581 /******************************************************************************/