Alessandro Angelino / target-freescale-ksdk

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Fork of target-freescale-ksdk by Morpheus

TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h@0:e4d670b91a9a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:26:50 2016 +0000
Revision:
0:e4d670b91a9a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:e4d670b91a9a 1 /*
screamer 0:e4d670b91a9a 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
screamer 0:e4d670b91a9a 3 * All rights reserved.
screamer 0:e4d670b91a9a 4 *
screamer 0:e4d670b91a9a 5 * Redistribution and use in source and binary forms, with or without modification,
screamer 0:e4d670b91a9a 6 * are permitted provided that the following conditions are met:
screamer 0:e4d670b91a9a 7 *
screamer 0:e4d670b91a9a 8 * o Redistributions of source code must retain the above copyright notice, this list
screamer 0:e4d670b91a9a 9 * of conditions and the following disclaimer.
screamer 0:e4d670b91a9a 10 *
screamer 0:e4d670b91a9a 11 * o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:e4d670b91a9a 12 * list of conditions and the following disclaimer in the documentation and/or
screamer 0:e4d670b91a9a 13 * other materials provided with the distribution.
screamer 0:e4d670b91a9a 14 *
screamer 0:e4d670b91a9a 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:e4d670b91a9a 16 * contributors may be used to endorse or promote products derived from this
screamer 0:e4d670b91a9a 17 * software without specific prior written permission.
screamer 0:e4d670b91a9a 18 *
screamer 0:e4d670b91a9a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:e4d670b91a9a 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:e4d670b91a9a 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:e4d670b91a9a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:e4d670b91a9a 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:e4d670b91a9a 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:e4d670b91a9a 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:e4d670b91a9a 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:e4d670b91a9a 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:e4d670b91a9a 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:e4d670b91a9a 29 */
screamer 0:e4d670b91a9a 30 #if !defined(__FSL_FTM_HAL_H__)
screamer 0:e4d670b91a9a 31 #define __FSL_FTM_HAL_H__
screamer 0:e4d670b91a9a 32
screamer 0:e4d670b91a9a 33 #include "fsl_device_registers.h"
screamer 0:e4d670b91a9a 34 #include "fsl_ftm_features.h"
screamer 0:e4d670b91a9a 35 #include <stdbool.h>
screamer 0:e4d670b91a9a 36 #include <assert.h>
screamer 0:e4d670b91a9a 37
screamer 0:e4d670b91a9a 38 /*!
screamer 0:e4d670b91a9a 39 * @addtogroup ftm_hal
screamer 0:e4d670b91a9a 40 * @{
screamer 0:e4d670b91a9a 41 */
screamer 0:e4d670b91a9a 42
screamer 0:e4d670b91a9a 43 /*******************************************************************************
screamer 0:e4d670b91a9a 44 * Definitions
screamer 0:e4d670b91a9a 45 ******************************************************************************/
screamer 0:e4d670b91a9a 46 #define HW_CHAN0 (0U) /*!< Channel number for CHAN0.*/
screamer 0:e4d670b91a9a 47 #define HW_CHAN1 (1U) /*!< Channel number for CHAN1.*/
screamer 0:e4d670b91a9a 48 #define HW_CHAN2 (2U) /*!< Channel number for CHAN2.*/
screamer 0:e4d670b91a9a 49 #define HW_CHAN3 (3U) /*!< Channel number for CHAN3.*/
screamer 0:e4d670b91a9a 50 #define HW_CHAN4 (4U) /*!< Channel number for CHAN4.*/
screamer 0:e4d670b91a9a 51 #define HW_CHAN5 (5U) /*!< Channel number for CHAN5.*/
screamer 0:e4d670b91a9a 52 #define HW_CHAN6 (6U) /*!< Channel number for CHAN6.*/
screamer 0:e4d670b91a9a 53 #define HW_CHAN7 (7U) /*!< Channel number for CHAN7.*/
screamer 0:e4d670b91a9a 54
screamer 0:e4d670b91a9a 55 #define FTM_COMBINE_CHAN_CTRL_WIDTH (8U)
screamer 0:e4d670b91a9a 56
screamer 0:e4d670b91a9a 57 /*! @brief FlexTimer clock source selection*/
screamer 0:e4d670b91a9a 58 typedef enum _ftm_clock_source
screamer 0:e4d670b91a9a 59 {
screamer 0:e4d670b91a9a 60 kClock_source_FTM_None = 0,
screamer 0:e4d670b91a9a 61 kClock_source_FTM_SystemClk,
screamer 0:e4d670b91a9a 62 kClock_source_FTM_FixedClk,
screamer 0:e4d670b91a9a 63 kClock_source_FTM_ExternalClk
screamer 0:e4d670b91a9a 64 }ftm_clock_source_t;
screamer 0:e4d670b91a9a 65
screamer 0:e4d670b91a9a 66 /*! @brief FlexTimer counting mode selection */
screamer 0:e4d670b91a9a 67 typedef enum _ftm_counting_mode
screamer 0:e4d670b91a9a 68 {
screamer 0:e4d670b91a9a 69 kCounting_FTM_UP = 0,
screamer 0:e4d670b91a9a 70 kCounting_FTM_UpDown
screamer 0:e4d670b91a9a 71 }ftm_counting_mode_t;
screamer 0:e4d670b91a9a 72
screamer 0:e4d670b91a9a 73 /*! @brief FlexTimer pre-scaler factor selection for the clock source*/
screamer 0:e4d670b91a9a 74 typedef enum _ftm_clock_ps
screamer 0:e4d670b91a9a 75 {
screamer 0:e4d670b91a9a 76 kFtmDividedBy1 = 0,
screamer 0:e4d670b91a9a 77 kFtmDividedBy2 ,
screamer 0:e4d670b91a9a 78 kFtmDividedBy4 ,
screamer 0:e4d670b91a9a 79 kFtmDividedBy8,
screamer 0:e4d670b91a9a 80 kFtmDividedBy16,
screamer 0:e4d670b91a9a 81 kFtmDividedBy32,
screamer 0:e4d670b91a9a 82 kFtmDividedBy64,
screamer 0:e4d670b91a9a 83 kFtmDividedBy128
screamer 0:e4d670b91a9a 84 }ftm_clock_ps_t;
screamer 0:e4d670b91a9a 85
screamer 0:e4d670b91a9a 86 /*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/
screamer 0:e4d670b91a9a 87 typedef enum _ftm_deadtime_ps
screamer 0:e4d670b91a9a 88 {
screamer 0:e4d670b91a9a 89 kFtmDivided1 = 1,
screamer 0:e4d670b91a9a 90 kFtmDivided4 = 2,
screamer 0:e4d670b91a9a 91 kFtmDivided16 = 3,
screamer 0:e4d670b91a9a 92 }ftm_deadtime_ps_t;
screamer 0:e4d670b91a9a 93
screamer 0:e4d670b91a9a 94 /*! @brief FlexTimer operation mode, capture, output, dual */
screamer 0:e4d670b91a9a 95 typedef enum _ftm_config_mode_t
screamer 0:e4d670b91a9a 96 {
screamer 0:e4d670b91a9a 97 kFtmInputCapture,
screamer 0:e4d670b91a9a 98 kFtmOutputCompare,
screamer 0:e4d670b91a9a 99 kFtmEdgeAlignedPWM,
screamer 0:e4d670b91a9a 100 kFtmCenterAlignedPWM,
screamer 0:e4d670b91a9a 101 kFtmCombinedPWM,
screamer 0:e4d670b91a9a 102 kFtmDualEdgeCapture
screamer 0:e4d670b91a9a 103 }ftm_config_mode_t;
screamer 0:e4d670b91a9a 104
screamer 0:e4d670b91a9a 105 /*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */
screamer 0:e4d670b91a9a 106 typedef enum _ftm_input_capture_edge_mode_t
screamer 0:e4d670b91a9a 107 {
screamer 0:e4d670b91a9a 108 kFtmRisingEdge = 0,
screamer 0:e4d670b91a9a 109 kFtmFallingEdge,
screamer 0:e4d670b91a9a 110 kFtmRisingAndFalling
screamer 0:e4d670b91a9a 111 }ftm_input_capture_edge_mode_t;
screamer 0:e4d670b91a9a 112
screamer 0:e4d670b91a9a 113 /*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/
screamer 0:e4d670b91a9a 114 typedef enum _ftm_output_compare_edge_mode_t
screamer 0:e4d670b91a9a 115 {
screamer 0:e4d670b91a9a 116 kFtmToggleOnMatch = 0,
screamer 0:e4d670b91a9a 117 kFtmClearOnMatch,
screamer 0:e4d670b91a9a 118 kFtmSetOnMatch
screamer 0:e4d670b91a9a 119 }ftm_output_compare_edge_mode_t;
screamer 0:e4d670b91a9a 120
screamer 0:e4d670b91a9a 121 /*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */
screamer 0:e4d670b91a9a 122 typedef enum _ftm_pwm_edge_mode_t
screamer 0:e4d670b91a9a 123 {
screamer 0:e4d670b91a9a 124 kFtmHighTrue = 0,
screamer 0:e4d670b91a9a 125 kFtmLowTrue
screamer 0:e4d670b91a9a 126 }ftm_pwm_edge_mode_t;
screamer 0:e4d670b91a9a 127
screamer 0:e4d670b91a9a 128 /*! @brief FlexTimer dual capture edge mode, one shot or continuous */
screamer 0:e4d670b91a9a 129 typedef enum _ftm_dual_capture_edge_mode_t
screamer 0:e4d670b91a9a 130 {
screamer 0:e4d670b91a9a 131 kFtmOneShout = 0,
screamer 0:e4d670b91a9a 132 kFtmContinuous
screamer 0:e4d670b91a9a 133 }ftm_dual_capture_edge_mode_t;
screamer 0:e4d670b91a9a 134
screamer 0:e4d670b91a9a 135 /*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */
screamer 0:e4d670b91a9a 136 typedef enum _ftm_quad_decode_mode_t
screamer 0:e4d670b91a9a 137 {
screamer 0:e4d670b91a9a 138 kFtmQuadPhaseEncode = 0,
screamer 0:e4d670b91a9a 139 kFtmQuadCountAndDir
screamer 0:e4d670b91a9a 140 }ftm_quad_decode_mode_t;
screamer 0:e4d670b91a9a 141
screamer 0:e4d670b91a9a 142 /*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */
screamer 0:e4d670b91a9a 143 typedef enum _ftm_quad_phase_polarity_t
screamer 0:e4d670b91a9a 144 {
screamer 0:e4d670b91a9a 145 kFtmQuadPhaseNormal = 0,
screamer 0:e4d670b91a9a 146 kFtmQuadPhaseInvert
screamer 0:e4d670b91a9a 147 }ftm_quad_phase_polarity_t;
screamer 0:e4d670b91a9a 148
screamer 0:e4d670b91a9a 149 /*! @brief FlexTimer edge mode*/
screamer 0:e4d670b91a9a 150 typedef union _ftm_edge_mode_t
screamer 0:e4d670b91a9a 151 {
screamer 0:e4d670b91a9a 152 ftm_input_capture_edge_mode_t input_capture_edge_mode;
screamer 0:e4d670b91a9a 153 ftm_output_compare_edge_mode_t output_compare_edge_mode;
screamer 0:e4d670b91a9a 154 ftm_pwm_edge_mode_t ftm_pwm_edge_mode;
screamer 0:e4d670b91a9a 155 ftm_dual_capture_edge_mode_t ftm_dual_capture_edge_mode;
screamer 0:e4d670b91a9a 156 }ftm_edge_mode_t;
screamer 0:e4d670b91a9a 157
screamer 0:e4d670b91a9a 158 /*!
screamer 0:e4d670b91a9a 159 * @brief FlexTimer driver PWM parameter
screamer 0:e4d670b91a9a 160 *
screamer 0:e4d670b91a9a 161 */
screamer 0:e4d670b91a9a 162 typedef struct FtmPwmParam
screamer 0:e4d670b91a9a 163 {
screamer 0:e4d670b91a9a 164 ftm_config_mode_t mode; /*!< FlexTimer PWM operation mode */
screamer 0:e4d670b91a9a 165 ftm_pwm_edge_mode_t edgeMode; /*!< PWM output mode */
screamer 0:e4d670b91a9a 166 uint32_t uFrequencyHZ; /*!< PWM period in Hz */
screamer 0:e4d670b91a9a 167 uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
screamer 0:e4d670b91a9a 168 0=inactive signal(0% duty cycle)...
screamer 0:e4d670b91a9a 169 100=active signal (100% duty cycle). */
screamer 0:e4d670b91a9a 170 uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
screamer 0:e4d670b91a9a 171 Specifies the delay to the first edge in a PWM period.
screamer 0:e4d670b91a9a 172 If unsure please leave as 0, should be specified as
screamer 0:e4d670b91a9a 173 percentage of the PWM period*/
screamer 0:e4d670b91a9a 174 }ftm_pwm_param_t;
screamer 0:e4d670b91a9a 175
screamer 0:e4d670b91a9a 176 /*! @brief FlexTimer quadrature decode phase parameters */
screamer 0:e4d670b91a9a 177 typedef struct FtmPhaseParam
screamer 0:e4d670b91a9a 178 {
screamer 0:e4d670b91a9a 179 bool kFtmPhaseInputFilter; /*!< false: disable phase filter, true: enable phase filter */
screamer 0:e4d670b91a9a 180 uint32_t kFtmPhaseFilterVal; /*!< Filter value, used only if phase input filter is enabled */
screamer 0:e4d670b91a9a 181 ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert */
screamer 0:e4d670b91a9a 182 }ftm_phase_params_t;
screamer 0:e4d670b91a9a 183
screamer 0:e4d670b91a9a 184 /*FTM timer control*/
screamer 0:e4d670b91a9a 185 /*!
screamer 0:e4d670b91a9a 186 * @brief Sets the FTM clock source.
screamer 0:e4d670b91a9a 187 *
screamer 0:e4d670b91a9a 188 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 189 * @param clock The FTM peripheral clock selection\n
screamer 0:e4d670b91a9a 190 * bits - 00: No clock 01: system clock 10: fixed clock 11: External clock
screamer 0:e4d670b91a9a 191 */
screamer 0:e4d670b91a9a 192 static inline void FTM_HAL_SetClockSource(uint32_t ftmBaseAddr, ftm_clock_source_t clock)
screamer 0:e4d670b91a9a 193 {
screamer 0:e4d670b91a9a 194 BW_FTM_SC_CLKS(ftmBaseAddr, clock);
screamer 0:e4d670b91a9a 195 }
screamer 0:e4d670b91a9a 196
screamer 0:e4d670b91a9a 197 /*!
screamer 0:e4d670b91a9a 198 * @brief Reads the FTM clock source.
screamer 0:e4d670b91a9a 199 *
screamer 0:e4d670b91a9a 200 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 201 *
screamer 0:e4d670b91a9a 202 * @return The FTM clock source selection\n
screamer 0:e4d670b91a9a 203 * bits - 00: No clock 01: system clock 10: fixed clock 11:External clock
screamer 0:e4d670b91a9a 204 */
screamer 0:e4d670b91a9a 205 static inline uint8_t FTM_HAL_GetClockSource(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 206 {
screamer 0:e4d670b91a9a 207 return BR_FTM_SC_CLKS(ftmBaseAddr);
screamer 0:e4d670b91a9a 208 }
screamer 0:e4d670b91a9a 209
screamer 0:e4d670b91a9a 210 /*!
screamer 0:e4d670b91a9a 211 * @brief Sets the FTM clock divider.
screamer 0:e4d670b91a9a 212 *
screamer 0:e4d670b91a9a 213 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 214 * @param ps The FTM peripheral clock pre-scale divider
screamer 0:e4d670b91a9a 215 */
screamer 0:e4d670b91a9a 216 static inline void FTM_HAL_SetClockPs(uint32_t ftmBaseAddr, ftm_clock_ps_t ps)
screamer 0:e4d670b91a9a 217 {
screamer 0:e4d670b91a9a 218 BW_FTM_SC_PS(ftmBaseAddr, ps);
screamer 0:e4d670b91a9a 219 }
screamer 0:e4d670b91a9a 220
screamer 0:e4d670b91a9a 221 /*!
screamer 0:e4d670b91a9a 222 * @brief Reads the FTM clock divider.
screamer 0:e4d670b91a9a 223 *
screamer 0:e4d670b91a9a 224 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 225 *
screamer 0:e4d670b91a9a 226 * @return The FTM clock pre-scale divider
screamer 0:e4d670b91a9a 227 */
screamer 0:e4d670b91a9a 228 static inline uint8_t FTM_HAL_GetClockPs(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 229 {
screamer 0:e4d670b91a9a 230 return BR_FTM_SC_PS(ftmBaseAddr);
screamer 0:e4d670b91a9a 231 }
screamer 0:e4d670b91a9a 232
screamer 0:e4d670b91a9a 233 /*!
screamer 0:e4d670b91a9a 234 * @brief Enables the FTM peripheral timer overflow interrupt.
screamer 0:e4d670b91a9a 235 *
screamer 0:e4d670b91a9a 236 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 237 */
screamer 0:e4d670b91a9a 238 static inline void FTM_HAL_EnableTimerOverflowInt(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 239 {
screamer 0:e4d670b91a9a 240 HW_FTM_SC_SET(ftmBaseAddr, BM_FTM_SC_TOIE);
screamer 0:e4d670b91a9a 241 }
screamer 0:e4d670b91a9a 242
screamer 0:e4d670b91a9a 243 /*!
screamer 0:e4d670b91a9a 244 * @brief Disables the FTM peripheral timer overflow interrupt.
screamer 0:e4d670b91a9a 245 *
screamer 0:e4d670b91a9a 246 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 247 */
screamer 0:e4d670b91a9a 248 static inline void FTM_HAL_DisableTimerOverflowInt(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 249 {
screamer 0:e4d670b91a9a 250 HW_FTM_SC_CLR(ftmBaseAddr, BM_FTM_SC_TOIE);
screamer 0:e4d670b91a9a 251 }
screamer 0:e4d670b91a9a 252
screamer 0:e4d670b91a9a 253 /*!
screamer 0:e4d670b91a9a 254 * @brief Reads the bit that controls enabling the FTM timer overflow interrupt.
screamer 0:e4d670b91a9a 255 *
screamer 0:e4d670b91a9a 256 * @param baseAddr FTM module base address.
screamer 0:e4d670b91a9a 257 * @retval true if overflow interrupt is enabled, false if not
screamer 0:e4d670b91a9a 258 */
screamer 0:e4d670b91a9a 259 static inline bool FTM_HAL_IsOverflowIntEnabled(uint32_t baseAddr)
screamer 0:e4d670b91a9a 260 {
screamer 0:e4d670b91a9a 261 return (bool)(BR_FTM_SC_TOIE(baseAddr));
screamer 0:e4d670b91a9a 262 }
screamer 0:e4d670b91a9a 263
screamer 0:e4d670b91a9a 264 /*!
screamer 0:e4d670b91a9a 265 * @brief Clears the timer overflow interrupt flag.
screamer 0:e4d670b91a9a 266 *
screamer 0:e4d670b91a9a 267 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 268 */
screamer 0:e4d670b91a9a 269 static inline void FTM_HAL_ClearTimerOverflow(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 270 {
screamer 0:e4d670b91a9a 271 BW_FTM_SC_TOF(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 272 }
screamer 0:e4d670b91a9a 273
screamer 0:e4d670b91a9a 274 /*!
screamer 0:e4d670b91a9a 275 * @brief Returns the FTM peripheral timer overflow interrupt flag.
screamer 0:e4d670b91a9a 276 *
screamer 0:e4d670b91a9a 277 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 278 * @retval true if overflow, false if not
screamer 0:e4d670b91a9a 279 */
screamer 0:e4d670b91a9a 280 static inline bool FTM_HAL_HasTimerOverflowed(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 281 {
screamer 0:e4d670b91a9a 282 return BR_FTM_SC_TOF(ftmBaseAddr);
screamer 0:e4d670b91a9a 283 }
screamer 0:e4d670b91a9a 284
screamer 0:e4d670b91a9a 285 /*!
screamer 0:e4d670b91a9a 286 * @brief Sets the FTM center-aligned PWM select.
screamer 0:e4d670b91a9a 287 *
screamer 0:e4d670b91a9a 288 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 289 * @param mode 1:upcounting mode 0:up_down counting mode
screamer 0:e4d670b91a9a 290 */
screamer 0:e4d670b91a9a 291 static inline void FTM_HAL_SetCpwms(uint32_t ftmBaseAddr, uint8_t mode)
screamer 0:e4d670b91a9a 292 {
screamer 0:e4d670b91a9a 293 assert(mode < 2);
screamer 0:e4d670b91a9a 294 BW_FTM_SC_CPWMS(ftmBaseAddr, mode);
screamer 0:e4d670b91a9a 295 }
screamer 0:e4d670b91a9a 296
screamer 0:e4d670b91a9a 297 /*!
screamer 0:e4d670b91a9a 298 * @brief Sets the FTM peripheral current counter value.
screamer 0:e4d670b91a9a 299 *
screamer 0:e4d670b91a9a 300 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 301 * @param val FTM timer counter value to be set
screamer 0:e4d670b91a9a 302 */
screamer 0:e4d670b91a9a 303 static inline void FTM_HAL_SetCounter(uint32_t ftmBaseAddr,uint16_t val)
screamer 0:e4d670b91a9a 304 {
screamer 0:e4d670b91a9a 305 BW_FTM_CNT_COUNT(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 306 }
screamer 0:e4d670b91a9a 307
screamer 0:e4d670b91a9a 308 /*!
screamer 0:e4d670b91a9a 309 * @brief Returns the FTM peripheral current counter value.
screamer 0:e4d670b91a9a 310 *
screamer 0:e4d670b91a9a 311 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 312 * @retval current FTM timer counter value
screamer 0:e4d670b91a9a 313 */
screamer 0:e4d670b91a9a 314 static inline uint16_t FTM_HAL_GetCounter(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 315 {
screamer 0:e4d670b91a9a 316 return BR_FTM_CNT_COUNT(ftmBaseAddr);
screamer 0:e4d670b91a9a 317 }
screamer 0:e4d670b91a9a 318
screamer 0:e4d670b91a9a 319 /*!
screamer 0:e4d670b91a9a 320 * @brief Sets the FTM peripheral timer modulo value.
screamer 0:e4d670b91a9a 321 *
screamer 0:e4d670b91a9a 322 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 323 * @param val The value to be set to the timer modulo
screamer 0:e4d670b91a9a 324 */
screamer 0:e4d670b91a9a 325 static inline void FTM_HAL_SetMod(uint32_t ftmBaseAddr, uint16_t val)
screamer 0:e4d670b91a9a 326 {
screamer 0:e4d670b91a9a 327 BW_FTM_MOD_MOD(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 328 }
screamer 0:e4d670b91a9a 329
screamer 0:e4d670b91a9a 330 /*!
screamer 0:e4d670b91a9a 331 * @brief Returns the FTM peripheral counter modulo value.
screamer 0:e4d670b91a9a 332 *
screamer 0:e4d670b91a9a 333 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 334 * @retval FTM timer modulo value
screamer 0:e4d670b91a9a 335 */
screamer 0:e4d670b91a9a 336 static inline uint16_t FTM_HAL_GetMod(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 337 {
screamer 0:e4d670b91a9a 338 return BR_FTM_MOD_MOD(ftmBaseAddr);
screamer 0:e4d670b91a9a 339 }
screamer 0:e4d670b91a9a 340
screamer 0:e4d670b91a9a 341 /*!
screamer 0:e4d670b91a9a 342 * @brief Sets the FTM peripheral timer counter initial value.
screamer 0:e4d670b91a9a 343 *
screamer 0:e4d670b91a9a 344 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 345 * @param val initial value to be set
screamer 0:e4d670b91a9a 346 */
screamer 0:e4d670b91a9a 347 static inline void FTM_HAL_SetCounterInitVal(uint32_t ftmBaseAddr, uint16_t val)
screamer 0:e4d670b91a9a 348 {
screamer 0:e4d670b91a9a 349 BW_FTM_CNTIN_INIT(ftmBaseAddr, val & BM_FTM_CNTIN_INIT);
screamer 0:e4d670b91a9a 350 }
screamer 0:e4d670b91a9a 351
screamer 0:e4d670b91a9a 352 /*!
screamer 0:e4d670b91a9a 353 * @brief Returns the FTM peripheral counter initial value.
screamer 0:e4d670b91a9a 354 *
screamer 0:e4d670b91a9a 355 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 356 * @retval FTM timer counter initial value
screamer 0:e4d670b91a9a 357 */
screamer 0:e4d670b91a9a 358 static inline uint16_t FTM_HAL_GetCounterInitVal(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 359 {
screamer 0:e4d670b91a9a 360 return BR_FTM_CNTIN_INIT(ftmBaseAddr);
screamer 0:e4d670b91a9a 361 }
screamer 0:e4d670b91a9a 362
screamer 0:e4d670b91a9a 363 /*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */
screamer 0:e4d670b91a9a 364 /*!
screamer 0:e4d670b91a9a 365 * @brief Sets the FTM peripheral timer channel mode.
screamer 0:e4d670b91a9a 366 *
screamer 0:e4d670b91a9a 367 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 368 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 369 * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11
screamer 0:e4d670b91a9a 370 */
screamer 0:e4d670b91a9a 371 static inline void FTM_HAL_SetChnMSnBAMode(uint32_t ftmBaseAddr, uint8_t channel, uint8_t selection)
screamer 0:e4d670b91a9a 372 {
screamer 0:e4d670b91a9a 373 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 374 BW_FTM_CnSC_MSA(ftmBaseAddr, channel, selection & 1);
screamer 0:e4d670b91a9a 375 BW_FTM_CnSC_MSB(ftmBaseAddr, channel, selection & 2 ? 1 : 0);
screamer 0:e4d670b91a9a 376 }
screamer 0:e4d670b91a9a 377
screamer 0:e4d670b91a9a 378 /*!
screamer 0:e4d670b91a9a 379 * @brief Sets the FTM peripheral timer channel edge level.
screamer 0:e4d670b91a9a 380 *
screamer 0:e4d670b91a9a 381 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 382 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 383 * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11
screamer 0:e4d670b91a9a 384 */
screamer 0:e4d670b91a9a 385 static inline void FTM_HAL_SetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel, uint8_t level)
screamer 0:e4d670b91a9a 386 {
screamer 0:e4d670b91a9a 387 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 388 BW_FTM_CnSC_ELSA(ftmBaseAddr, channel, level & 1 ? 1 : 0);
screamer 0:e4d670b91a9a 389 BW_FTM_CnSC_ELSB(ftmBaseAddr, channel, level & 2 ? 1 : 0);
screamer 0:e4d670b91a9a 390 }
screamer 0:e4d670b91a9a 391
screamer 0:e4d670b91a9a 392 /*!
screamer 0:e4d670b91a9a 393 * @brief Gets the FTM peripheral timer channel mode.
screamer 0:e4d670b91a9a 394 *
screamer 0:e4d670b91a9a 395 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 396 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 397 * @retval The MSnB:MSnA mode value, will be 00,01, 10, 11
screamer 0:e4d670b91a9a 398 */
screamer 0:e4d670b91a9a 399 static inline uint8_t FTM_HAL_GetChnMode(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 400 {
screamer 0:e4d670b91a9a 401 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 402 return (BR_FTM_CnSC_MSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_MSB(ftmBaseAddr, channel) << 1));
screamer 0:e4d670b91a9a 403 }
screamer 0:e4d670b91a9a 404
screamer 0:e4d670b91a9a 405 /*!
screamer 0:e4d670b91a9a 406 * @brief Gets the FTM peripheral timer channel edge level.
screamer 0:e4d670b91a9a 407 *
screamer 0:e4d670b91a9a 408 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 409 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 410 * @retval The ELSnB:ELSnA mode value, will be 00,01, 10, 11
screamer 0:e4d670b91a9a 411 */
screamer 0:e4d670b91a9a 412 static inline uint8_t FTM_HAL_GetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 413 {
screamer 0:e4d670b91a9a 414 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 415 return (BR_FTM_CnSC_ELSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_ELSB(ftmBaseAddr, channel) << 1));
screamer 0:e4d670b91a9a 416 }
screamer 0:e4d670b91a9a 417
screamer 0:e4d670b91a9a 418 /*!
screamer 0:e4d670b91a9a 419 * @brief Enables or disables the FTM peripheral timer channel DMA.
screamer 0:e4d670b91a9a 420 *
screamer 0:e4d670b91a9a 421 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 422 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 423 * @param val enable or disable
screamer 0:e4d670b91a9a 424 */
screamer 0:e4d670b91a9a 425 static inline void FTM_HAL_SetChnDmaCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 426 {
screamer 0:e4d670b91a9a 427 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 428 BW_FTM_CnSC_DMA(ftmBaseAddr, channel,(val? 1 : 0));
screamer 0:e4d670b91a9a 429 }
screamer 0:e4d670b91a9a 430
screamer 0:e4d670b91a9a 431 /*!
screamer 0:e4d670b91a9a 432 * @brief Returns whether the FTM peripheral timer channel DMA is enabled.
screamer 0:e4d670b91a9a 433 *
screamer 0:e4d670b91a9a 434 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 435 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 436 * @retval true if enabled, false if disabled
screamer 0:e4d670b91a9a 437 */
screamer 0:e4d670b91a9a 438 static inline bool FTM_HAL_IsChnDma(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 439 {
screamer 0:e4d670b91a9a 440 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 441 return (BR_FTM_CnSC_DMA(ftmBaseAddr, channel) ? true : false);
screamer 0:e4d670b91a9a 442 }
screamer 0:e4d670b91a9a 443
screamer 0:e4d670b91a9a 444 /*!
screamer 0:e4d670b91a9a 445 * @brief Enables the FTM peripheral timer channel(n) interrupt.
screamer 0:e4d670b91a9a 446 *
screamer 0:e4d670b91a9a 447 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 448 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 449 */
screamer 0:e4d670b91a9a 450 static inline void FTM_HAL_EnableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 451 {
screamer 0:e4d670b91a9a 452 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 453 BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 1);
screamer 0:e4d670b91a9a 454 }
screamer 0:e4d670b91a9a 455 /*!
screamer 0:e4d670b91a9a 456 * @brief Disables the FTM peripheral timer channel(n) interrupt.
screamer 0:e4d670b91a9a 457 *
screamer 0:e4d670b91a9a 458 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 459 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 460 */
screamer 0:e4d670b91a9a 461 static inline void FTM_HAL_DisableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 462 {
screamer 0:e4d670b91a9a 463 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 464 BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 0);
screamer 0:e4d670b91a9a 465 }
screamer 0:e4d670b91a9a 466
screamer 0:e4d670b91a9a 467 /*!
screamer 0:e4d670b91a9a 468 * @brief Returns whether any event for the FTM peripheral timer channel has occurred.
screamer 0:e4d670b91a9a 469 *
screamer 0:e4d670b91a9a 470 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 471 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 472 * @retval true if event occurred, false otherwise.
screamer 0:e4d670b91a9a 473 */
screamer 0:e4d670b91a9a 474 static inline bool FTM_HAL_HasChnEventOccurred(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 475 {
screamer 0:e4d670b91a9a 476 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 477 return (BR_FTM_CnSC_CHF(ftmBaseAddr, channel)) ? true : false;
screamer 0:e4d670b91a9a 478 }
screamer 0:e4d670b91a9a 479
screamer 0:e4d670b91a9a 480 /*FTM channel control*/
screamer 0:e4d670b91a9a 481 /*!
screamer 0:e4d670b91a9a 482 * @brief Sets the FTM peripheral timer channel counter value.
screamer 0:e4d670b91a9a 483 *
screamer 0:e4d670b91a9a 484 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 485 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 486 * @param val counter value to be set
screamer 0:e4d670b91a9a 487 */
screamer 0:e4d670b91a9a 488 static inline void FTM_HAL_SetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
screamer 0:e4d670b91a9a 489 {
screamer 0:e4d670b91a9a 490 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 491 HW_FTM_CnV_WR(ftmBaseAddr, channel, val);
screamer 0:e4d670b91a9a 492 }
screamer 0:e4d670b91a9a 493
screamer 0:e4d670b91a9a 494 /*!
screamer 0:e4d670b91a9a 495 * @brief Gets the FTM peripheral timer channel counter value.
screamer 0:e4d670b91a9a 496 *
screamer 0:e4d670b91a9a 497 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 498 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 499 * @retval val return current channel counter value
screamer 0:e4d670b91a9a 500 */
screamer 0:e4d670b91a9a 501 static inline uint16_t FTM_HAL_GetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
screamer 0:e4d670b91a9a 502 {
screamer 0:e4d670b91a9a 503 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 504 return BR_FTM_CnV_VAL(ftmBaseAddr, channel);
screamer 0:e4d670b91a9a 505 }
screamer 0:e4d670b91a9a 506
screamer 0:e4d670b91a9a 507 /*!
screamer 0:e4d670b91a9a 508 * @brief Gets the FTM peripheral timer channel event status.
screamer 0:e4d670b91a9a 509 *
screamer 0:e4d670b91a9a 510 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 511 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 512 * @retval val return current channel event status value
screamer 0:e4d670b91a9a 513 */
screamer 0:e4d670b91a9a 514 static inline uint32_t FTM_HAL_GetChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 515 {
screamer 0:e4d670b91a9a 516 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 517 return (HW_FTM_STATUS_RD(ftmBaseAddr)&(1U << channel)) ? true : false;
screamer 0:e4d670b91a9a 518 /*return BR_FTM_STATUS(ftmBaseAddr, channel);*/
screamer 0:e4d670b91a9a 519 }
screamer 0:e4d670b91a9a 520
screamer 0:e4d670b91a9a 521 /*!
screamer 0:e4d670b91a9a 522 * @brief Clears the FTM peripheral timer all channel event status.
screamer 0:e4d670b91a9a 523 *
screamer 0:e4d670b91a9a 524 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 525 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 526 * @retval val return current channel counter value
screamer 0:e4d670b91a9a 527 */
screamer 0:e4d670b91a9a 528 static inline void FTM_HAL_ClearChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
screamer 0:e4d670b91a9a 529 {
screamer 0:e4d670b91a9a 530 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 531 HW_FTM_STATUS_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 532 }
screamer 0:e4d670b91a9a 533
screamer 0:e4d670b91a9a 534 /*!
screamer 0:e4d670b91a9a 535 * @brief Sets the FTM peripheral timer channel output mask.
screamer 0:e4d670b91a9a 536 *
screamer 0:e4d670b91a9a 537 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 538 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 539 * @param mask mask to be set 0 or 1, unmasked or masked
screamer 0:e4d670b91a9a 540 */
screamer 0:e4d670b91a9a 541 static inline void FTM_HAL_SetChnOutputMask(uint32_t ftmBaseAddr, uint8_t channel, bool mask)
screamer 0:e4d670b91a9a 542 {
screamer 0:e4d670b91a9a 543 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 544 mask? HW_FTM_OUTMASK_SET(ftmBaseAddr, 1U << channel) : HW_FTM_OUTMASK_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 545 /* BW_FTM_OUTMASK_CHnOM(ftmBaseAddr, channel,mask); */
screamer 0:e4d670b91a9a 546 }
screamer 0:e4d670b91a9a 547
screamer 0:e4d670b91a9a 548 /*!
screamer 0:e4d670b91a9a 549 * @brief Sets the FTM peripheral timer channel output initial state 0 or 1.
screamer 0:e4d670b91a9a 550 *
screamer 0:e4d670b91a9a 551 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 552 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 553 * @param state counter value to be set 0 or 1
screamer 0:e4d670b91a9a 554 */
screamer 0:e4d670b91a9a 555 static inline void FTM_HAL_SetChnOutputInitState(uint32_t ftmBaseAddr, uint8_t channel, uint8_t state)
screamer 0:e4d670b91a9a 556 {
screamer 0:e4d670b91a9a 557 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 558 HW_FTM_OUTINIT_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 559 HW_FTM_OUTINIT_SET(ftmBaseAddr, (uint8_t)(state << channel));
screamer 0:e4d670b91a9a 560 }
screamer 0:e4d670b91a9a 561
screamer 0:e4d670b91a9a 562 /*!
screamer 0:e4d670b91a9a 563 * @brief Sets the FTM peripheral timer channel output polarity.
screamer 0:e4d670b91a9a 564 *
screamer 0:e4d670b91a9a 565 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 566 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 567 * @param pol polarity to be set 0 or 1
screamer 0:e4d670b91a9a 568 */
screamer 0:e4d670b91a9a 569 static inline void FTM_HAL_SetChnOutputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
screamer 0:e4d670b91a9a 570 {
screamer 0:e4d670b91a9a 571 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 572 HW_FTM_POL_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 573 HW_FTM_POL_SET(ftmBaseAddr, (uint8_t)(pol << channel));
screamer 0:e4d670b91a9a 574 }
screamer 0:e4d670b91a9a 575 /*!
screamer 0:e4d670b91a9a 576 * @brief Sets the FTM peripheral timer channel input polarity.
screamer 0:e4d670b91a9a 577 *
screamer 0:e4d670b91a9a 578 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 579 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 580 * @param pol polarity to be set, 0: active high, 1:active low
screamer 0:e4d670b91a9a 581 */
screamer 0:e4d670b91a9a 582 static inline void FTM_HAL_SetChnFaultInputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
screamer 0:e4d670b91a9a 583 {
screamer 0:e4d670b91a9a 584 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 585 HW_FTM_FLTPOL_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 586 HW_FTM_FLTPOL_SET(ftmBaseAddr, (uint8_t)(pol<<channel));
screamer 0:e4d670b91a9a 587 }
screamer 0:e4d670b91a9a 588
screamer 0:e4d670b91a9a 589
screamer 0:e4d670b91a9a 590 /*Feature mode selection HAL*/
screamer 0:e4d670b91a9a 591 /*FTM fault control*/
screamer 0:e4d670b91a9a 592 /*!
screamer 0:e4d670b91a9a 593 * @brief Enables the FTM peripheral timer fault interrupt.
screamer 0:e4d670b91a9a 594 *
screamer 0:e4d670b91a9a 595 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 596 */
screamer 0:e4d670b91a9a 597 static inline void FTM_HAL_EnableFaultInt(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 598 {
screamer 0:e4d670b91a9a 599 BW_FTM_MODE_FAULTIE(ftmBaseAddr, 1);
screamer 0:e4d670b91a9a 600 }
screamer 0:e4d670b91a9a 601
screamer 0:e4d670b91a9a 602 /*!
screamer 0:e4d670b91a9a 603 * @brief Disables the FTM peripheral timer fault interrupt.
screamer 0:e4d670b91a9a 604 *
screamer 0:e4d670b91a9a 605 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 606 */
screamer 0:e4d670b91a9a 607 static inline void FTM_HAL_DisableFaultInt(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 608 {
screamer 0:e4d670b91a9a 609 BW_FTM_MODE_FAULTIE(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 610 }
screamer 0:e4d670b91a9a 611
screamer 0:e4d670b91a9a 612 /*!
screamer 0:e4d670b91a9a 613 * @brief Defines the FTM fault control mode.
screamer 0:e4d670b91a9a 614 *
screamer 0:e4d670b91a9a 615 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 616 * @param mode, valid options are 1, 2, 3, 4
screamer 0:e4d670b91a9a 617 */
screamer 0:e4d670b91a9a 618 static inline void FTM_HAL_SetFaultControlMode(uint32_t ftmBaseAddr, uint8_t mode)
screamer 0:e4d670b91a9a 619 {
screamer 0:e4d670b91a9a 620 BW_FTM_MODE_FAULTM(ftmBaseAddr, mode);
screamer 0:e4d670b91a9a 621 }
screamer 0:e4d670b91a9a 622
screamer 0:e4d670b91a9a 623 /*!
screamer 0:e4d670b91a9a 624 * @brief Enables or disables the FTM peripheral timer capture test mode.
screamer 0:e4d670b91a9a 625 *
screamer 0:e4d670b91a9a 626 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 627 * @param enable true to enable capture test mode, false to disable
screamer 0:e4d670b91a9a 628 */
screamer 0:e4d670b91a9a 629 static inline void FTM_HAL_SetCaptureTestCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 630 {
screamer 0:e4d670b91a9a 631 BW_FTM_MODE_CAPTEST(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 632 }
screamer 0:e4d670b91a9a 633
screamer 0:e4d670b91a9a 634 /*!
screamer 0:e4d670b91a9a 635 * @brief Enables or disables the FTM write protection.
screamer 0:e4d670b91a9a 636 *
screamer 0:e4d670b91a9a 637 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 638 * @param enable true: Write-protection is enabled, false: Write-protection is disabled
screamer 0:e4d670b91a9a 639 */
screamer 0:e4d670b91a9a 640 static inline void FTM_HAL_SetWriteProtectionCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 641 {
screamer 0:e4d670b91a9a 642 enable ? BW_FTM_FMS_WPEN(ftmBaseAddr, 1) : BW_FTM_MODE_WPDIS(ftmBaseAddr, 1);
screamer 0:e4d670b91a9a 643 }
screamer 0:e4d670b91a9a 644
screamer 0:e4d670b91a9a 645 /*!
screamer 0:e4d670b91a9a 646 * @brief Enables the FTM peripheral timer group.
screamer 0:e4d670b91a9a 647 *
screamer 0:e4d670b91a9a 648 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 649 * @param enable true: all registers including FTM-specific registers are available
screamer 0:e4d670b91a9a 650 * false: only the TPM-compatible registers are available
screamer 0:e4d670b91a9a 651 */
screamer 0:e4d670b91a9a 652 static inline void FTM_HAL_Enable(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 653 {
screamer 0:e4d670b91a9a 654 assert(BR_FTM_MODE_WPDIS(ftmBaseAddr));
screamer 0:e4d670b91a9a 655 BW_FTM_MODE_FTMEN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 656 }
screamer 0:e4d670b91a9a 657
screamer 0:e4d670b91a9a 658 /*!
screamer 0:e4d670b91a9a 659 * @brief Initializes the channels output.
screamer 0:e4d670b91a9a 660 *
screamer 0:e4d670b91a9a 661 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 662 * @param enable true: the channels output is initialized according to the state of OUTINIT reg
screamer 0:e4d670b91a9a 663 * false: has no effect
screamer 0:e4d670b91a9a 664 */
screamer 0:e4d670b91a9a 665 static inline void FTM_HAL_SetInitChnOutputCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 666 {
screamer 0:e4d670b91a9a 667 BW_FTM_MODE_INIT(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 668 }
screamer 0:e4d670b91a9a 669
screamer 0:e4d670b91a9a 670 /*!
screamer 0:e4d670b91a9a 671 * @brief Sets the FTM peripheral timer sync mode.
screamer 0:e4d670b91a9a 672 *
screamer 0:e4d670b91a9a 673 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 674 * @param enable true: no restriction both software and hardware triggers can be used\n
screamer 0:e4d670b91a9a 675 * false: software trigger can only be used for MOD and CnV synch, hardware trigger
screamer 0:e4d670b91a9a 676 * only for OUTMASK and FTM counter synch.
screamer 0:e4d670b91a9a 677 */
screamer 0:e4d670b91a9a 678 static inline void FTM_HAL_SetPwmSyncMode(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 679 {
screamer 0:e4d670b91a9a 680 BW_FTM_MODE_PWMSYNC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 681 }
screamer 0:e4d670b91a9a 682
screamer 0:e4d670b91a9a 683 /*FTM synchronization control*/
screamer 0:e4d670b91a9a 684 /*!
screamer 0:e4d670b91a9a 685 * @brief Enables or disables the FTM peripheral timer software trigger.
screamer 0:e4d670b91a9a 686 *
screamer 0:e4d670b91a9a 687 * @param ftmBaseAddr The FTM base address.
screamer 0:e4d670b91a9a 688 * @param enable true: software trigger is selected, false: software trigger is not selected
screamer 0:e4d670b91a9a 689 */
screamer 0:e4d670b91a9a 690 static inline void FTM_HAL_SetSoftwareTriggerCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 691 {
screamer 0:e4d670b91a9a 692 BW_FTM_SYNC_SWSYNC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 693 }
screamer 0:e4d670b91a9a 694
screamer 0:e4d670b91a9a 695 /*!
screamer 0:e4d670b91a9a 696 * @brief Sets the FTM peripheral timer hardware trigger.
screamer 0:e4d670b91a9a 697 *
screamer 0:e4d670b91a9a 698 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 699 * @param trigger_num 0, 1, 2 for trigger0, trigger1 and trigger3
screamer 0:e4d670b91a9a 700 * @param enable true: enable hardware trigger from field trigger_num for PWM synch
screamer 0:e4d670b91a9a 701 * false: disable hardware trigger from field trigger_num for PWM synch
screamer 0:e4d670b91a9a 702 */
screamer 0:e4d670b91a9a 703 void FTM_HAL_SetHardwareTrigger(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable);
screamer 0:e4d670b91a9a 704
screamer 0:e4d670b91a9a 705 /*!
screamer 0:e4d670b91a9a 706 * @brief Determines when the OUTMASK register is updated with the value of its buffer.
screamer 0:e4d670b91a9a 707 *
screamer 0:e4d670b91a9a 708 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 709 * @param enable true if OUTMASK register is updated only by PWM sync\n
screamer 0:e4d670b91a9a 710 * false if OUTMASK register is updated in all rising edges of the system clock
screamer 0:e4d670b91a9a 711 */
screamer 0:e4d670b91a9a 712 static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 713 {
screamer 0:e4d670b91a9a 714 BW_FTM_SYNC_SYNCHOM(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 715 }
screamer 0:e4d670b91a9a 716
screamer 0:e4d670b91a9a 717 /*!
screamer 0:e4d670b91a9a 718 * @brief Determines if the FTM counter is re-initialized when the selected trigger for
screamer 0:e4d670b91a9a 719 * synchronization is detected.
screamer 0:e4d670b91a9a 720 *
screamer 0:e4d670b91a9a 721 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 722 * @param enable True to update FTM counter when triggered , false to count normally
screamer 0:e4d670b91a9a 723 */
screamer 0:e4d670b91a9a 724 static inline void FTM_HAL_SetCountReinitSyncCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 725 {
screamer 0:e4d670b91a9a 726 BW_FTM_SYNC_REINIT(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 727 }
screamer 0:e4d670b91a9a 728
screamer 0:e4d670b91a9a 729 /*!
screamer 0:e4d670b91a9a 730 * @brief Enables or disables the FTM peripheral timer maximum loading points.
screamer 0:e4d670b91a9a 731 *
screamer 0:e4d670b91a9a 732 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 733 * @param enable True to enable maximum loading point, false to disable
screamer 0:e4d670b91a9a 734 */
screamer 0:e4d670b91a9a 735 static inline void FTM_HAL_SetMaxLoadingCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 736 {
screamer 0:e4d670b91a9a 737 BW_FTM_SYNC_CNTMAX(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 738 }
screamer 0:e4d670b91a9a 739 /*!
screamer 0:e4d670b91a9a 740 * @brief Enables or disables the FTM peripheral timer minimum loading points.
screamer 0:e4d670b91a9a 741 *
screamer 0:e4d670b91a9a 742 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 743 * @param enable True to enable minimum loading point, false to disable
screamer 0:e4d670b91a9a 744 */
screamer 0:e4d670b91a9a 745 static inline void FTM_HAL_SetMinLoadingCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 746 {
screamer 0:e4d670b91a9a 747 BW_FTM_SYNC_CNTMIN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 748 }
screamer 0:e4d670b91a9a 749
screamer 0:e4d670b91a9a 750 /*!
screamer 0:e4d670b91a9a 751 * @brief Combines the channel control.
screamer 0:e4d670b91a9a 752 *
screamer 0:e4d670b91a9a 753 * Returns an index for each channel pair.
screamer 0:e4d670b91a9a 754 *
screamer 0:e4d670b91a9a 755 * @param channel The FTM peripheral channel number.
screamer 0:e4d670b91a9a 756 * @return 0 for channel pair 0 & 1\n
screamer 0:e4d670b91a9a 757 * 1 for channel pair 2 & 3\n
screamer 0:e4d670b91a9a 758 * 2 for channel pair 4 & 5\n
screamer 0:e4d670b91a9a 759 * 3 for channel pair 6 & 7
screamer 0:e4d670b91a9a 760 */
screamer 0:e4d670b91a9a 761 uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel);
screamer 0:e4d670b91a9a 762
screamer 0:e4d670b91a9a 763 /*!
screamer 0:e4d670b91a9a 764 * @brief Enables the FTM peripheral timer channel pair fault control.
screamer 0:e4d670b91a9a 765 *
screamer 0:e4d670b91a9a 766 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 767 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 768 * @param enable True to enable fault control, false to disable
screamer 0:e4d670b91a9a 769 */
screamer 0:e4d670b91a9a 770 static inline void FTM_HAL_SetDualChnFaultCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 771 {
screamer 0:e4d670b91a9a 772 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 773
screamer 0:e4d670b91a9a 774 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 775 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 776 }
screamer 0:e4d670b91a9a 777
screamer 0:e4d670b91a9a 778 /*!
screamer 0:e4d670b91a9a 779 * @brief Enables or disables the FTM peripheral timer channel pair counter PWM sync.
screamer 0:e4d670b91a9a 780 *
screamer 0:e4d670b91a9a 781 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 782 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 783 * @param enable True to enable PWM synchronization, false to disable
screamer 0:e4d670b91a9a 784 */
screamer 0:e4d670b91a9a 785 static inline void FTM_HAL_SetDualChnPwmSyncCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 786 {
screamer 0:e4d670b91a9a 787 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 788
screamer 0:e4d670b91a9a 789 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 790 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 791 }
screamer 0:e4d670b91a9a 792
screamer 0:e4d670b91a9a 793 /*!
screamer 0:e4d670b91a9a 794 * @brief Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
screamer 0:e4d670b91a9a 795 *
screamer 0:e4d670b91a9a 796 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 797 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 798 * @param enable True to enable deadtime insertion, false to disable
screamer 0:e4d670b91a9a 799 */
screamer 0:e4d670b91a9a 800 static inline void FTM_HAL_SetDualChnDeadtimeCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 801 {
screamer 0:e4d670b91a9a 802 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 803
screamer 0:e4d670b91a9a 804 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 805 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 806 }
screamer 0:e4d670b91a9a 807
screamer 0:e4d670b91a9a 808 /*!
screamer 0:e4d670b91a9a 809 * @brief Enables or disables the FTM peripheral timer channel dual edge capture decap.
screamer 0:e4d670b91a9a 810 *
screamer 0:e4d670b91a9a 811 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 812 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 813 * @param enable True to enable dual edge capture mode, false to disable
screamer 0:e4d670b91a9a 814 */
screamer 0:e4d670b91a9a 815 static inline void FTM_HAL_SetDualChnDecapCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 816 {
screamer 0:e4d670b91a9a 817 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 818
screamer 0:e4d670b91a9a 819 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 820 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 821 }
screamer 0:e4d670b91a9a 822
screamer 0:e4d670b91a9a 823 /*!
screamer 0:e4d670b91a9a 824 * @brief Enables the FTM peripheral timer dual edge capture mode.
screamer 0:e4d670b91a9a 825 *
screamer 0:e4d670b91a9a 826 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 827 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 828 * @param enable True to enable dual edge capture, false to disable
screamer 0:e4d670b91a9a 829 */
screamer 0:e4d670b91a9a 830 static inline void FTM_HAL_SetDualEdgeCaptureCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 831 {
screamer 0:e4d670b91a9a 832 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 833
screamer 0:e4d670b91a9a 834 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 835 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 836 }
screamer 0:e4d670b91a9a 837
screamer 0:e4d670b91a9a 838 /*!
screamer 0:e4d670b91a9a 839 * @brief Enables or disables the FTM peripheral timer channel pair output complement mode.
screamer 0:e4d670b91a9a 840 *
screamer 0:e4d670b91a9a 841 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 842 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 843 * @param enable True to enable complementary mode, false to disable
screamer 0:e4d670b91a9a 844 */
screamer 0:e4d670b91a9a 845 static inline void FTM_HAL_SetDualChnCompCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 846 {
screamer 0:e4d670b91a9a 847 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 848
screamer 0:e4d670b91a9a 849 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 850 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 851
screamer 0:e4d670b91a9a 852 }
screamer 0:e4d670b91a9a 853
screamer 0:e4d670b91a9a 854 /*!
screamer 0:e4d670b91a9a 855 * @brief Enables or disables the FTM peripheral timer channel pair output combine mode.
screamer 0:e4d670b91a9a 856 *
screamer 0:e4d670b91a9a 857 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 858 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 859 * @param enable True to enable channel pair to combine, false to disable
screamer 0:e4d670b91a9a 860 */
screamer 0:e4d670b91a9a 861 static inline void FTM_HAL_SetDualChnCombineCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
screamer 0:e4d670b91a9a 862 {
screamer 0:e4d670b91a9a 863 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 864
screamer 0:e4d670b91a9a 865 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
screamer 0:e4d670b91a9a 866 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
screamer 0:e4d670b91a9a 867 }
screamer 0:e4d670b91a9a 868
screamer 0:e4d670b91a9a 869 /*FTM dead time insertion control*/
screamer 0:e4d670b91a9a 870 /*!
screamer 0:e4d670b91a9a 871 * @brief Sets the FTM deadtime divider.
screamer 0:e4d670b91a9a 872 *
screamer 0:e4d670b91a9a 873 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 874 * @param divider The FTM peripheral prescale divider\n
screamer 0:e4d670b91a9a 875 * 0x :divided by 1, 10: divided by 4, 11:divided by 16
screamer 0:e4d670b91a9a 876 */
screamer 0:e4d670b91a9a 877 static inline void FTM_HAL_SetDeadtimePrescale(uint32_t ftmBaseAddr, ftm_deadtime_ps_t divider)
screamer 0:e4d670b91a9a 878 {
screamer 0:e4d670b91a9a 879 BW_FTM_DEADTIME_DTPS(ftmBaseAddr, divider);
screamer 0:e4d670b91a9a 880 }
screamer 0:e4d670b91a9a 881
screamer 0:e4d670b91a9a 882 /*!
screamer 0:e4d670b91a9a 883 * @brief Sets the FTM deadtime value.
screamer 0:e4d670b91a9a 884 *
screamer 0:e4d670b91a9a 885 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 886 * @param count The FTM peripheral prescale divider\n
screamer 0:e4d670b91a9a 887 * 0: no counts inserted, 1: 1 count is inserted, 2: 2 count is inserted....
screamer 0:e4d670b91a9a 888 */
screamer 0:e4d670b91a9a 889 static inline void FTM_HAL_SetDeadtimeCount(uint32_t ftmBaseAddr, uint8_t count)
screamer 0:e4d670b91a9a 890 {
screamer 0:e4d670b91a9a 891 BW_FTM_DEADTIME_DTVAL(ftmBaseAddr, count);
screamer 0:e4d670b91a9a 892 }
screamer 0:e4d670b91a9a 893
screamer 0:e4d670b91a9a 894 /*!
screamer 0:e4d670b91a9a 895 * @brief Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register.
screamer 0:e4d670b91a9a 896 *
screamer 0:e4d670b91a9a 897 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 898 * @param enable True to enable, false to disable
screamer 0:e4d670b91a9a 899 */
screamer 0:e4d670b91a9a 900 static inline void FTM_HAL_SetInitTriggerCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 901 {
screamer 0:e4d670b91a9a 902 BW_FTM_EXTTRIG_INITTRIGEN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 903 }
screamer 0:e4d670b91a9a 904
screamer 0:e4d670b91a9a 905 /*FTM external trigger */
screamer 0:e4d670b91a9a 906 /*!
screamer 0:e4d670b91a9a 907 * @brief Enables or disables the generation of the FTM peripheral timer channel trigger.
screamer 0:e4d670b91a9a 908 *
screamer 0:e4d670b91a9a 909 * Enables or disables the when the generation of the FTM peripheral timer channel trigger when the
screamer 0:e4d670b91a9a 910 * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers.
screamer 0:e4d670b91a9a 911 *
screamer 0:e4d670b91a9a 912 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 913 * @param channel Channel to be enabled, valid value 0, 1, 2, 3, 4, 5
screamer 0:e4d670b91a9a 914 * @param val True to enable, false to disable
screamer 0:e4d670b91a9a 915 */
screamer 0:e4d670b91a9a 916 void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val);
screamer 0:e4d670b91a9a 917
screamer 0:e4d670b91a9a 918 /*!
screamer 0:e4d670b91a9a 919 * @brief Checks whether any channel trigger event has occurred.
screamer 0:e4d670b91a9a 920 *
screamer 0:e4d670b91a9a 921 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 922 * @retval true if there is a channel trigger event, false if not.
screamer 0:e4d670b91a9a 923 */
screamer 0:e4d670b91a9a 924 static inline bool FTM_HAL_IsChnTriggerGenerated(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 925 {
screamer 0:e4d670b91a9a 926 return BR_FTM_EXTTRIG_TRIGF(ftmBaseAddr);
screamer 0:e4d670b91a9a 927 }
screamer 0:e4d670b91a9a 928
screamer 0:e4d670b91a9a 929
screamer 0:e4d670b91a9a 930 /*Fault mode status*/
screamer 0:e4d670b91a9a 931 /*!
screamer 0:e4d670b91a9a 932 * @brief Gets the FTM detected fault input.
screamer 0:e4d670b91a9a 933 *
screamer 0:e4d670b91a9a 934 * This function reads the status for all fault inputs
screamer 0:e4d670b91a9a 935 *
screamer 0:e4d670b91a9a 936 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 937 * @retval Return fault byte
screamer 0:e4d670b91a9a 938 */
screamer 0:e4d670b91a9a 939 static inline uint8_t FTM_HAL_GetDetectedFaultInput(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 940 {
screamer 0:e4d670b91a9a 941 return (HW_FTM_FMS(ftmBaseAddr).U & 0x0f);
screamer 0:e4d670b91a9a 942 }
screamer 0:e4d670b91a9a 943 /*!
screamer 0:e4d670b91a9a 944 * @brief Checks whether the write protection is enabled.
screamer 0:e4d670b91a9a 945 *
screamer 0:e4d670b91a9a 946 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 947 * @retval True if enabled, false if not
screamer 0:e4d670b91a9a 948 */
screamer 0:e4d670b91a9a 949 static inline bool FTM_HAL_IsWriteProtectionEnabled(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 950 {
screamer 0:e4d670b91a9a 951 return BR_FTM_FMS_WPEN(ftmBaseAddr) ? true : false;
screamer 0:e4d670b91a9a 952 }
screamer 0:e4d670b91a9a 953
screamer 0:e4d670b91a9a 954 /*Quadrature decoder control*/
screamer 0:e4d670b91a9a 955
screamer 0:e4d670b91a9a 956 /*!
screamer 0:e4d670b91a9a 957 * @brief Enables the channel quadrature decoder.
screamer 0:e4d670b91a9a 958 *
screamer 0:e4d670b91a9a 959 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 960 * @param enable True to enable, false to disable
screamer 0:e4d670b91a9a 961 */
screamer 0:e4d670b91a9a 962 static inline void FTM_HAL_SetQuadDecoderCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 963 {
screamer 0:e4d670b91a9a 964 BW_FTM_QDCTRL_QUADEN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 965 }
screamer 0:e4d670b91a9a 966
screamer 0:e4d670b91a9a 967 /*!
screamer 0:e4d670b91a9a 968 * @brief Enables or disables the phase A input filter.
screamer 0:e4d670b91a9a 969 *
screamer 0:e4d670b91a9a 970 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 971 * @param enable true enables the phase input filter, false disables the filter
screamer 0:e4d670b91a9a 972 */
screamer 0:e4d670b91a9a 973 static inline void FTM_HAL_SetQuadPhaseAFilterCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 974 {
screamer 0:e4d670b91a9a 975 BW_FTM_QDCTRL_PHAFLTREN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 976 }
screamer 0:e4d670b91a9a 977
screamer 0:e4d670b91a9a 978 /*!
screamer 0:e4d670b91a9a 979 * @brief Enables or disables the phase B input filter.
screamer 0:e4d670b91a9a 980 *
screamer 0:e4d670b91a9a 981 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 982 * @param enable true enables the phase input filter, false disables the filter
screamer 0:e4d670b91a9a 983 */
screamer 0:e4d670b91a9a 984 static inline void FTM_HAL_SetQuadPhaseBFilterCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 985 {
screamer 0:e4d670b91a9a 986 BW_FTM_QDCTRL_PHBFLTREN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 987 }
screamer 0:e4d670b91a9a 988
screamer 0:e4d670b91a9a 989 /*!
screamer 0:e4d670b91a9a 990 * @brief Selects polarity for the quadrature decode phase A input.
screamer 0:e4d670b91a9a 991 *
screamer 0:e4d670b91a9a 992 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 993 * @param mode 0: Normal polarity, 1: Inverted polarity
screamer 0:e4d670b91a9a 994 */
screamer 0:e4d670b91a9a 995 static inline void FTM_HAL_SetQuadPhaseAPolarity(uint32_t ftmBaseAddr,
screamer 0:e4d670b91a9a 996 ftm_quad_phase_polarity_t mode)
screamer 0:e4d670b91a9a 997 {
screamer 0:e4d670b91a9a 998 BW_FTM_QDCTRL_PHAPOL(ftmBaseAddr, mode);
screamer 0:e4d670b91a9a 999 }
screamer 0:e4d670b91a9a 1000
screamer 0:e4d670b91a9a 1001 /*!
screamer 0:e4d670b91a9a 1002 * @brief Selects polarity for the quadrature decode phase B input.
screamer 0:e4d670b91a9a 1003 *
screamer 0:e4d670b91a9a 1004 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1005 * @param mode 0: Normal polarity, 1: Inverted polarity
screamer 0:e4d670b91a9a 1006 */
screamer 0:e4d670b91a9a 1007 static inline void FTM_HAL_SetQuadPhaseBPolarity(uint32_t ftmBaseAddr,
screamer 0:e4d670b91a9a 1008 ftm_quad_phase_polarity_t mode)
screamer 0:e4d670b91a9a 1009 {
screamer 0:e4d670b91a9a 1010 BW_FTM_QDCTRL_PHBPOL(ftmBaseAddr, mode);
screamer 0:e4d670b91a9a 1011 }
screamer 0:e4d670b91a9a 1012
screamer 0:e4d670b91a9a 1013 /*!
screamer 0:e4d670b91a9a 1014 * @brief Sets the encoding mode used in quadrature decoding mode.
screamer 0:e4d670b91a9a 1015 *
screamer 0:e4d670b91a9a 1016 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1017 * @param quadMode 0: Phase A and Phase B encoding mode\n
screamer 0:e4d670b91a9a 1018 * 1: Count and direction encoding mode
screamer 0:e4d670b91a9a 1019 */
screamer 0:e4d670b91a9a 1020 static inline void FTM_HAL_SetQuadMode(uint32_t ftmBaseAddr, ftm_quad_decode_mode_t quadMode)
screamer 0:e4d670b91a9a 1021 {
screamer 0:e4d670b91a9a 1022 BW_FTM_QDCTRL_QUADMODE(ftmBaseAddr, quadMode);
screamer 0:e4d670b91a9a 1023 }
screamer 0:e4d670b91a9a 1024
screamer 0:e4d670b91a9a 1025 /*!
screamer 0:e4d670b91a9a 1026 * @brief Gets the FTM counter direction in quadrature mode.
screamer 0:e4d670b91a9a 1027 *
screamer 0:e4d670b91a9a 1028 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1029 *
screamer 0:e4d670b91a9a 1030 * @retval 1 if counting direction is increasing, 0 if counting direction is decreasing
screamer 0:e4d670b91a9a 1031 */
screamer 0:e4d670b91a9a 1032 static inline uint8_t FTM_HAL_GetQuadDir(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 1033 {
screamer 0:e4d670b91a9a 1034 return BR_FTM_QDCTRL_QUADMODE(ftmBaseAddr);
screamer 0:e4d670b91a9a 1035 }
screamer 0:e4d670b91a9a 1036
screamer 0:e4d670b91a9a 1037 /*!
screamer 0:e4d670b91a9a 1038 * @brief Gets the Timer overflow direction in quadrature mode.
screamer 0:e4d670b91a9a 1039 *
screamer 0:e4d670b91a9a 1040 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1041 *
screamer 0:e4d670b91a9a 1042 * @retval 1 if TOF bit was set on the top of counting, o if TOF bit was set on the bottom of counting
screamer 0:e4d670b91a9a 1043 */
screamer 0:e4d670b91a9a 1044 static inline uint8_t FTM_HAL_GetQuadTimerOverflowDir(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 1045 {
screamer 0:e4d670b91a9a 1046 return BR_FTM_QDCTRL_TOFDIR(ftmBaseAddr);
screamer 0:e4d670b91a9a 1047 }
screamer 0:e4d670b91a9a 1048
screamer 0:e4d670b91a9a 1049 /*!
screamer 0:e4d670b91a9a 1050 * @brief Sets the FTM peripheral timer channel input capture filter value.
screamer 0:e4d670b91a9a 1051 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1052 * @param channel The FTM peripheral channel number, only 0,1,2,3, channel 4, 5,6, 7 don't have.
screamer 0:e4d670b91a9a 1053 * @param val Filter value to be set
screamer 0:e4d670b91a9a 1054 */
screamer 0:e4d670b91a9a 1055 void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val);
screamer 0:e4d670b91a9a 1056
screamer 0:e4d670b91a9a 1057 /*!
screamer 0:e4d670b91a9a 1058 * @brief Sets the fault input filter value.
screamer 0:e4d670b91a9a 1059 *
screamer 0:e4d670b91a9a 1060 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1061 * @param val fault input filter value
screamer 0:e4d670b91a9a 1062 */
screamer 0:e4d670b91a9a 1063 static inline void FTM_HAL_SetFaultInputFilterVal(uint32_t ftmBaseAddr, uint32_t val)
screamer 0:e4d670b91a9a 1064 {
screamer 0:e4d670b91a9a 1065 BW_FTM_FLTCTRL_FFVAL(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 1066 }
screamer 0:e4d670b91a9a 1067
screamer 0:e4d670b91a9a 1068 /*!
screamer 0:e4d670b91a9a 1069 * @brief Enables or disables the fault input filter.
screamer 0:e4d670b91a9a 1070 *
screamer 0:e4d670b91a9a 1071 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1072 * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
screamer 0:e4d670b91a9a 1073 * @param val true to enable fault input filter, false to disable fault input filter
screamer 0:e4d670b91a9a 1074 */
screamer 0:e4d670b91a9a 1075 static inline void FTM_HAL_SetFaultInputFilterCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
screamer 0:e4d670b91a9a 1076 {
screamer 0:e4d670b91a9a 1077 assert(inputNum < HW_CHAN4);
screamer 0:e4d670b91a9a 1078 val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << (inputNum + 4))) :
screamer 0:e4d670b91a9a 1079 HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << (inputNum + 4)));
screamer 0:e4d670b91a9a 1080 }
screamer 0:e4d670b91a9a 1081
screamer 0:e4d670b91a9a 1082 /*!
screamer 0:e4d670b91a9a 1083 * @brief Enables or disables the fault input.
screamer 0:e4d670b91a9a 1084 *
screamer 0:e4d670b91a9a 1085 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1086 * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
screamer 0:e4d670b91a9a 1087 * @param val true to enable fault input, false to disable fault input
screamer 0:e4d670b91a9a 1088 */
screamer 0:e4d670b91a9a 1089 static inline void FTM_HAL_SetFaultInputCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
screamer 0:e4d670b91a9a 1090 {
screamer 0:e4d670b91a9a 1091 assert(inputNum < HW_CHAN4);
screamer 0:e4d670b91a9a 1092 val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << inputNum)) :
screamer 0:e4d670b91a9a 1093 HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << inputNum));
screamer 0:e4d670b91a9a 1094 }
screamer 0:e4d670b91a9a 1095
screamer 0:e4d670b91a9a 1096 /*!
screamer 0:e4d670b91a9a 1097 * @brief Enables or disables the channel invert for a channel pair.
screamer 0:e4d670b91a9a 1098 *
screamer 0:e4d670b91a9a 1099 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1100 * @param channel The FTM peripheral channel number
screamer 0:e4d670b91a9a 1101 * @param val true to enable channel inverting, false to disable channel inverting
screamer 0:e4d670b91a9a 1102 */
screamer 0:e4d670b91a9a 1103 static inline void FTM_HAL_SetDualChnInvertCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 1104 {
screamer 0:e4d670b91a9a 1105 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 1106
screamer 0:e4d670b91a9a 1107 val ? HW_FTM_INVCTRL_SET(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel))) :
screamer 0:e4d670b91a9a 1108 HW_FTM_INVCTRL_CLR(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel)));
screamer 0:e4d670b91a9a 1109 }
screamer 0:e4d670b91a9a 1110
screamer 0:e4d670b91a9a 1111 /*FTM software output control*/
screamer 0:e4d670b91a9a 1112 /*!
screamer 0:e4d670b91a9a 1113 * @brief Enables or disables the channel software output control.
screamer 0:e4d670b91a9a 1114 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1115 * @param channel Channel to be enabled or disabled
screamer 0:e4d670b91a9a 1116 * @param val true to enable, channel output will be affected by software output control\n
screamer 0:e4d670b91a9a 1117 false to disable, channel output is unaffected
screamer 0:e4d670b91a9a 1118 */
screamer 0:e4d670b91a9a 1119 static inline void FTM_HAL_SetChnSoftwareCtrlCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 1120 {
screamer 0:e4d670b91a9a 1121 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 1122 val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << channel)) :
screamer 0:e4d670b91a9a 1123 HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << channel));
screamer 0:e4d670b91a9a 1124 }
screamer 0:e4d670b91a9a 1125 /*!
screamer 0:e4d670b91a9a 1126 * @brief Sets the channel software output control value.
screamer 0:e4d670b91a9a 1127 *
screamer 0:e4d670b91a9a 1128 * @param ftmBaseAddr The FTM base address.
screamer 0:e4d670b91a9a 1129 * @param channel Channel to be configured
screamer 0:e4d670b91a9a 1130 * @param val True to set 1, false to set 0
screamer 0:e4d670b91a9a 1131 */
screamer 0:e4d670b91a9a 1132 static inline void FTM_HAL_SetChnSoftwareCtrlVal(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 1133 {
screamer 0:e4d670b91a9a 1134 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 1135 val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << (channel + 8))) :
screamer 0:e4d670b91a9a 1136 HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << (channel + 8)));
screamer 0:e4d670b91a9a 1137 }
screamer 0:e4d670b91a9a 1138
screamer 0:e4d670b91a9a 1139 /*FTM PWM load control*/
screamer 0:e4d670b91a9a 1140 /*!
screamer 0:e4d670b91a9a 1141 * @brief Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
screamer 0:e4d670b91a9a 1142 *
screamer 0:e4d670b91a9a 1143 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1144 * @param enable true to enable, false to disable
screamer 0:e4d670b91a9a 1145 */
screamer 0:e4d670b91a9a 1146 static inline void FTM_HAL_SetPwmLoadCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1147 {
screamer 0:e4d670b91a9a 1148 BW_FTM_PWMLOAD_LDOK(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1149 }
screamer 0:e4d670b91a9a 1150
screamer 0:e4d670b91a9a 1151 /*!
screamer 0:e4d670b91a9a 1152 * @brief Includes or excludes the channel in the matching process.
screamer 0:e4d670b91a9a 1153 *
screamer 0:e4d670b91a9a 1154 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1155 * @param channel Channel to be configured
screamer 0:e4d670b91a9a 1156 * @param val true means include the channel in the matching process\n
screamer 0:e4d670b91a9a 1157 * false means do not include channel in the matching process
screamer 0:e4d670b91a9a 1158 */
screamer 0:e4d670b91a9a 1159 static inline void FTM_HAL_SetPwmLoadChnSelCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 1160 {
screamer 0:e4d670b91a9a 1161 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
screamer 0:e4d670b91a9a 1162 val ? HW_FTM_PWMLOAD_SET(ftmBaseAddr, 1U << channel) : HW_FTM_PWMLOAD_CLR(ftmBaseAddr, 1U << channel);
screamer 0:e4d670b91a9a 1163 }
screamer 0:e4d670b91a9a 1164
screamer 0:e4d670b91a9a 1165 /*FTM configuration*/
screamer 0:e4d670b91a9a 1166 /*!
screamer 0:e4d670b91a9a 1167 * @brief Enables or disables the FTM global time base signal generation to other FTM's.
screamer 0:e4d670b91a9a 1168 *
screamer 0:e4d670b91a9a 1169 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1170 * @param enable True to enable, false to disable
screamer 0:e4d670b91a9a 1171 */
screamer 0:e4d670b91a9a 1172 static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1173 {
screamer 0:e4d670b91a9a 1174 BW_FTM_CONF_GTBEOUT(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1175 }
screamer 0:e4d670b91a9a 1176
screamer 0:e4d670b91a9a 1177 /*!
screamer 0:e4d670b91a9a 1178 * @brief Enables or disables the FTM timer global time base.
screamer 0:e4d670b91a9a 1179 *
screamer 0:e4d670b91a9a 1180 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1181 * @param enable True to enable, false to disable
screamer 0:e4d670b91a9a 1182 */
screamer 0:e4d670b91a9a 1183 static inline void FTM_HAL_SetGlobalTimeBaseCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1184 {
screamer 0:e4d670b91a9a 1185 BW_FTM_CONF_GTBEEN(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1186 }
screamer 0:e4d670b91a9a 1187
screamer 0:e4d670b91a9a 1188 /*!
screamer 0:e4d670b91a9a 1189 * @brief Sets the BDM mode..
screamer 0:e4d670b91a9a 1190 *
screamer 0:e4d670b91a9a 1191 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1192 * @param val FTM behaviour in BDM mode, options are 0,1,2,3
screamer 0:e4d670b91a9a 1193 */
screamer 0:e4d670b91a9a 1194 static inline void FTM_HAL_SetBdmMode(uint32_t ftmBaseAddr, uint8_t val)
screamer 0:e4d670b91a9a 1195 {
screamer 0:e4d670b91a9a 1196 BW_FTM_CONF_BDMMODE(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 1197 }
screamer 0:e4d670b91a9a 1198
screamer 0:e4d670b91a9a 1199 /*!
screamer 0:e4d670b91a9a 1200 * @brief Sets the FTM timer TOF Frequency
screamer 0:e4d670b91a9a 1201 *
screamer 0:e4d670b91a9a 1202 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1203 * @param val Value of the TOF bit set frequency
screamer 0:e4d670b91a9a 1204 */
screamer 0:e4d670b91a9a 1205 static inline void FTM_HAL_SetTofFreq(uint32_t ftmBaseAddr, uint8_t val)
screamer 0:e4d670b91a9a 1206 {
screamer 0:e4d670b91a9a 1207 BW_FTM_CONF_NUMTOF(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 1208 }
screamer 0:e4d670b91a9a 1209
screamer 0:e4d670b91a9a 1210 /*FTM sync configuration*/
screamer 0:e4d670b91a9a 1211 /*hardware sync*/
screamer 0:e4d670b91a9a 1212 /*!
screamer 0:e4d670b91a9a 1213 * @brief Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
screamer 0:e4d670b91a9a 1214 *
screamer 0:e4d670b91a9a 1215 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1216 * @param enable true means the hardware trigger activates register sync\n
screamer 0:e4d670b91a9a 1217 * false means the hardware trigger does not activate register sync.
screamer 0:e4d670b91a9a 1218 */
screamer 0:e4d670b91a9a 1219 static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1220 {
screamer 0:e4d670b91a9a 1221 BW_FTM_SYNCONF_HWSOC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1222 }
screamer 0:e4d670b91a9a 1223
screamer 0:e4d670b91a9a 1224 /*!
screamer 0:e4d670b91a9a 1225 * @brief Sets sync mode for FTM INVCTRL register when using a hardware trigger.
screamer 0:e4d670b91a9a 1226 *
screamer 0:e4d670b91a9a 1227 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1228 * @param enable true means the hardware trigger activates register sync\n
screamer 0:e4d670b91a9a 1229 * false means the hardware trigger does not activate register sync.
screamer 0:e4d670b91a9a 1230 */
screamer 0:e4d670b91a9a 1231 static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1232 {
screamer 0:e4d670b91a9a 1233 BW_FTM_SYNCONF_HWINVC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1234 }
screamer 0:e4d670b91a9a 1235
screamer 0:e4d670b91a9a 1236 /*!
screamer 0:e4d670b91a9a 1237 * @brief Sets sync mode for FTM OUTMASK register when using a hardware trigger.
screamer 0:e4d670b91a9a 1238 *
screamer 0:e4d670b91a9a 1239 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1240 * @param enable true means hardware trigger activates register sync\n
screamer 0:e4d670b91a9a 1241 * false means hardware trigger does not activate register sync.
screamer 0:e4d670b91a9a 1242 */
screamer 0:e4d670b91a9a 1243 static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1244 {
screamer 0:e4d670b91a9a 1245 BW_FTM_SYNCONF_HWOM(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1246 }
screamer 0:e4d670b91a9a 1247
screamer 0:e4d670b91a9a 1248 /*!
screamer 0:e4d670b91a9a 1249 * @brief Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger.
screamer 0:e4d670b91a9a 1250 *
screamer 0:e4d670b91a9a 1251 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1252 * @param enable true means hardware trigger activates register sync\n
screamer 0:e4d670b91a9a 1253 * false means hardware trigger does not activate register sync.
screamer 0:e4d670b91a9a 1254 */
screamer 0:e4d670b91a9a 1255 static inline void FTM_HAL_SetModCntinCvHardwareSycnModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1256 {
screamer 0:e4d670b91a9a 1257 BW_FTM_SYNCONF_HWWRBUF(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1258 }
screamer 0:e4d670b91a9a 1259
screamer 0:e4d670b91a9a 1260 /*!
screamer 0:e4d670b91a9a 1261 * @brief Sets sync mode for FTM counter register when using a hardware trigger.
screamer 0:e4d670b91a9a 1262 *
screamer 0:e4d670b91a9a 1263 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1264 * @param enable true means hardware trigger activates register sync\n
screamer 0:e4d670b91a9a 1265 * false means hardware trigger does not activate register sync.
screamer 0:e4d670b91a9a 1266 */
screamer 0:e4d670b91a9a 1267 static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1268 {
screamer 0:e4d670b91a9a 1269 BW_FTM_SYNCONF_HWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1270 }
screamer 0:e4d670b91a9a 1271
screamer 0:e4d670b91a9a 1272 /*!
screamer 0:e4d670b91a9a 1273 * @brief Sets sync mode for FTM SWOCTRL register when using a software trigger.
screamer 0:e4d670b91a9a 1274 *
screamer 0:e4d670b91a9a 1275 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1276 * @param enable true means software trigger activates register sync\n
screamer 0:e4d670b91a9a 1277 * false means software trigger does not activate register sync.
screamer 0:e4d670b91a9a 1278 */
screamer 0:e4d670b91a9a 1279 static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1280 {
screamer 0:e4d670b91a9a 1281 BW_FTM_SYNCONF_SWSOC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1282 }
screamer 0:e4d670b91a9a 1283
screamer 0:e4d670b91a9a 1284 /*!
screamer 0:e4d670b91a9a 1285 * @brief Sets sync mode for FTM INVCTRL register when using a software trigger.
screamer 0:e4d670b91a9a 1286 *
screamer 0:e4d670b91a9a 1287 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1288 * @param enable true means software trigger activates register sync\n
screamer 0:e4d670b91a9a 1289 * false means software trigger does not activate register sync.
screamer 0:e4d670b91a9a 1290 */
screamer 0:e4d670b91a9a 1291 static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1292 {
screamer 0:e4d670b91a9a 1293 BW_FTM_SYNCONF_SWINVC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1294 }
screamer 0:e4d670b91a9a 1295
screamer 0:e4d670b91a9a 1296 /*!
screamer 0:e4d670b91a9a 1297 * @brief Sets sync mode for FTM OUTMASK register when using a software trigger.
screamer 0:e4d670b91a9a 1298 *
screamer 0:e4d670b91a9a 1299 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1300 * @param enable true means software trigger activates register sync\n
screamer 0:e4d670b91a9a 1301 * false means software trigger does not activate register sync.
screamer 0:e4d670b91a9a 1302 */
screamer 0:e4d670b91a9a 1303 static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1304 {
screamer 0:e4d670b91a9a 1305 BW_FTM_SYNCONF_SWOM(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1306 }
screamer 0:e4d670b91a9a 1307
screamer 0:e4d670b91a9a 1308 /*!
screamer 0:e4d670b91a9a 1309 * @brief Sets synch mode for FTM MOD, CNTIN and CV registers when using a software trigger.
screamer 0:e4d670b91a9a 1310 *
screamer 0:e4d670b91a9a 1311 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1312 * @param enable true means software trigger activates register sync\n
screamer 0:e4d670b91a9a 1313 * false means software trigger does not activate register sync.
screamer 0:e4d670b91a9a 1314 */
screamer 0:e4d670b91a9a 1315 static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1316 {
screamer 0:e4d670b91a9a 1317 BW_FTM_SYNCONF_SWWRBUF(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1318 }
screamer 0:e4d670b91a9a 1319
screamer 0:e4d670b91a9a 1320 /*!
screamer 0:e4d670b91a9a 1321 * @brief Sets sync mode for FTM counter register when using a software trigger.
screamer 0:e4d670b91a9a 1322 *
screamer 0:e4d670b91a9a 1323 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1324 * @param enable true means software trigger activates register sync\n
screamer 0:e4d670b91a9a 1325 * false means software trigger does not activate register sync.
screamer 0:e4d670b91a9a 1326 */
screamer 0:e4d670b91a9a 1327 static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1328 {
screamer 0:e4d670b91a9a 1329 BW_FTM_SYNCONF_SWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1330 }
screamer 0:e4d670b91a9a 1331
screamer 0:e4d670b91a9a 1332 /*!
screamer 0:e4d670b91a9a 1333 * @brief Sets the PWM synchronization mode to enhanced or legacy.
screamer 0:e4d670b91a9a 1334 *
screamer 0:e4d670b91a9a 1335 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1336 * @param enable true means use Enhanced PWM synchronization\n
screamer 0:e4d670b91a9a 1337 * false means to use Legacy mode
screamer 0:e4d670b91a9a 1338 */
screamer 0:e4d670b91a9a 1339 static inline void FTM_HAL_SetPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1340 {
screamer 0:e4d670b91a9a 1341 BW_FTM_SYNCONF_SYNCMODE(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1342 }
screamer 0:e4d670b91a9a 1343
screamer 0:e4d670b91a9a 1344 /*!
screamer 0:e4d670b91a9a 1345 * @brief Sets the SWOCTRL register PWM synchronization mode.
screamer 0:e4d670b91a9a 1346 *
screamer 0:e4d670b91a9a 1347 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1348 * @param enable true means SWOCTRL register is updated by PWM synch\n
screamer 0:e4d670b91a9a 1349 * false means SWOCTRL register is updated at all rising edges of system clock
screamer 0:e4d670b91a9a 1350 */
screamer 0:e4d670b91a9a 1351 static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1352 {
screamer 0:e4d670b91a9a 1353 BW_FTM_SYNCONF_SWOC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1354 }
screamer 0:e4d670b91a9a 1355
screamer 0:e4d670b91a9a 1356 /*!
screamer 0:e4d670b91a9a 1357 * @brief Sets the INVCTRL register PWM synchronization mode.
screamer 0:e4d670b91a9a 1358 *
screamer 0:e4d670b91a9a 1359 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1360 * @param enable true means INVCTRL register is updated by PWM synch\n
screamer 0:e4d670b91a9a 1361 * false means INVCTRL register is updated at all rising edges of system clock
screamer 0:e4d670b91a9a 1362 */
screamer 0:e4d670b91a9a 1363 static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1364 {
screamer 0:e4d670b91a9a 1365 BW_FTM_SYNCONF_INVC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1366 }
screamer 0:e4d670b91a9a 1367
screamer 0:e4d670b91a9a 1368 /*!
screamer 0:e4d670b91a9a 1369 * @brief Sets the CNTIN register PWM synchronization mode.
screamer 0:e4d670b91a9a 1370 *
screamer 0:e4d670b91a9a 1371 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1372 * @param enable true means CNTIN register is updated by PWM synch\n
screamer 0:e4d670b91a9a 1373 * false means CNTIN register is updated at all rising edges of system clock
screamer 0:e4d670b91a9a 1374 */
screamer 0:e4d670b91a9a 1375 static inline void FTM_HAL_SetCntinPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
screamer 0:e4d670b91a9a 1376 {
screamer 0:e4d670b91a9a 1377 BW_FTM_SYNCONF_CNTINC(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1378 }
screamer 0:e4d670b91a9a 1379
screamer 0:e4d670b91a9a 1380
screamer 0:e4d670b91a9a 1381 /*HAL functionality*/
screamer 0:e4d670b91a9a 1382 /*!
screamer 0:e4d670b91a9a 1383 * @brief Resets the FTM registers
screamer 0:e4d670b91a9a 1384 *
screamer 0:e4d670b91a9a 1385 * @param instance The FTM instance number
screamer 0:e4d670b91a9a 1386 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1387 */
screamer 0:e4d670b91a9a 1388 void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance);
screamer 0:e4d670b91a9a 1389
screamer 0:e4d670b91a9a 1390 /*!
screamer 0:e4d670b91a9a 1391 * @brief Initializes the FTM.
screamer 0:e4d670b91a9a 1392 *
screamer 0:e4d670b91a9a 1393 * @param ftmBaseAddr The FTM base address.
screamer 0:e4d670b91a9a 1394 */
screamer 0:e4d670b91a9a 1395 void FTM_HAL_Init(uint32_t ftmBaseAddr);
screamer 0:e4d670b91a9a 1396
screamer 0:e4d670b91a9a 1397 /*Initializes the 5 FTM operating mode, input capture, output compare, PWM output(edge aligned, center-aligned, conbine), dual and quadrature).*/
screamer 0:e4d670b91a9a 1398
screamer 0:e4d670b91a9a 1399 /*void FTM_HAL_input_capture_mode(uint32_t ftmBaseAddr);*/
screamer 0:e4d670b91a9a 1400 /*void FTM_HAL_output_compare_mode(uint32_t ftmBaseAddr);*/
screamer 0:e4d670b91a9a 1401
screamer 0:e4d670b91a9a 1402 /*!
screamer 0:e4d670b91a9a 1403 * @brief Enables the FTM timer when it is PWM output mode.
screamer 0:e4d670b91a9a 1404 *
screamer 0:e4d670b91a9a 1405 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1406 * @param config PWM configuration parameter
screamer 0:e4d670b91a9a 1407 * @param channel The channel or channel pair number(combined mode).
screamer 0:e4d670b91a9a 1408 */
screamer 0:e4d670b91a9a 1409 void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
screamer 0:e4d670b91a9a 1410
screamer 0:e4d670b91a9a 1411 /*!
screamer 0:e4d670b91a9a 1412 * @brief Disables the PWM output mode.
screamer 0:e4d670b91a9a 1413 *
screamer 0:e4d670b91a9a 1414 * @param ftmBaseAddr The FTM base address
screamer 0:e4d670b91a9a 1415 * @param config PWM configuration parameter
screamer 0:e4d670b91a9a 1416 * @param channel The channel or channel pair number(combined mode).
screamer 0:e4d670b91a9a 1417 */
screamer 0:e4d670b91a9a 1418 void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
screamer 0:e4d670b91a9a 1419
screamer 0:e4d670b91a9a 1420 /*void FTM_HAL_dual_mode(uint32_t ftmBaseAddr);*/
screamer 0:e4d670b91a9a 1421 /*void FTM_HAL_quad_mode(uint32_t ftmBaseAddr);*/
screamer 0:e4d670b91a9a 1422
screamer 0:e4d670b91a9a 1423
screamer 0:e4d670b91a9a 1424 /*void FTM_HAL_set_counting_mode(); //up, up down or free running counting mode*/
screamer 0:e4d670b91a9a 1425 /*void FTM_HAL_set_deadtime(uint32_t ftmBaseAddr, uint_32 us);*/
screamer 0:e4d670b91a9a 1426
screamer 0:e4d670b91a9a 1427 /*! @}*/
screamer 0:e4d670b91a9a 1428
screamer 0:e4d670b91a9a 1429 #endif /* __FSL_FTM_HAL_H__*/
screamer 0:e4d670b91a9a 1430 /*******************************************************************************
screamer 0:e4d670b91a9a 1431 * EOF
screamer 0:e4d670b91a9a 1432 ******************************************************************************/
screamer 0:e4d670b91a9a 1433