Andy K / SimpleIOMacros

Simple to use macros to manipulate GPIOs quickly.

Dependents:   revcounter FastStepDriver

IOMacros.h@0:a3a04e1ce9c2, 2010-10-29 (annotated)

Committer:
AjK
Date:
Fri Oct 29 23:31:21 2010 +0000
Revision:
0:a3a04e1ce9c2
Child:
1:cb1f38aaae0a
First release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 0:a3a04e1ce9c2 1 /*
AjK 0:a3a04e1ce9c2 2 Copyright (c) 2010 Andy Kirkham
AjK 0:a3a04e1ce9c2 3
AjK 0:a3a04e1ce9c2 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 0:a3a04e1ce9c2 5 of this software and associated documentation files (the "Software"), to deal
AjK 0:a3a04e1ce9c2 6 in the Software without restriction, including without limitation the rights
AjK 0:a3a04e1ce9c2 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 0:a3a04e1ce9c2 8 copies of the Software, and to permit persons to whom the Software is
AjK 0:a3a04e1ce9c2 9 furnished to do so, subject to the following conditions:
AjK 0:a3a04e1ce9c2 10
AjK 0:a3a04e1ce9c2 11 The above copyright notice and this permission notice shall be included in
AjK 0:a3a04e1ce9c2 12 all copies or substantial portions of the Software.
AjK 0:a3a04e1ce9c2 13
AjK 0:a3a04e1ce9c2 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 0:a3a04e1ce9c2 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 0:a3a04e1ce9c2 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 0:a3a04e1ce9c2 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 0:a3a04e1ce9c2 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 0:a3a04e1ce9c2 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 0:a3a04e1ce9c2 20 THE SOFTWARE.
AjK 0:a3a04e1ce9c2 21 */
AjK 0:a3a04e1ce9c2 22
AjK 0:a3a04e1ce9c2 23 #ifndef IOMACROS_H
AjK 0:a3a04e1ce9c2 24 #define IOMACROS_H
AjK 0:a3a04e1ce9c2 25
AjK 0:a3a04e1ce9c2 26 #ifndef __LPC17xx_H__
AjK 0:a3a04e1ce9c2 27 #include "LPC17xx.h"
AjK 0:a3a04e1ce9c2 28 #endif
AjK 0:a3a04e1ce9c2 29
AjK 0:a3a04e1ce9c2 30 #define PIN_PULLUP 0UL
AjK 0:a3a04e1ce9c2 31 #define PIN_REPEAT 1UL
AjK 0:a3a04e1ce9c2 32 #define PIN_NONE 2UL
AjK 0:a3a04e1ce9c2 33 #define PIN_PULLDOWN 3UL
AjK 0:a3a04e1ce9c2 34
AjK 0:a3a04e1ce9c2 35 /* p5 is P0.9 */
AjK 0:a3a04e1ce9c2 36 #define p5_SEL_MASK ~(3UL << 18)
AjK 0:a3a04e1ce9c2 37 #define p5_SET_MASK (1UL << 9)
AjK 0:a3a04e1ce9c2 38 #define p5_CLR_MASK ~(p5_SET_MASK)
AjK 0:a3a04e1ce9c2 39 #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK
AjK 0:a3a04e1ce9c2 40 #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK;
AjK 0:a3a04e1ce9c2 41 #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK
AjK 0:a3a04e1ce9c2 42 #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK
AjK 0:a3a04e1ce9c2 43 #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)
AjK 0:a3a04e1ce9c2 44 #define p5_IS_CLR !(p5_IS_SET)
AjK 0:a3a04e1ce9c2 45 #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)
AjK 0:a3a04e1ce9c2 46
AjK 0:a3a04e1ce9c2 47 /* p6 is P0.8 */
AjK 0:a3a04e1ce9c2 48 #define p6_SEL_MASK ~(3UL << 16)
AjK 0:a3a04e1ce9c2 49 #define p6_SET_MASK (1UL << 8)
AjK 0:a3a04e1ce9c2 50 #define p6_CLR_MASK ~(p6_SET_MASK)
AjK 0:a3a04e1ce9c2 51 #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK
AjK 0:a3a04e1ce9c2 52 #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK;
AjK 0:a3a04e1ce9c2 53 #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK
AjK 0:a3a04e1ce9c2 54 #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK
AjK 0:a3a04e1ce9c2 55 #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)
AjK 0:a3a04e1ce9c2 56 #define p6_IS_CLR !(p6_IS_SET)
AjK 0:a3a04e1ce9c2 57 #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16)
AjK 0:a3a04e1ce9c2 58
AjK 0:a3a04e1ce9c2 59 /* p7 is P0.7 */
AjK 0:a3a04e1ce9c2 60 #define p7_SEL_MASK ~(3UL << 14)
AjK 0:a3a04e1ce9c2 61 #define p7_SET_MASK (1UL << 7)
AjK 0:a3a04e1ce9c2 62 #define p7_CLR_MASK ~(p7_SET_MASK)
AjK 0:a3a04e1ce9c2 63 #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK
AjK 0:a3a04e1ce9c2 64 #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK;
AjK 0:a3a04e1ce9c2 65 #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK
AjK 0:a3a04e1ce9c2 66 #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK
AjK 0:a3a04e1ce9c2 67 #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)
AjK 0:a3a04e1ce9c2 68 #define p7_IS_CLR !(p7_IS_SET)
AjK 0:a3a04e1ce9c2 69 #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14)
AjK 0:a3a04e1ce9c2 70
AjK 0:a3a04e1ce9c2 71 /* p8 is P0.6 */
AjK 0:a3a04e1ce9c2 72 #define p8_SEL_MASK ~(3UL << 12)
AjK 0:a3a04e1ce9c2 73 #define p8_SET_MASK (1UL << 6)
AjK 0:a3a04e1ce9c2 74 #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK
AjK 0:a3a04e1ce9c2 75 #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK;
AjK 0:a3a04e1ce9c2 76 #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK
AjK 0:a3a04e1ce9c2 77 #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK
AjK 0:a3a04e1ce9c2 78 #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)
AjK 0:a3a04e1ce9c2 79 #define p8_IS_CLR !(p8_IS_SET)
AjK 0:a3a04e1ce9c2 80 #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12)
AjK 0:a3a04e1ce9c2 81
AjK 0:a3a04e1ce9c2 82 /* p9 is P0.0 */
AjK 0:a3a04e1ce9c2 83 #define p9_SEL_MASK ~(3UL << 0)
AjK 0:a3a04e1ce9c2 84 #define p9_SET_MASK (1UL << 0)
AjK 0:a3a04e1ce9c2 85 #define p9_CLR_MASK ~(p9_SET_MASK)
AjK 0:a3a04e1ce9c2 86 #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK
AjK 0:a3a04e1ce9c2 87 #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK;
AjK 0:a3a04e1ce9c2 88 #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK
AjK 0:a3a04e1ce9c2 89 #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK
AjK 0:a3a04e1ce9c2 90 #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)
AjK 0:a3a04e1ce9c2 91 #define p9_IS_CLR !(p9_IS_SET)
AjK 0:a3a04e1ce9c2 92 #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0)
AjK 0:a3a04e1ce9c2 93
AjK 0:a3a04e1ce9c2 94 /* p10 is P0.1 */
AjK 0:a3a04e1ce9c2 95 #define p10_SEL_MASK ~(3UL << 2)
AjK 0:a3a04e1ce9c2 96 #define p10_SET_MASK (1UL << 1)
AjK 0:a3a04e1ce9c2 97 #define p10_CLR_MASK ~(p10_SET_MASK)
AjK 0:a3a04e1ce9c2 98 #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK
AjK 0:a3a04e1ce9c2 99 #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK;
AjK 0:a3a04e1ce9c2 100 #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK
AjK 0:a3a04e1ce9c2 101 #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK
AjK 0:a3a04e1ce9c2 102 #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)
AjK 0:a3a04e1ce9c2 103 #define p10_IS_CLR !(p10_IS_SET)
AjK 0:a3a04e1ce9c2 104 #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)
AjK 0:a3a04e1ce9c2 105
AjK 0:a3a04e1ce9c2 106 /* p11 is P0.18 */
AjK 0:a3a04e1ce9c2 107 #define p11_SEL_MASK ~(3UL << 4)
AjK 0:a3a04e1ce9c2 108 #define p11_SET_MASK (1UL << 18)
AjK 0:a3a04e1ce9c2 109 #define p11_CLR_MASK ~(p11_SET_MASK)
AjK 0:a3a04e1ce9c2 110 #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK
AjK 0:a3a04e1ce9c2 111 #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK;
AjK 0:a3a04e1ce9c2 112 #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK
AjK 0:a3a04e1ce9c2 113 #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK
AjK 0:a3a04e1ce9c2 114 #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)
AjK 0:a3a04e1ce9c2 115 #define p11_IS_CLR !(p11_IS_SET)
AjK 0:a3a04e1ce9c2 116 #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)
AjK 0:a3a04e1ce9c2 117
AjK 0:a3a04e1ce9c2 118 /* p12 is P0.17 */
AjK 0:a3a04e1ce9c2 119 #define p12_SEL_MASK ~(3UL << 2)
AjK 0:a3a04e1ce9c2 120 #define p12_SET_MASK (1UL << 17)
AjK 0:a3a04e1ce9c2 121 #define p12_CLR_MASK ~(p12_SET_MASK)
AjK 0:a3a04e1ce9c2 122 #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK
AjK 0:a3a04e1ce9c2 123 #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK;
AjK 0:a3a04e1ce9c2 124 #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK
AjK 0:a3a04e1ce9c2 125 #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK
AjK 0:a3a04e1ce9c2 126 #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)
AjK 0:a3a04e1ce9c2 127 #define p12_IS_CLR !(p12_IS_SET)
AjK 0:a3a04e1ce9c2 128 #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)
AjK 0:a3a04e1ce9c2 129
AjK 0:a3a04e1ce9c2 130 /* p13 is P0.15 */
AjK 0:a3a04e1ce9c2 131 #define p13_SEL_MASK ~(3UL << 30)
AjK 0:a3a04e1ce9c2 132 #define p13_SET_MASK (1UL << 15)
AjK 0:a3a04e1ce9c2 133 #define p13_CLR_MASK ~(p13_SET_MASK)
AjK 0:a3a04e1ce9c2 134 #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK
AjK 0:a3a04e1ce9c2 135 #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK;
AjK 0:a3a04e1ce9c2 136 #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK
AjK 0:a3a04e1ce9c2 137 #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK
AjK 0:a3a04e1ce9c2 138 #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)
AjK 0:a3a04e1ce9c2 139 #define p13_IS_CLR !(p13_IS_SET)
AjK 0:a3a04e1ce9c2 140 #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)
AjK 0:a3a04e1ce9c2 141
AjK 0:a3a04e1ce9c2 142 /* p14 is P0.16 */
AjK 0:a3a04e1ce9c2 143 #define p14_SEL_MASK ~(3UL << 0)
AjK 0:a3a04e1ce9c2 144 #define p14_SET_MASK (1UL << 16)
AjK 0:a3a04e1ce9c2 145 #define p14_CLR_MASK ~(p14_SET_MASK)
AjK 0:a3a04e1ce9c2 146 #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK
AjK 0:a3a04e1ce9c2 147 #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK;
AjK 0:a3a04e1ce9c2 148 #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK
AjK 0:a3a04e1ce9c2 149 #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK
AjK 0:a3a04e1ce9c2 150 #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)
AjK 0:a3a04e1ce9c2 151 #define p14_IS_CLR !(p14_IS_SET)
AjK 0:a3a04e1ce9c2 152 #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)
AjK 0:a3a04e1ce9c2 153
AjK 0:a3a04e1ce9c2 154 /* p15 is P0.23 */
AjK 0:a3a04e1ce9c2 155 #define p15_SEL_MASK ~(3UL << 14)
AjK 0:a3a04e1ce9c2 156 #define p15_SET_MASK (1UL << 23)
AjK 0:a3a04e1ce9c2 157 #define p15_CLR_MASK ~(p15_SET_MASK)
AjK 0:a3a04e1ce9c2 158 #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK
AjK 0:a3a04e1ce9c2 159 #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK;
AjK 0:a3a04e1ce9c2 160 #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK
AjK 0:a3a04e1ce9c2 161 #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK
AjK 0:a3a04e1ce9c2 162 #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)
AjK 0:a3a04e1ce9c2 163 #define p15_IS_CLR !(p15_IS_SET)
AjK 0:a3a04e1ce9c2 164 #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)
AjK 0:a3a04e1ce9c2 165
AjK 0:a3a04e1ce9c2 166 /* p16 is P0.24 */
AjK 0:a3a04e1ce9c2 167 #define p16_SEL_MASK ~(3UL << 16)
AjK 0:a3a04e1ce9c2 168 #define p16_SET_MASK (1UL << 24)
AjK 0:a3a04e1ce9c2 169 #define p16_CLR_MASK ~(p16_SET_MASK)
AjK 0:a3a04e1ce9c2 170 #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK
AjK 0:a3a04e1ce9c2 171 #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK;
AjK 0:a3a04e1ce9c2 172 #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK
AjK 0:a3a04e1ce9c2 173 #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK
AjK 0:a3a04e1ce9c2 174 #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)
AjK 0:a3a04e1ce9c2 175 #define p16_IS_CLR !(p16_IS_SET)
AjK 0:a3a04e1ce9c2 176 #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)
AjK 0:a3a04e1ce9c2 177
AjK 0:a3a04e1ce9c2 178 /* p17 is P0.25 */
AjK 0:a3a04e1ce9c2 179 #define p17_SEL_MASK ~(3UL << 18)
AjK 0:a3a04e1ce9c2 180 #define p17_SET_MASK (1UL << 25)
AjK 0:a3a04e1ce9c2 181 #define p17_CLR_MASK ~(p17_SET_MASK)
AjK 0:a3a04e1ce9c2 182 #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK
AjK 0:a3a04e1ce9c2 183 #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK;
AjK 0:a3a04e1ce9c2 184 #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK
AjK 0:a3a04e1ce9c2 185 #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK
AjK 0:a3a04e1ce9c2 186 #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)
AjK 0:a3a04e1ce9c2 187 #define p17_IS_CLR !(p17_IS_SET)
AjK 0:a3a04e1ce9c2 188 #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)
AjK 0:a3a04e1ce9c2 189
AjK 0:a3a04e1ce9c2 190 /* p18 is P0.26 */
AjK 0:a3a04e1ce9c2 191 #define p18_SEL_MASK ~(3UL << 20)
AjK 0:a3a04e1ce9c2 192 #define p18_SET_MASK (1UL << 26)
AjK 0:a3a04e1ce9c2 193 #define p18_CLR_MASK ~(p18_SET_MASK)
AjK 0:a3a04e1ce9c2 194 #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK
AjK 0:a3a04e1ce9c2 195 #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK;
AjK 0:a3a04e1ce9c2 196 #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK
AjK 0:a3a04e1ce9c2 197 #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK
AjK 0:a3a04e1ce9c2 198 #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)
AjK 0:a3a04e1ce9c2 199 #define p18_IS_CLR !(p18_IS_SET)
AjK 0:a3a04e1ce9c2 200 #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)
AjK 0:a3a04e1ce9c2 201
AjK 0:a3a04e1ce9c2 202 /* p19 is P1.30 */
AjK 0:a3a04e1ce9c2 203 #define p19_SEL_MASK ~(3UL << 28)
AjK 0:a3a04e1ce9c2 204 #define p19_SET_MASK (1UL << 30)
AjK 0:a3a04e1ce9c2 205 #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK
AjK 0:a3a04e1ce9c2 206 #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK;
AjK 0:a3a04e1ce9c2 207 #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK
AjK 0:a3a04e1ce9c2 208 #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK
AjK 0:a3a04e1ce9c2 209 #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)
AjK 0:a3a04e1ce9c2 210 #define p19_IS_CLR !(p19_IS_SET)
AjK 0:a3a04e1ce9c2 211 #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)
AjK 0:a3a04e1ce9c2 212
AjK 0:a3a04e1ce9c2 213 /* p20 is P1.31 */
AjK 0:a3a04e1ce9c2 214 #define p20_SEL_MASK ~(3UL << 30)
AjK 0:a3a04e1ce9c2 215 #define p20_SET_MASK (1UL << 31)
AjK 0:a3a04e1ce9c2 216 #define p20_CLR_MASK ~(p20_SET_MASK)
AjK 0:a3a04e1ce9c2 217 #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK
AjK 0:a3a04e1ce9c2 218 #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK;
AjK 0:a3a04e1ce9c2 219 #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK
AjK 0:a3a04e1ce9c2 220 #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK
AjK 0:a3a04e1ce9c2 221 #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)
AjK 0:a3a04e1ce9c2 222 #define p20_IS_CLR !(p20_IS_SET)
AjK 0:a3a04e1ce9c2 223 #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)
AjK 0:a3a04e1ce9c2 224
AjK 0:a3a04e1ce9c2 225 /* p21 is P2.5 */
AjK 0:a3a04e1ce9c2 226 #define p21_SEL_MASK ~(3UL << 10)
AjK 0:a3a04e1ce9c2 227 #define p21_SET_MASK (1UL << 5)
AjK 0:a3a04e1ce9c2 228 #define p21_CLR_MASK ~(p21_SET_MASK)
AjK 0:a3a04e1ce9c2 229 #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK
AjK 0:a3a04e1ce9c2 230 #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK;
AjK 0:a3a04e1ce9c2 231 #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK
AjK 0:a3a04e1ce9c2 232 #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK
AjK 0:a3a04e1ce9c2 233 #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)
AjK 0:a3a04e1ce9c2 234 #define p21_IS_CLR !(p21_IS_SET)
AjK 0:a3a04e1ce9c2 235 #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)
AjK 0:a3a04e1ce9c2 236
AjK 0:a3a04e1ce9c2 237 /* p22 is P2.4 */
AjK 0:a3a04e1ce9c2 238 #define p22_SEL_MASK ~(3UL << 8)
AjK 0:a3a04e1ce9c2 239 #define p22_SET_MASK (1UL << 4)
AjK 0:a3a04e1ce9c2 240 #define p22_CLR_MASK ~(p22_SET_MASK)
AjK 0:a3a04e1ce9c2 241 #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK
AjK 0:a3a04e1ce9c2 242 #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK;
AjK 0:a3a04e1ce9c2 243 #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK
AjK 0:a3a04e1ce9c2 244 #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK
AjK 0:a3a04e1ce9c2 245 #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)
AjK 0:a3a04e1ce9c2 246 #define p22_IS_CLR !(p22_IS_SET)
AjK 0:a3a04e1ce9c2 247 #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)
AjK 0:a3a04e1ce9c2 248
AjK 0:a3a04e1ce9c2 249 /* p23 is P2.3 */
AjK 0:a3a04e1ce9c2 250 #define p23_SEL_MASK ~(3UL << 6)
AjK 0:a3a04e1ce9c2 251 #define p23_SET_MASK (1UL << 3)
AjK 0:a3a04e1ce9c2 252 #define p23_CLR_MASK ~(p23_SET_MASK)
AjK 0:a3a04e1ce9c2 253 #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK
AjK 0:a3a04e1ce9c2 254 #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK;
AjK 0:a3a04e1ce9c2 255 #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK
AjK 0:a3a04e1ce9c2 256 #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK
AjK 0:a3a04e1ce9c2 257 #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)
AjK 0:a3a04e1ce9c2 258 #define p23_IS_CLR !(p23_IS_SET)
AjK 0:a3a04e1ce9c2 259 #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)
AjK 0:a3a04e1ce9c2 260
AjK 0:a3a04e1ce9c2 261 /* p24 is P2.2 */
AjK 0:a3a04e1ce9c2 262 #define p24_SEL_MASK ~(3UL << 4)
AjK 0:a3a04e1ce9c2 263 #define p24_SET_MASK (1UL << 2)
AjK 0:a3a04e1ce9c2 264 #define p24_CLR_MASK ~(p24_SET_MASK)
AjK 0:a3a04e1ce9c2 265 #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK
AjK 0:a3a04e1ce9c2 266 #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK;
AjK 0:a3a04e1ce9c2 267 #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK
AjK 0:a3a04e1ce9c2 268 #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK
AjK 0:a3a04e1ce9c2 269 #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)
AjK 0:a3a04e1ce9c2 270 #define p24_IS_CLR !(p24_IS_SET)
AjK 0:a3a04e1ce9c2 271 #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)
AjK 0:a3a04e1ce9c2 272
AjK 0:a3a04e1ce9c2 273 /* p25 is P2.1 */
AjK 0:a3a04e1ce9c2 274 #define p25_SEL_MASK ~(3UL << 2)
AjK 0:a3a04e1ce9c2 275 #define p25_SET_MASK (1UL << 1)
AjK 0:a3a04e1ce9c2 276 #define p25_CLR_MASK ~(p25_SET_MASK)
AjK 0:a3a04e1ce9c2 277 #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK
AjK 0:a3a04e1ce9c2 278 #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK;
AjK 0:a3a04e1ce9c2 279 #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK
AjK 0:a3a04e1ce9c2 280 #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK
AjK 0:a3a04e1ce9c2 281 #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)
AjK 0:a3a04e1ce9c2 282 #define p25_IS_CLR !(p25_IS_SET)
AjK 0:a3a04e1ce9c2 283 #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)
AjK 0:a3a04e1ce9c2 284
AjK 0:a3a04e1ce9c2 285 /* p26 is P2.0 */
AjK 0:a3a04e1ce9c2 286 #define p26_SEL_MASK ~(3UL << 0)
AjK 0:a3a04e1ce9c2 287 #define p26_SET_MASK (1UL << 0)
AjK 0:a3a04e1ce9c2 288 #define p26_CLR_MASK ~(p26_SET_MASK)
AjK 0:a3a04e1ce9c2 289 #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK
AjK 0:a3a04e1ce9c2 290 #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK;
AjK 0:a3a04e1ce9c2 291 #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK
AjK 0:a3a04e1ce9c2 292 #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK
AjK 0:a3a04e1ce9c2 293 #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)
AjK 0:a3a04e1ce9c2 294 #define p26_IS_CLR !(p26_IS_SET)
AjK 0:a3a04e1ce9c2 295 #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)
AjK 0:a3a04e1ce9c2 296
AjK 0:a3a04e1ce9c2 297 /* p27 is P0.11 */
AjK 0:a3a04e1ce9c2 298 #define p27_SEL_MASK ~(3UL << 22)
AjK 0:a3a04e1ce9c2 299 #define p27_SET_MASK (1UL << 11)
AjK 0:a3a04e1ce9c2 300 #define p27_CLR_MASK ~(p27_SET_MASK)
AjK 0:a3a04e1ce9c2 301 #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK
AjK 0:a3a04e1ce9c2 302 #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK;
AjK 0:a3a04e1ce9c2 303 #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK
AjK 0:a3a04e1ce9c2 304 #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK
AjK 0:a3a04e1ce9c2 305 #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)
AjK 0:a3a04e1ce9c2 306 #define p27_IS_CLR !(p27_IS_SET)
AjK 0:a3a04e1ce9c2 307 #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)
AjK 0:a3a04e1ce9c2 308
AjK 0:a3a04e1ce9c2 309 /* p28 is P0.10 */
AjK 0:a3a04e1ce9c2 310 #define p28_SEL_MASK ~(3UL << 20)
AjK 0:a3a04e1ce9c2 311 #define p28_SET_MASK (1UL << 10)
AjK 0:a3a04e1ce9c2 312 #define p28_CLR_MASK ~(p28_SET_MASK)
AjK 0:a3a04e1ce9c2 313 #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK
AjK 0:a3a04e1ce9c2 314 #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK;
AjK 0:a3a04e1ce9c2 315 #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK
AjK 0:a3a04e1ce9c2 316 #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK
AjK 0:a3a04e1ce9c2 317 #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)
AjK 0:a3a04e1ce9c2 318 #define p28_IS_CLR !(p28_IS_SET)
AjK 0:a3a04e1ce9c2 319 #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)
AjK 0:a3a04e1ce9c2 320
AjK 0:a3a04e1ce9c2 321 /* p29 is P0.5 */
AjK 0:a3a04e1ce9c2 322 #define p29_SEL_MASK ~(3UL << 10)
AjK 0:a3a04e1ce9c2 323 #define p29_SET_MASK (1UL << 5)
AjK 0:a3a04e1ce9c2 324 #define p29_CLR_MASK ~(p29_SET_MASK)
AjK 0:a3a04e1ce9c2 325 #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK
AjK 0:a3a04e1ce9c2 326 #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK;
AjK 0:a3a04e1ce9c2 327 #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK
AjK 0:a3a04e1ce9c2 328 #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK
AjK 0:a3a04e1ce9c2 329 #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)
AjK 0:a3a04e1ce9c2 330 #define p29_IS_CLR !(p29_IS_SET)
AjK 0:a3a04e1ce9c2 331 #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)
AjK 0:a3a04e1ce9c2 332
AjK 0:a3a04e1ce9c2 333 /* p30 is P0.4 */
AjK 0:a3a04e1ce9c2 334 #define p30_SEL_MASK ~(3UL << 8)
AjK 0:a3a04e1ce9c2 335 #define p30_SET_MASK (1UL << 4)
AjK 0:a3a04e1ce9c2 336 #define p30_CLR_MASK ~(p30_SET_MASK)
AjK 0:a3a04e1ce9c2 337 #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK
AjK 0:a3a04e1ce9c2 338 #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK;
AjK 0:a3a04e1ce9c2 339 #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK
AjK 0:a3a04e1ce9c2 340 #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK
AjK 0:a3a04e1ce9c2 341 #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)
AjK 0:a3a04e1ce9c2 342 #define p30_IS_CLR !(p30_IS_SET)
AjK 0:a3a04e1ce9c2 343 #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)
AjK 0:a3a04e1ce9c2 344
AjK 0:a3a04e1ce9c2 345 /* The following definitions are for the four Mbed LEDs.
AjK 0:a3a04e1ce9c2 346 LED1 = P1.18
AjK 0:a3a04e1ce9c2 347 LED2 = P1.20
AjK 0:a3a04e1ce9c2 348 LED3 = P1.21
AjK 0:a3a04e1ce9c2 349 LED4 = P1.23 */
AjK 0:a3a04e1ce9c2 350
AjK 0:a3a04e1ce9c2 351 #define P1_18_SEL_MASK ~(3UL << 4)
AjK 0:a3a04e1ce9c2 352 #define P1_18_SET_MASK (1UL << 18)
AjK 0:a3a04e1ce9c2 353 #define P1_18_CLR_MASK ~(P1_18_SET_MASK)
AjK 0:a3a04e1ce9c2 354 #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK
AjK 0:a3a04e1ce9c2 355 #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK;
AjK 0:a3a04e1ce9c2 356 #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK
AjK 0:a3a04e1ce9c2 357 #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK
AjK 0:a3a04e1ce9c2 358 #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)
AjK 0:a3a04e1ce9c2 359 #define P1_18_IS_CLR !(P1_18_IS_SET)
AjK 0:a3a04e1ce9c2 360 #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT
AjK 0:a3a04e1ce9c2 361 #define LED1_ON P1_18_SET
AjK 0:a3a04e1ce9c2 362 #define LED1_OFF P1_18_CLR
AjK 0:a3a04e1ce9c2 363 #define LED1_IS_ON P1_18_IS_SET
AjK 0:a3a04e1ce9c2 364 #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON
AjK 0:a3a04e1ce9c2 365
AjK 0:a3a04e1ce9c2 366 #define P1_20_SEL_MASK ~(3UL << 8)
AjK 0:a3a04e1ce9c2 367 #define P1_20_SET_MASK (1UL << 20)
AjK 0:a3a04e1ce9c2 368 #define P1_20_CLR_MASK ~(P1_20_SET_MASK)
AjK 0:a3a04e1ce9c2 369 #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK
AjK 0:a3a04e1ce9c2 370 #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK;
AjK 0:a3a04e1ce9c2 371 #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK
AjK 0:a3a04e1ce9c2 372 #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK
AjK 0:a3a04e1ce9c2 373 #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)
AjK 0:a3a04e1ce9c2 374 #define P1_20_IS_CLR !(P1_20_IS_SET)
AjK 0:a3a04e1ce9c2 375 #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT
AjK 0:a3a04e1ce9c2 376 #define LED2_ON P1_20_SET
AjK 0:a3a04e1ce9c2 377 #define LED2_OFF P1_20_CLR
AjK 0:a3a04e1ce9c2 378 #define LED2_IS_ON P1_20_IS_SET
AjK 0:a3a04e1ce9c2 379 #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON
AjK 0:a3a04e1ce9c2 380
AjK 0:a3a04e1ce9c2 381 #define P1_21_SEL_MASK ~(3UL << 10)
AjK 0:a3a04e1ce9c2 382 #define P1_21_SET_MASK (1UL << 21)
AjK 0:a3a04e1ce9c2 383 #define P1_21_CLR_MASK ~(P1_21_SET_MASK)
AjK 0:a3a04e1ce9c2 384 #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK
AjK 0:a3a04e1ce9c2 385 #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK;
AjK 0:a3a04e1ce9c2 386 #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK
AjK 0:a3a04e1ce9c2 387 #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK
AjK 0:a3a04e1ce9c2 388 #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)
AjK 0:a3a04e1ce9c2 389 #define P1_21_IS_CLR !(P1_21_IS_SET)
AjK 0:a3a04e1ce9c2 390 #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT
AjK 0:a3a04e1ce9c2 391 #define LED3_ON P1_21_SET
AjK 0:a3a04e1ce9c2 392 #define LED3_OFF P1_21_CLR
AjK 0:a3a04e1ce9c2 393 #define LED3_IS_ON P1_21_IS_SET
AjK 0:a3a04e1ce9c2 394 #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON
AjK 0:a3a04e1ce9c2 395
AjK 0:a3a04e1ce9c2 396 #define P1_23_SEL_MASK ~(3UL << 14)
AjK 0:a3a04e1ce9c2 397 #define P1_23_SET_MASK (1UL << 23)
AjK 0:a3a04e1ce9c2 398 #define P1_23_CLR_MASK ~(P1_23_SET_MASK)
AjK 0:a3a04e1ce9c2 399 #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK
AjK 0:a3a04e1ce9c2 400 #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK;
AjK 0:a3a04e1ce9c2 401 #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK
AjK 0:a3a04e1ce9c2 402 #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK
AjK 0:a3a04e1ce9c2 403 #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)
AjK 0:a3a04e1ce9c2 404 #define P1_23_IS_CLR !(P1_23_IS_SET)
AjK 0:a3a04e1ce9c2 405 #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT
AjK 0:a3a04e1ce9c2 406 #define LED4_ON P1_23_SET
AjK 0:a3a04e1ce9c2 407 #define LED4_OFF P1_23_CLR
AjK 0:a3a04e1ce9c2 408 #define LED4_IS_ON P1_23_IS_SET
AjK 0:a3a04e1ce9c2 409 #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON
AjK 0:a3a04e1ce9c2 410
AjK 0:a3a04e1ce9c2 411 #endif
AjK 0:a3a04e1ce9c2 412