Andy K / Mbed 2 deprecated AD9951TEST

Attempt to read the AD9951 DSP serial output via SSP and \"IRQ driven bit-reading\".

iomacros.h@0:e45bbd4486df, 2011-01-18 (annotated)

Committer:
AjK
Date:
Tue Jan 18 01:27:57 2011 +0000
Revision:
0:e45bbd4486df
0.1 A test failure case!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 0:e45bbd4486df 1 /*
AjK 0:e45bbd4486df 2 Copyright (c) 2011 Andy Kirkham
AjK 0:e45bbd4486df 3
AjK 0:e45bbd4486df 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 0:e45bbd4486df 5 of this software and associated documentation files (the "Software"), to deal
AjK 0:e45bbd4486df 6 in the Software without restriction, including without limitation the rights
AjK 0:e45bbd4486df 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 0:e45bbd4486df 8 copies of the Software, and to permit persons to whom the Software is
AjK 0:e45bbd4486df 9 furnished to do so, subject to the following conditions:
AjK 0:e45bbd4486df 10
AjK 0:e45bbd4486df 11 The above copyright notice and this permission notice shall be included in
AjK 0:e45bbd4486df 12 all copies or substantial portions of the Software.
AjK 0:e45bbd4486df 13
AjK 0:e45bbd4486df 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 0:e45bbd4486df 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 0:e45bbd4486df 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 0:e45bbd4486df 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 0:e45bbd4486df 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 0:e45bbd4486df 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 0:e45bbd4486df 20 THE SOFTWARE.
AjK 0:e45bbd4486df 21 */
AjK 0:e45bbd4486df 22
AjK 0:e45bbd4486df 23 /* Andy's personal pin basher macro file, used mainly for debugging. */
AjK 0:e45bbd4486df 24
AjK 0:e45bbd4486df 25 #ifndef IOMACROS_H
AjK 0:e45bbd4486df 26 #define IOMACROS_H
AjK 0:e45bbd4486df 27
AjK 0:e45bbd4486df 28 #ifndef __LPC17xx_H__
AjK 0:e45bbd4486df 29 #include "LPC17xx.h"
AjK 0:e45bbd4486df 30 #endif
AjK 0:e45bbd4486df 31
AjK 0:e45bbd4486df 32 #define PIN_PULLUP 0UL
AjK 0:e45bbd4486df 33 #define PIN_REPEAT 1UL
AjK 0:e45bbd4486df 34 #define PIN_NONE 2UL
AjK 0:e45bbd4486df 35 #define PIN_PULLDOWN 3UL
AjK 0:e45bbd4486df 36
AjK 0:e45bbd4486df 37 /* p5 is P0.9 */
AjK 0:e45bbd4486df 38 #define p5_SEL_MASK ~(3UL << 18)
AjK 0:e45bbd4486df 39 #define p5_SET_MASK (1UL << 9)
AjK 0:e45bbd4486df 40 #define p5_CLR_MASK ~(p5_SET_MASK)
AjK 0:e45bbd4486df 41 #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK
AjK 0:e45bbd4486df 42 #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK;
AjK 0:e45bbd4486df 43 #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK
AjK 0:e45bbd4486df 44 #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK
AjK 0:e45bbd4486df 45 #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)
AjK 0:e45bbd4486df 46 #define p5_IS_CLR !(p5_IS_SET)
AjK 0:e45bbd4486df 47 #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)
AjK 0:e45bbd4486df 48
AjK 0:e45bbd4486df 49 /* p6 is P0.8 */
AjK 0:e45bbd4486df 50 #define p6_SEL_MASK ~(3UL << 16)
AjK 0:e45bbd4486df 51 #define p6_SET_MASK (1UL << 8)
AjK 0:e45bbd4486df 52 #define p6_CLR_MASK ~(p6_SET_MASK)
AjK 0:e45bbd4486df 53 #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK
AjK 0:e45bbd4486df 54 #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK;
AjK 0:e45bbd4486df 55 #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK
AjK 0:e45bbd4486df 56 #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK
AjK 0:e45bbd4486df 57 #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)
AjK 0:e45bbd4486df 58 #define p6_IS_CLR !(p6_IS_SET)
AjK 0:e45bbd4486df 59 #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16)
AjK 0:e45bbd4486df 60
AjK 0:e45bbd4486df 61 /* p7 is P0.7 */
AjK 0:e45bbd4486df 62 #define p7_SEL_MASK ~(3UL << 14)
AjK 0:e45bbd4486df 63 #define p7_SET_MASK (1UL << 7)
AjK 0:e45bbd4486df 64 #define p7_CLR_MASK ~(p7_SET_MASK)
AjK 0:e45bbd4486df 65 #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK
AjK 0:e45bbd4486df 66 #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK;
AjK 0:e45bbd4486df 67 #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK
AjK 0:e45bbd4486df 68 #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK
AjK 0:e45bbd4486df 69 #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)
AjK 0:e45bbd4486df 70 #define p7_IS_CLR !(p7_IS_SET)
AjK 0:e45bbd4486df 71 #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14)
AjK 0:e45bbd4486df 72
AjK 0:e45bbd4486df 73 /* p8 is P0.6 */
AjK 0:e45bbd4486df 74 #define p8_SEL_MASK ~(3UL << 12)
AjK 0:e45bbd4486df 75 #define p8_SET_MASK (1UL << 6)
AjK 0:e45bbd4486df 76 #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK
AjK 0:e45bbd4486df 77 #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK;
AjK 0:e45bbd4486df 78 #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK
AjK 0:e45bbd4486df 79 #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK
AjK 0:e45bbd4486df 80 #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)
AjK 0:e45bbd4486df 81 #define p8_IS_CLR !(p8_IS_SET)
AjK 0:e45bbd4486df 82 #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12)
AjK 0:e45bbd4486df 83
AjK 0:e45bbd4486df 84 /* p9 is P0.0 */
AjK 0:e45bbd4486df 85 #define p9_SEL_MASK ~(3UL << 0)
AjK 0:e45bbd4486df 86 #define p9_SET_MASK (1UL << 0)
AjK 0:e45bbd4486df 87 #define p9_CLR_MASK ~(p9_SET_MASK)
AjK 0:e45bbd4486df 88 #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK
AjK 0:e45bbd4486df 89 #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK;
AjK 0:e45bbd4486df 90 #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK
AjK 0:e45bbd4486df 91 #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK
AjK 0:e45bbd4486df 92 #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)
AjK 0:e45bbd4486df 93 #define p9_IS_CLR !(p9_IS_SET)
AjK 0:e45bbd4486df 94 #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0)
AjK 0:e45bbd4486df 95
AjK 0:e45bbd4486df 96 /* p10 is P0.1 */
AjK 0:e45bbd4486df 97 #define p10_SEL_MASK ~(3UL << 2)
AjK 0:e45bbd4486df 98 #define p10_SET_MASK (1UL << 1)
AjK 0:e45bbd4486df 99 #define p10_CLR_MASK ~(p10_SET_MASK)
AjK 0:e45bbd4486df 100 #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK
AjK 0:e45bbd4486df 101 #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK;
AjK 0:e45bbd4486df 102 #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK
AjK 0:e45bbd4486df 103 #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK
AjK 0:e45bbd4486df 104 #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)
AjK 0:e45bbd4486df 105 #define p10_IS_CLR !(p10_IS_SET)
AjK 0:e45bbd4486df 106 #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)
AjK 0:e45bbd4486df 107
AjK 0:e45bbd4486df 108 /* p11 is P0.18 */
AjK 0:e45bbd4486df 109 #define p11_SEL_MASK ~(3UL << 4)
AjK 0:e45bbd4486df 110 #define p11_SET_MASK (1UL << 18)
AjK 0:e45bbd4486df 111 #define p11_CLR_MASK ~(p11_SET_MASK)
AjK 0:e45bbd4486df 112 #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK
AjK 0:e45bbd4486df 113 #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK;
AjK 0:e45bbd4486df 114 #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK
AjK 0:e45bbd4486df 115 #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK
AjK 0:e45bbd4486df 116 #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)
AjK 0:e45bbd4486df 117 #define p11_IS_CLR !(p11_IS_SET)
AjK 0:e45bbd4486df 118 #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)
AjK 0:e45bbd4486df 119
AjK 0:e45bbd4486df 120 /* p12 is P0.17 */
AjK 0:e45bbd4486df 121 #define p12_SEL_MASK ~(3UL << 2)
AjK 0:e45bbd4486df 122 #define p12_SET_MASK (1UL << 17)
AjK 0:e45bbd4486df 123 #define p12_CLR_MASK ~(p12_SET_MASK)
AjK 0:e45bbd4486df 124 #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK
AjK 0:e45bbd4486df 125 #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK;
AjK 0:e45bbd4486df 126 #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK
AjK 0:e45bbd4486df 127 #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK
AjK 0:e45bbd4486df 128 #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)
AjK 0:e45bbd4486df 129 #define p12_IS_CLR !(p12_IS_SET)
AjK 0:e45bbd4486df 130 #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)
AjK 0:e45bbd4486df 131
AjK 0:e45bbd4486df 132 /* p13 is P0.15 */
AjK 0:e45bbd4486df 133 #define p13_SEL_MASK ~(3UL << 30)
AjK 0:e45bbd4486df 134 #define p13_SET_MASK (1UL << 15)
AjK 0:e45bbd4486df 135 #define p13_CLR_MASK ~(p13_SET_MASK)
AjK 0:e45bbd4486df 136 #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK
AjK 0:e45bbd4486df 137 #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK;
AjK 0:e45bbd4486df 138 #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK
AjK 0:e45bbd4486df 139 #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK
AjK 0:e45bbd4486df 140 #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)
AjK 0:e45bbd4486df 141 #define p13_IS_CLR !(p13_IS_SET)
AjK 0:e45bbd4486df 142 #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)
AjK 0:e45bbd4486df 143
AjK 0:e45bbd4486df 144 /* p14 is P0.16 */
AjK 0:e45bbd4486df 145 #define p14_SEL_MASK ~(3UL << 0)
AjK 0:e45bbd4486df 146 #define p14_SET_MASK (1UL << 16)
AjK 0:e45bbd4486df 147 #define p14_CLR_MASK ~(p14_SET_MASK)
AjK 0:e45bbd4486df 148 #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK
AjK 0:e45bbd4486df 149 #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK;
AjK 0:e45bbd4486df 150 #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK
AjK 0:e45bbd4486df 151 #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK
AjK 0:e45bbd4486df 152 #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)
AjK 0:e45bbd4486df 153 #define p14_IS_CLR !(p14_IS_SET)
AjK 0:e45bbd4486df 154 #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)
AjK 0:e45bbd4486df 155
AjK 0:e45bbd4486df 156 /* p15 is P0.23 */
AjK 0:e45bbd4486df 157 #define p15_SEL_MASK ~(3UL << 14)
AjK 0:e45bbd4486df 158 #define p15_SET_MASK (1UL << 23)
AjK 0:e45bbd4486df 159 #define p15_CLR_MASK ~(p15_SET_MASK)
AjK 0:e45bbd4486df 160 #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK
AjK 0:e45bbd4486df 161 #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK;
AjK 0:e45bbd4486df 162 #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK
AjK 0:e45bbd4486df 163 #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK
AjK 0:e45bbd4486df 164 #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)
AjK 0:e45bbd4486df 165 #define p15_IS_CLR !(p15_IS_SET)
AjK 0:e45bbd4486df 166 #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)
AjK 0:e45bbd4486df 167
AjK 0:e45bbd4486df 168 /* p16 is P0.24 */
AjK 0:e45bbd4486df 169 #define p16_SEL_MASK ~(3UL << 16)
AjK 0:e45bbd4486df 170 #define p16_SET_MASK (1UL << 24)
AjK 0:e45bbd4486df 171 #define p16_CLR_MASK ~(p16_SET_MASK)
AjK 0:e45bbd4486df 172 #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK
AjK 0:e45bbd4486df 173 #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK;
AjK 0:e45bbd4486df 174 #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK
AjK 0:e45bbd4486df 175 #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK
AjK 0:e45bbd4486df 176 #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)
AjK 0:e45bbd4486df 177 #define p16_IS_CLR !(p16_IS_SET)
AjK 0:e45bbd4486df 178 #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)
AjK 0:e45bbd4486df 179
AjK 0:e45bbd4486df 180 /* p17 is P0.25 */
AjK 0:e45bbd4486df 181 #define p17_SEL_MASK ~(3UL << 18)
AjK 0:e45bbd4486df 182 #define p17_SET_MASK (1UL << 25)
AjK 0:e45bbd4486df 183 #define p17_CLR_MASK ~(p17_SET_MASK)
AjK 0:e45bbd4486df 184 #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK
AjK 0:e45bbd4486df 185 #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK;
AjK 0:e45bbd4486df 186 #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK
AjK 0:e45bbd4486df 187 #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK
AjK 0:e45bbd4486df 188 #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)
AjK 0:e45bbd4486df 189 #define p17_IS_CLR !(p17_IS_SET)
AjK 0:e45bbd4486df 190 #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)
AjK 0:e45bbd4486df 191
AjK 0:e45bbd4486df 192 /* p18 is P0.26 */
AjK 0:e45bbd4486df 193 #define p18_SEL_MASK ~(3UL << 20)
AjK 0:e45bbd4486df 194 #define p18_SET_MASK (1UL << 26)
AjK 0:e45bbd4486df 195 #define p18_CLR_MASK ~(p18_SET_MASK)
AjK 0:e45bbd4486df 196 #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK
AjK 0:e45bbd4486df 197 #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK;
AjK 0:e45bbd4486df 198 #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK
AjK 0:e45bbd4486df 199 #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK
AjK 0:e45bbd4486df 200 #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)
AjK 0:e45bbd4486df 201 #define p18_IS_CLR !(p18_IS_SET)
AjK 0:e45bbd4486df 202 #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)
AjK 0:e45bbd4486df 203
AjK 0:e45bbd4486df 204 /* p19 is P1.30 */
AjK 0:e45bbd4486df 205 #define p19_SEL_MASK ~(3UL << 28)
AjK 0:e45bbd4486df 206 #define p19_SET_MASK (1UL << 30)
AjK 0:e45bbd4486df 207 #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK
AjK 0:e45bbd4486df 208 #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK;
AjK 0:e45bbd4486df 209 #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK
AjK 0:e45bbd4486df 210 #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK
AjK 0:e45bbd4486df 211 #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)
AjK 0:e45bbd4486df 212 #define p19_IS_CLR !(p19_IS_SET)
AjK 0:e45bbd4486df 213 #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)
AjK 0:e45bbd4486df 214
AjK 0:e45bbd4486df 215 /* p20 is P1.31 */
AjK 0:e45bbd4486df 216 #define p20_SEL_MASK ~(3UL << 30)
AjK 0:e45bbd4486df 217 #define p20_SET_MASK (1UL << 31)
AjK 0:e45bbd4486df 218 #define p20_CLR_MASK ~(p20_SET_MASK)
AjK 0:e45bbd4486df 219 #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK
AjK 0:e45bbd4486df 220 #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK;
AjK 0:e45bbd4486df 221 #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK
AjK 0:e45bbd4486df 222 #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK
AjK 0:e45bbd4486df 223 #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)
AjK 0:e45bbd4486df 224 #define p20_IS_CLR !(p20_IS_SET)
AjK 0:e45bbd4486df 225 #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)
AjK 0:e45bbd4486df 226
AjK 0:e45bbd4486df 227 /* p21 is P2.5 */
AjK 0:e45bbd4486df 228 #define p21_SEL_MASK ~(3UL << 10)
AjK 0:e45bbd4486df 229 #define p21_SET_MASK (1UL << 5)
AjK 0:e45bbd4486df 230 #define p21_CLR_MASK ~(p21_SET_MASK)
AjK 0:e45bbd4486df 231 #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK
AjK 0:e45bbd4486df 232 #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK;
AjK 0:e45bbd4486df 233 #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK
AjK 0:e45bbd4486df 234 #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK
AjK 0:e45bbd4486df 235 #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)
AjK 0:e45bbd4486df 236 #define p21_IS_CLR !(p21_IS_SET)
AjK 0:e45bbd4486df 237 #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET
AjK 0:e45bbd4486df 238 #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)
AjK 0:e45bbd4486df 239
AjK 0:e45bbd4486df 240 /* p22 is P2.4 */
AjK 0:e45bbd4486df 241 #define p22_SEL_MASK ~(3UL << 8)
AjK 0:e45bbd4486df 242 #define p22_SET_MASK (1UL << 4)
AjK 0:e45bbd4486df 243 #define p22_CLR_MASK ~(p22_SET_MASK)
AjK 0:e45bbd4486df 244 #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK
AjK 0:e45bbd4486df 245 #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK;
AjK 0:e45bbd4486df 246 #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK
AjK 0:e45bbd4486df 247 #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK
AjK 0:e45bbd4486df 248 #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)
AjK 0:e45bbd4486df 249 #define p22_IS_CLR !(p22_IS_SET)
AjK 0:e45bbd4486df 250 #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET
AjK 0:e45bbd4486df 251 #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)
AjK 0:e45bbd4486df 252
AjK 0:e45bbd4486df 253 /* p23 is P2.3 */
AjK 0:e45bbd4486df 254 #define p23_SEL_MASK ~(3UL << 6)
AjK 0:e45bbd4486df 255 #define p23_SET_MASK (1UL << 3)
AjK 0:e45bbd4486df 256 #define p23_CLR_MASK ~(p23_SET_MASK)
AjK 0:e45bbd4486df 257 #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK
AjK 0:e45bbd4486df 258 #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK;
AjK 0:e45bbd4486df 259 #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK
AjK 0:e45bbd4486df 260 #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK
AjK 0:e45bbd4486df 261 #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)
AjK 0:e45bbd4486df 262 #define p23_IS_CLR !(p23_IS_SET)
AjK 0:e45bbd4486df 263 #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET
AjK 0:e45bbd4486df 264 #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)
AjK 0:e45bbd4486df 265
AjK 0:e45bbd4486df 266 /* p24 is P2.2 */
AjK 0:e45bbd4486df 267 #define p24_SEL_MASK ~(3UL << 4)
AjK 0:e45bbd4486df 268 #define p24_SET_MASK (1UL << 2)
AjK 0:e45bbd4486df 269 #define p24_CLR_MASK ~(p24_SET_MASK)
AjK 0:e45bbd4486df 270 #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK
AjK 0:e45bbd4486df 271 #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK;
AjK 0:e45bbd4486df 272 #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK
AjK 0:e45bbd4486df 273 #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK
AjK 0:e45bbd4486df 274 #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)
AjK 0:e45bbd4486df 275 #define p24_IS_CLR !(p24_IS_SET)
AjK 0:e45bbd4486df 276 #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET
AjK 0:e45bbd4486df 277 #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)
AjK 0:e45bbd4486df 278
AjK 0:e45bbd4486df 279 /* p25 is P2.1 */
AjK 0:e45bbd4486df 280 #define p25_SEL_MASK ~(3UL << 2)
AjK 0:e45bbd4486df 281 #define p25_SET_MASK (1UL << 1)
AjK 0:e45bbd4486df 282 #define p25_CLR_MASK ~(p25_SET_MASK)
AjK 0:e45bbd4486df 283 #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK
AjK 0:e45bbd4486df 284 #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK;
AjK 0:e45bbd4486df 285 #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK
AjK 0:e45bbd4486df 286 #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK
AjK 0:e45bbd4486df 287 #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)
AjK 0:e45bbd4486df 288 #define p25_IS_CLR !(p25_IS_SET)
AjK 0:e45bbd4486df 289 #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)
AjK 0:e45bbd4486df 290
AjK 0:e45bbd4486df 291 /* p26 is P2.0 */
AjK 0:e45bbd4486df 292 #define p26_SEL_MASK ~(3UL << 0)
AjK 0:e45bbd4486df 293 #define p26_SET_MASK (1UL << 0)
AjK 0:e45bbd4486df 294 #define p26_CLR_MASK ~(p26_SET_MASK)
AjK 0:e45bbd4486df 295 #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK
AjK 0:e45bbd4486df 296 #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK;
AjK 0:e45bbd4486df 297 #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK
AjK 0:e45bbd4486df 298 #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK
AjK 0:e45bbd4486df 299 #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)
AjK 0:e45bbd4486df 300 #define p26_IS_CLR !(p26_IS_SET)
AjK 0:e45bbd4486df 301 #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)
AjK 0:e45bbd4486df 302
AjK 0:e45bbd4486df 303 /* p27 is P0.11 */
AjK 0:e45bbd4486df 304 #define p27_SEL_MASK ~(3UL << 22)
AjK 0:e45bbd4486df 305 #define p27_SET_MASK (1UL << 11)
AjK 0:e45bbd4486df 306 #define p27_CLR_MASK ~(p27_SET_MASK)
AjK 0:e45bbd4486df 307 #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK
AjK 0:e45bbd4486df 308 #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK;
AjK 0:e45bbd4486df 309 #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK
AjK 0:e45bbd4486df 310 #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK
AjK 0:e45bbd4486df 311 #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)
AjK 0:e45bbd4486df 312 #define p27_IS_CLR !(p27_IS_SET)
AjK 0:e45bbd4486df 313 #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)
AjK 0:e45bbd4486df 314
AjK 0:e45bbd4486df 315 /* p28 is P0.10 */
AjK 0:e45bbd4486df 316 #define p28_SEL_MASK ~(3UL << 20)
AjK 0:e45bbd4486df 317 #define p28_SET_MASK (1UL << 10)
AjK 0:e45bbd4486df 318 #define p28_CLR_MASK ~(p28_SET_MASK)
AjK 0:e45bbd4486df 319 #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK
AjK 0:e45bbd4486df 320 #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK;
AjK 0:e45bbd4486df 321 #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK
AjK 0:e45bbd4486df 322 #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK
AjK 0:e45bbd4486df 323 #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)
AjK 0:e45bbd4486df 324 #define p28_IS_CLR !(p28_IS_SET)
AjK 0:e45bbd4486df 325 #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)
AjK 0:e45bbd4486df 326
AjK 0:e45bbd4486df 327 /* p29 is P0.5 */
AjK 0:e45bbd4486df 328 #define p29_SEL_MASK ~(3UL << 10)
AjK 0:e45bbd4486df 329 #define p29_SET_MASK (1UL << 5)
AjK 0:e45bbd4486df 330 #define p29_CLR_MASK ~(p29_SET_MASK)
AjK 0:e45bbd4486df 331 #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK
AjK 0:e45bbd4486df 332 #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK;
AjK 0:e45bbd4486df 333 #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK
AjK 0:e45bbd4486df 334 #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK
AjK 0:e45bbd4486df 335 #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)
AjK 0:e45bbd4486df 336 #define p29_IS_CLR !(p29_IS_SET)
AjK 0:e45bbd4486df 337 #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET
AjK 0:e45bbd4486df 338 #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)
AjK 0:e45bbd4486df 339
AjK 0:e45bbd4486df 340 /* p30 is P0.4 */
AjK 0:e45bbd4486df 341 #define p30_SEL_MASK ~(3UL << 8)
AjK 0:e45bbd4486df 342 #define p30_SET_MASK (1UL << 4)
AjK 0:e45bbd4486df 343 #define p30_CLR_MASK ~(p30_SET_MASK)
AjK 0:e45bbd4486df 344 #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK
AjK 0:e45bbd4486df 345 #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK;
AjK 0:e45bbd4486df 346 #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK
AjK 0:e45bbd4486df 347 #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK
AjK 0:e45bbd4486df 348 #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)
AjK 0:e45bbd4486df 349 #define p30_IS_CLR !(p30_IS_SET)
AjK 0:e45bbd4486df 350 #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)
AjK 0:e45bbd4486df 351
AjK 0:e45bbd4486df 352 /* The following definitions are for the four Mbed LEDs.
AjK 0:e45bbd4486df 353 LED1 = P1.18
AjK 0:e45bbd4486df 354 LED2 = P1.20
AjK 0:e45bbd4486df 355 LED3 = P1.21
AjK 0:e45bbd4486df 356 LED4 = P1.23 */
AjK 0:e45bbd4486df 357
AjK 0:e45bbd4486df 358 #define P1_18_SEL_MASK ~(3UL << 4)
AjK 0:e45bbd4486df 359 #define P1_18_SET_MASK (1UL << 18)
AjK 0:e45bbd4486df 360 #define P1_18_CLR_MASK ~(P1_18_SET_MASK)
AjK 0:e45bbd4486df 361 #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK
AjK 0:e45bbd4486df 362 #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK;
AjK 0:e45bbd4486df 363 #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK
AjK 0:e45bbd4486df 364 #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK
AjK 0:e45bbd4486df 365 #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)
AjK 0:e45bbd4486df 366 #define P1_18_IS_CLR !(P1_18_IS_SET)
AjK 0:e45bbd4486df 367 #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT
AjK 0:e45bbd4486df 368 #define LED1_ON P1_18_SET
AjK 0:e45bbd4486df 369 #define LED1_OFF P1_18_CLR
AjK 0:e45bbd4486df 370 #define LED1_IS_ON P1_18_IS_SET
AjK 0:e45bbd4486df 371 #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON
AjK 0:e45bbd4486df 372
AjK 0:e45bbd4486df 373 #define P1_20_SEL_MASK ~(3UL << 8)
AjK 0:e45bbd4486df 374 #define P1_20_SET_MASK (1UL << 20)
AjK 0:e45bbd4486df 375 #define P1_20_CLR_MASK ~(P1_20_SET_MASK)
AjK 0:e45bbd4486df 376 #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK
AjK 0:e45bbd4486df 377 #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK;
AjK 0:e45bbd4486df 378 #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK
AjK 0:e45bbd4486df 379 #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK
AjK 0:e45bbd4486df 380 #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)
AjK 0:e45bbd4486df 381 #define P1_20_IS_CLR !(P1_20_IS_SET)
AjK 0:e45bbd4486df 382 #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT
AjK 0:e45bbd4486df 383 #define LED2_ON P1_20_SET
AjK 0:e45bbd4486df 384 #define LED2_OFF P1_20_CLR
AjK 0:e45bbd4486df 385 #define LED2_IS_ON P1_20_IS_SET
AjK 0:e45bbd4486df 386 #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON
AjK 0:e45bbd4486df 387
AjK 0:e45bbd4486df 388 #define P1_21_SEL_MASK ~(3UL << 10)
AjK 0:e45bbd4486df 389 #define P1_21_SET_MASK (1UL << 21)
AjK 0:e45bbd4486df 390 #define P1_21_CLR_MASK ~(P1_21_SET_MASK)
AjK 0:e45bbd4486df 391 #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK
AjK 0:e45bbd4486df 392 #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK;
AjK 0:e45bbd4486df 393 #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK
AjK 0:e45bbd4486df 394 #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK
AjK 0:e45bbd4486df 395 #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)
AjK 0:e45bbd4486df 396 #define P1_21_IS_CLR !(P1_21_IS_SET)
AjK 0:e45bbd4486df 397 #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT
AjK 0:e45bbd4486df 398 #define LED3_ON P1_21_SET
AjK 0:e45bbd4486df 399 #define LED3_OFF P1_21_CLR
AjK 0:e45bbd4486df 400 #define LED3_IS_ON P1_21_IS_SET
AjK 0:e45bbd4486df 401 #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON
AjK 0:e45bbd4486df 402
AjK 0:e45bbd4486df 403 #define P1_23_SEL_MASK ~(3UL << 14)
AjK 0:e45bbd4486df 404 #define P1_23_SET_MASK (1UL << 23)
AjK 0:e45bbd4486df 405 #define P1_23_CLR_MASK ~(P1_23_SET_MASK)
AjK 0:e45bbd4486df 406 #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK
AjK 0:e45bbd4486df 407 #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK;
AjK 0:e45bbd4486df 408 #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK
AjK 0:e45bbd4486df 409 #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK
AjK 0:e45bbd4486df 410 #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)
AjK 0:e45bbd4486df 411 #define P1_23_IS_CLR !(P1_23_IS_SET)
AjK 0:e45bbd4486df 412 #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT
AjK 0:e45bbd4486df 413 #define LED4_ON P1_23_SET
AjK 0:e45bbd4486df 414 #define LED4_OFF P1_23_CLR
AjK 0:e45bbd4486df 415 #define LED4_IS_ON P1_23_IS_SET
AjK 0:e45bbd4486df 416 #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON
AjK 0:e45bbd4486df 417
AjK 0:e45bbd4486df 418 #endif
AjK 0:e45bbd4486df 419