Adam Green / EthernetInterface

Deprecated fork of old network stack source from github. Please use official library instead: https://mbed.org/users/mbed_official/code/EthernetInterface/

lwip-eth/arch/lpc17xx_emac.h@1:eadc868c2acf, 2013-10-26 (annotated)

Committer:
AdamGreen
Date:
Sat Oct 26 08:51:36 2013 +0000
Revision:
1:eadc868c2acf
Parent:
0:3b00827bb0b7 
Fix TCP checksum bug and stranded large TCP segments.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AdamGreen 0:3b00827bb0b7 1 /**********************************************************************
AdamGreen 0:3b00827bb0b7 2 * $Id$ lpc17xx_emac.h 2010-05-21
AdamGreen 0:3b00827bb0b7 3 *//**
AdamGreen 0:3b00827bb0b7 4 * @file lpc17xx_emac.h
AdamGreen 0:3b00827bb0b7 5 * @brief Contains all macro definitions and function prototypes
AdamGreen 0:3b00827bb0b7 6 * support for Ethernet MAC firmware library on LPC17xx
AdamGreen 0:3b00827bb0b7 7 * @version 2.0
AdamGreen 0:3b00827bb0b7 8 * @date 21. May. 2010
AdamGreen 0:3b00827bb0b7 9 * @author NXP MCU SW Application Team
AdamGreen 0:3b00827bb0b7 10 *
AdamGreen 0:3b00827bb0b7 11 * Copyright(C) 2010, NXP Semiconductor
AdamGreen 0:3b00827bb0b7 12 * All rights reserved.
AdamGreen 0:3b00827bb0b7 13 *
AdamGreen 0:3b00827bb0b7 14 ***********************************************************************
AdamGreen 0:3b00827bb0b7 15 * Software that is described herein is for illustrative purposes only
AdamGreen 0:3b00827bb0b7 16 * which provides customers with programming information regarding the
AdamGreen 0:3b00827bb0b7 17 * products. This software is supplied "AS IS" without any warranties.
AdamGreen 0:3b00827bb0b7 18 * NXP Semiconductors assumes no responsibility or liability for the
AdamGreen 0:3b00827bb0b7 19 * use of the software, conveys no license or title under any patent,
AdamGreen 0:3b00827bb0b7 20 * copyright, or mask work right to the product. NXP Semiconductors
AdamGreen 0:3b00827bb0b7 21 * reserves the right to make changes in the software without
AdamGreen 0:3b00827bb0b7 22 * notification. NXP Semiconductors also make no representation or
AdamGreen 0:3b00827bb0b7 23 * warranty that such application will be suitable for the specified
AdamGreen 0:3b00827bb0b7 24 * use without further testing or modification.
AdamGreen 0:3b00827bb0b7 25 **********************************************************************/
AdamGreen 0:3b00827bb0b7 26
AdamGreen 0:3b00827bb0b7 27 /* Peripheral group ----------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
AdamGreen 0:3b00827bb0b7 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
AdamGreen 0:3b00827bb0b7 30 * @{
AdamGreen 0:3b00827bb0b7 31 */
AdamGreen 0:3b00827bb0b7 32
AdamGreen 0:3b00827bb0b7 33 #ifndef LPC17XX_EMAC_H_
AdamGreen 0:3b00827bb0b7 34 #define LPC17XX_EMAC_H_
AdamGreen 0:3b00827bb0b7 35
AdamGreen 0:3b00827bb0b7 36 /* Includes ------------------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 37 #include "cmsis.h"
AdamGreen 0:3b00827bb0b7 38
AdamGreen 0:3b00827bb0b7 39 #ifdef __cplusplus
AdamGreen 0:3b00827bb0b7 40 extern "C"
AdamGreen 0:3b00827bb0b7 41 {
AdamGreen 0:3b00827bb0b7 42 #endif
AdamGreen 0:3b00827bb0b7 43
AdamGreen 0:3b00827bb0b7 44 #define MCB_LPC_1768
AdamGreen 0:3b00827bb0b7 45 //#define IAR_LPC_1768
AdamGreen 0:3b00827bb0b7 46
AdamGreen 0:3b00827bb0b7 47 /* Public Macros -------------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
AdamGreen 0:3b00827bb0b7 49 * @{
AdamGreen 0:3b00827bb0b7 50 */
AdamGreen 0:3b00827bb0b7 51
AdamGreen 0:3b00827bb0b7 52
AdamGreen 0:3b00827bb0b7 53 /* EMAC PHY status type definitions */
AdamGreen 0:3b00827bb0b7 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
AdamGreen 0:3b00827bb0b7 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
AdamGreen 0:3b00827bb0b7 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
AdamGreen 0:3b00827bb0b7 57
AdamGreen 0:3b00827bb0b7 58 /* EMAC PHY device Speed definitions */
AdamGreen 0:3b00827bb0b7 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
AdamGreen 0:3b00827bb0b7 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
AdamGreen 0:3b00827bb0b7 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
AdamGreen 0:3b00827bb0b7 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
AdamGreen 0:3b00827bb0b7 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
AdamGreen 0:3b00827bb0b7 64
AdamGreen 0:3b00827bb0b7 65 /**
AdamGreen 0:3b00827bb0b7 66 * @}
AdamGreen 0:3b00827bb0b7 67 */
AdamGreen 0:3b00827bb0b7 68 /* Private Macros ------------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
AdamGreen 0:3b00827bb0b7 70 * @{
AdamGreen 0:3b00827bb0b7 71 */
AdamGreen 0:3b00827bb0b7 72
AdamGreen 0:3b00827bb0b7 73
AdamGreen 0:3b00827bb0b7 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
AdamGreen 0:3b00827bb0b7 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
AdamGreen 0:3b00827bb0b7 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
AdamGreen 0:3b00827bb0b7 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
AdamGreen 0:3b00827bb0b7 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
AdamGreen 0:3b00827bb0b7 79
AdamGreen 0:3b00827bb0b7 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
AdamGreen 0:3b00827bb0b7 81 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 82 * Macro defines for MAC Configuration Register 1
AdamGreen 0:3b00827bb0b7 83 **********************************************************************/
AdamGreen 0:3b00827bb0b7 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
AdamGreen 0:3b00827bb0b7 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
AdamGreen 0:3b00827bb0b7 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
AdamGreen 0:3b00827bb0b7 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
AdamGreen 0:3b00827bb0b7 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
AdamGreen 0:3b00827bb0b7 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
AdamGreen 0:3b00827bb0b7 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
AdamGreen 0:3b00827bb0b7 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
AdamGreen 0:3b00827bb0b7 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
AdamGreen 0:3b00827bb0b7 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
AdamGreen 0:3b00827bb0b7 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
AdamGreen 0:3b00827bb0b7 95
AdamGreen 0:3b00827bb0b7 96 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 97 * Macro defines for MAC Configuration Register 2
AdamGreen 0:3b00827bb0b7 98 **********************************************************************/
AdamGreen 0:3b00827bb0b7 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
AdamGreen 0:3b00827bb0b7 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
AdamGreen 0:3b00827bb0b7 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
AdamGreen 0:3b00827bb0b7 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
AdamGreen 0:3b00827bb0b7 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
AdamGreen 0:3b00827bb0b7 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
AdamGreen 0:3b00827bb0b7 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
AdamGreen 0:3b00827bb0b7 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
AdamGreen 0:3b00827bb0b7 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
AdamGreen 0:3b00827bb0b7 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
AdamGreen 0:3b00827bb0b7 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
AdamGreen 0:3b00827bb0b7 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
AdamGreen 0:3b00827bb0b7 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
AdamGreen 0:3b00827bb0b7 112
AdamGreen 0:3b00827bb0b7 113 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
AdamGreen 0:3b00827bb0b7 115 **********************************************************************/
AdamGreen 0:3b00827bb0b7 116 /** Programmable field representing the nibble time offset of the minimum possible period
AdamGreen 0:3b00827bb0b7 117 * between the end of any transmitted packet to the beginning of the next */
AdamGreen 0:3b00827bb0b7 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
AdamGreen 0:3b00827bb0b7 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
AdamGreen 0:3b00827bb0b7 120 * offset of the minimum possible period between the end of any transmitted packet to the
AdamGreen 0:3b00827bb0b7 121 * beginning of the next */
AdamGreen 0:3b00827bb0b7 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
AdamGreen 0:3b00827bb0b7 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
AdamGreen 0:3b00827bb0b7 124 * offset of the minimum possible period between the end of any transmitted packet to the
AdamGreen 0:3b00827bb0b7 125 * beginning of the next */
AdamGreen 0:3b00827bb0b7 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
AdamGreen 0:3b00827bb0b7 127
AdamGreen 0:3b00827bb0b7 128 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
AdamGreen 0:3b00827bb0b7 130 **********************************************************************/
AdamGreen 0:3b00827bb0b7 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
AdamGreen 0:3b00827bb0b7 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
AdamGreen 0:3b00827bb0b7 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
AdamGreen 0:3b00827bb0b7 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
AdamGreen 0:3b00827bb0b7 135 /** Programmable field representing the optional carrierSense window referenced in
AdamGreen 0:3b00827bb0b7 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
AdamGreen 0:3b00827bb0b7 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
AdamGreen 0:3b00827bb0b7 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
AdamGreen 0:3b00827bb0b7 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
AdamGreen 0:3b00827bb0b7 140
AdamGreen 0:3b00827bb0b7 141 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 142 * Macro defines for Collision Window/Retry Register
AdamGreen 0:3b00827bb0b7 143 **********************************************************************/
AdamGreen 0:3b00827bb0b7 144 /** Programmable field specifying the number of retransmission attempts following a collision before
AdamGreen 0:3b00827bb0b7 145 * aborting the packet due to excessive collisions */
AdamGreen 0:3b00827bb0b7 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
AdamGreen 0:3b00827bb0b7 147 /** Programmable field representing the slot time or collision window during which collisions occur
AdamGreen 0:3b00827bb0b7 148 * in properly configured networks */
AdamGreen 0:3b00827bb0b7 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
AdamGreen 0:3b00827bb0b7 150 /** Default value for Collision Window / Retry register */
AdamGreen 0:3b00827bb0b7 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
AdamGreen 0:3b00827bb0b7 152
AdamGreen 0:3b00827bb0b7 153 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 154 * Macro defines for Maximum Frame Register
AdamGreen 0:3b00827bb0b7 155 **********************************************************************/
AdamGreen 0:3b00827bb0b7 156 /** Represents a maximum receive frame of 1536 octets */
AdamGreen 0:3b00827bb0b7 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
AdamGreen 0:3b00827bb0b7 158
AdamGreen 0:3b00827bb0b7 159 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 160 * Macro defines for PHY Support Register
AdamGreen 0:3b00827bb0b7 161 **********************************************************************/
AdamGreen 0:3b00827bb0b7 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
AdamGreen 0:3b00827bb0b7 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
AdamGreen 0:3b00827bb0b7 164
AdamGreen 0:3b00827bb0b7 165 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 166 * Macro defines for Test Register
AdamGreen 0:3b00827bb0b7 167 **********************************************************************/
AdamGreen 0:3b00827bb0b7 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
AdamGreen 0:3b00827bb0b7 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
AdamGreen 0:3b00827bb0b7 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
AdamGreen 0:3b00827bb0b7 171
AdamGreen 0:3b00827bb0b7 172 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 173 * Macro defines for MII Management Configuration Register
AdamGreen 0:3b00827bb0b7 174 **********************************************************************/
AdamGreen 0:3b00827bb0b7 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
AdamGreen 0:3b00827bb0b7 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
AdamGreen 0:3b00827bb0b7 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
AdamGreen 0:3b00827bb0b7 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
AdamGreen 0:3b00827bb0b7 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
AdamGreen 0:3b00827bb0b7 180
AdamGreen 0:3b00827bb0b7 181 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 182 * Macro defines for MII Management Command Register
AdamGreen 0:3b00827bb0b7 183 **********************************************************************/
AdamGreen 0:3b00827bb0b7 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
AdamGreen 0:3b00827bb0b7 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
AdamGreen 0:3b00827bb0b7 186
AdamGreen 0:3b00827bb0b7 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
AdamGreen 0:3b00827bb0b7 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
AdamGreen 0:3b00827bb0b7 189
AdamGreen 0:3b00827bb0b7 190 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 191 * Macro defines for MII Management Address Register
AdamGreen 0:3b00827bb0b7 192 **********************************************************************/
AdamGreen 0:3b00827bb0b7 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
AdamGreen 0:3b00827bb0b7 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
AdamGreen 0:3b00827bb0b7 195
AdamGreen 0:3b00827bb0b7 196 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 197 * Macro defines for MII Management Write Data Register
AdamGreen 0:3b00827bb0b7 198 **********************************************************************/
AdamGreen 0:3b00827bb0b7 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
AdamGreen 0:3b00827bb0b7 200
AdamGreen 0:3b00827bb0b7 201 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 202 * Macro defines for MII Management Read Data Register
AdamGreen 0:3b00827bb0b7 203 **********************************************************************/
AdamGreen 0:3b00827bb0b7 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
AdamGreen 0:3b00827bb0b7 205
AdamGreen 0:3b00827bb0b7 206 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 207 * Macro defines for MII Management Indicators Register
AdamGreen 0:3b00827bb0b7 208 **********************************************************************/
AdamGreen 0:3b00827bb0b7 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
AdamGreen 0:3b00827bb0b7 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
AdamGreen 0:3b00827bb0b7 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
AdamGreen 0:3b00827bb0b7 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
AdamGreen 0:3b00827bb0b7 213
AdamGreen 0:3b00827bb0b7 214 /* Station Address 0 Register */
AdamGreen 0:3b00827bb0b7 215 /* Station Address 1 Register */
AdamGreen 0:3b00827bb0b7 216 /* Station Address 2 Register */
AdamGreen 0:3b00827bb0b7 217
AdamGreen 0:3b00827bb0b7 218
AdamGreen 0:3b00827bb0b7 219 /* Control register definitions --------------------------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 220 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 221 * Macro defines for Command Register
AdamGreen 0:3b00827bb0b7 222 **********************************************************************/
AdamGreen 0:3b00827bb0b7 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
AdamGreen 0:3b00827bb0b7 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
AdamGreen 0:3b00827bb0b7 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
AdamGreen 0:3b00827bb0b7 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
AdamGreen 0:3b00827bb0b7 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
AdamGreen 0:3b00827bb0b7 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
AdamGreen 0:3b00827bb0b7 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
AdamGreen 0:3b00827bb0b7 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
AdamGreen 0:3b00827bb0b7 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
AdamGreen 0:3b00827bb0b7 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
AdamGreen 0:3b00827bb0b7 233
AdamGreen 0:3b00827bb0b7 234 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 235 * Macro defines for Status Register
AdamGreen 0:3b00827bb0b7 236 **********************************************************************/
AdamGreen 0:3b00827bb0b7 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
AdamGreen 0:3b00827bb0b7 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
AdamGreen 0:3b00827bb0b7 239
AdamGreen 0:3b00827bb0b7 240 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 241 * Macro defines for Transmit Status Vector 0 Register
AdamGreen 0:3b00827bb0b7 242 **********************************************************************/
AdamGreen 0:3b00827bb0b7 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
AdamGreen 0:3b00827bb0b7 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
AdamGreen 0:3b00827bb0b7 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
AdamGreen 0:3b00827bb0b7 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
AdamGreen 0:3b00827bb0b7 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
AdamGreen 0:3b00827bb0b7 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
AdamGreen 0:3b00827bb0b7 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
AdamGreen 0:3b00827bb0b7 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
AdamGreen 0:3b00827bb0b7 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
AdamGreen 0:3b00827bb0b7 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
AdamGreen 0:3b00827bb0b7 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
AdamGreen 0:3b00827bb0b7 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
AdamGreen 0:3b00827bb0b7 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
AdamGreen 0:3b00827bb0b7 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
AdamGreen 0:3b00827bb0b7 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
AdamGreen 0:3b00827bb0b7 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
AdamGreen 0:3b00827bb0b7 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
AdamGreen 0:3b00827bb0b7 260
AdamGreen 0:3b00827bb0b7 261 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 262 * Macro defines for Transmit Status Vector 1 Register
AdamGreen 0:3b00827bb0b7 263 **********************************************************************/
AdamGreen 0:3b00827bb0b7 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
AdamGreen 0:3b00827bb0b7 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
AdamGreen 0:3b00827bb0b7 266
AdamGreen 0:3b00827bb0b7 267 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 268 * Macro defines for Receive Status Vector Register
AdamGreen 0:3b00827bb0b7 269 **********************************************************************/
AdamGreen 0:3b00827bb0b7 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
AdamGreen 0:3b00827bb0b7 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
AdamGreen 0:3b00827bb0b7 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
AdamGreen 0:3b00827bb0b7 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
AdamGreen 0:3b00827bb0b7 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
AdamGreen 0:3b00827bb0b7 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
AdamGreen 0:3b00827bb0b7 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
AdamGreen 0:3b00827bb0b7 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
AdamGreen 0:3b00827bb0b7 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
AdamGreen 0:3b00827bb0b7 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
AdamGreen 0:3b00827bb0b7 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
AdamGreen 0:3b00827bb0b7 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
AdamGreen 0:3b00827bb0b7 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
AdamGreen 0:3b00827bb0b7 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
AdamGreen 0:3b00827bb0b7 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
AdamGreen 0:3b00827bb0b7 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
AdamGreen 0:3b00827bb0b7 286
AdamGreen 0:3b00827bb0b7 287 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 288 * Macro defines for Flow Control Counter Register
AdamGreen 0:3b00827bb0b7 289 **********************************************************************/
AdamGreen 0:3b00827bb0b7 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
AdamGreen 0:3b00827bb0b7 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
AdamGreen 0:3b00827bb0b7 292
AdamGreen 0:3b00827bb0b7 293 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 294 * Macro defines for Flow Control Status Register
AdamGreen 0:3b00827bb0b7 295 **********************************************************************/
AdamGreen 0:3b00827bb0b7 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
AdamGreen 0:3b00827bb0b7 297
AdamGreen 0:3b00827bb0b7 298
AdamGreen 0:3b00827bb0b7 299 /* Receive filter register definitions -------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 300 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 301 * Macro defines for Receive Filter Control Register
AdamGreen 0:3b00827bb0b7 302 **********************************************************************/
AdamGreen 0:3b00827bb0b7 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
AdamGreen 0:3b00827bb0b7 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
AdamGreen 0:3b00827bb0b7 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
AdamGreen 0:3b00827bb0b7 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
AdamGreen 0:3b00827bb0b7 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
AdamGreen 0:3b00827bb0b7 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
AdamGreen 0:3b00827bb0b7 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
AdamGreen 0:3b00827bb0b7 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
AdamGreen 0:3b00827bb0b7 311
AdamGreen 0:3b00827bb0b7 312 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 313 * Macro defines for Receive Filter WoL Status/Clear Registers
AdamGreen 0:3b00827bb0b7 314 **********************************************************************/
AdamGreen 0:3b00827bb0b7 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
AdamGreen 0:3b00827bb0b7 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
AdamGreen 0:3b00827bb0b7 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
AdamGreen 0:3b00827bb0b7 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
AdamGreen 0:3b00827bb0b7 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
AdamGreen 0:3b00827bb0b7 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
AdamGreen 0:3b00827bb0b7 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
AdamGreen 0:3b00827bb0b7 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
AdamGreen 0:3b00827bb0b7 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
AdamGreen 0:3b00827bb0b7 324
AdamGreen 0:3b00827bb0b7 325
AdamGreen 0:3b00827bb0b7 326 /* Module control register definitions ---------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 327 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
AdamGreen 0:3b00827bb0b7 329 **********************************************************************/
AdamGreen 0:3b00827bb0b7 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
AdamGreen 0:3b00827bb0b7 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
AdamGreen 0:3b00827bb0b7 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
AdamGreen 0:3b00827bb0b7 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
AdamGreen 0:3b00827bb0b7 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
AdamGreen 0:3b00827bb0b7 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
AdamGreen 0:3b00827bb0b7 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
AdamGreen 0:3b00827bb0b7 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
AdamGreen 0:3b00827bb0b7 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
AdamGreen 0:3b00827bb0b7 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
AdamGreen 0:3b00827bb0b7 340
AdamGreen 0:3b00827bb0b7 341 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 342 * Macro defines for Power Down Register
AdamGreen 0:3b00827bb0b7 343 **********************************************************************/
AdamGreen 0:3b00827bb0b7 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
AdamGreen 0:3b00827bb0b7 345
AdamGreen 0:3b00827bb0b7 346 /* Descriptor and status formats ---------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 347 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 348 * Macro defines for RX Descriptor Control Word
AdamGreen 0:3b00827bb0b7 349 **********************************************************************/
AdamGreen 0:3b00827bb0b7 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
AdamGreen 0:3b00827bb0b7 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
AdamGreen 0:3b00827bb0b7 352
AdamGreen 0:3b00827bb0b7 353 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 354 * Macro defines for RX Status Hash CRC Word
AdamGreen 0:3b00827bb0b7 355 **********************************************************************/
AdamGreen 0:3b00827bb0b7 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
AdamGreen 0:3b00827bb0b7 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
AdamGreen 0:3b00827bb0b7 358
AdamGreen 0:3b00827bb0b7 359 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 360 * Macro defines for RX Status Information Word
AdamGreen 0:3b00827bb0b7 361 **********************************************************************/
AdamGreen 0:3b00827bb0b7 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
AdamGreen 0:3b00827bb0b7 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
AdamGreen 0:3b00827bb0b7 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
AdamGreen 0:3b00827bb0b7 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
AdamGreen 0:3b00827bb0b7 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
AdamGreen 0:3b00827bb0b7 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
AdamGreen 0:3b00827bb0b7 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
AdamGreen 0:3b00827bb0b7 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
AdamGreen 0:3b00827bb0b7 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
AdamGreen 0:3b00827bb0b7 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
AdamGreen 0:3b00827bb0b7 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
AdamGreen 0:3b00827bb0b7 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
AdamGreen 0:3b00827bb0b7 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
AdamGreen 0:3b00827bb0b7 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
AdamGreen 0:3b00827bb0b7 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
AdamGreen 0:3b00827bb0b7 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
AdamGreen 0:3b00827bb0b7 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
AdamGreen 0:3b00827bb0b7 379
AdamGreen 0:3b00827bb0b7 380 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 381 * Macro defines for TX Descriptor Control Word
AdamGreen 0:3b00827bb0b7 382 **********************************************************************/
AdamGreen 0:3b00827bb0b7 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
AdamGreen 0:3b00827bb0b7 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
AdamGreen 0:3b00827bb0b7 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
AdamGreen 0:3b00827bb0b7 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
AdamGreen 0:3b00827bb0b7 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
AdamGreen 0:3b00827bb0b7 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
AdamGreen 0:3b00827bb0b7 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
AdamGreen 0:3b00827bb0b7 390
AdamGreen 0:3b00827bb0b7 391 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 392 * Macro defines for TX Status Information Word
AdamGreen 0:3b00827bb0b7 393 **********************************************************************/
AdamGreen 0:3b00827bb0b7 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
AdamGreen 0:3b00827bb0b7 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
AdamGreen 0:3b00827bb0b7 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
AdamGreen 0:3b00827bb0b7 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
AdamGreen 0:3b00827bb0b7 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
AdamGreen 0:3b00827bb0b7 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
AdamGreen 0:3b00827bb0b7 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
AdamGreen 0:3b00827bb0b7 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
AdamGreen 0:3b00827bb0b7 402
AdamGreen 0:3b00827bb0b7 403 #ifdef MCB_LPC_1768
AdamGreen 0:3b00827bb0b7 404 /* DP83848C PHY definition ------------------------------------------------------------ */
AdamGreen 0:3b00827bb0b7 405
AdamGreen 0:3b00827bb0b7 406 /** PHY device reset time out definition */
AdamGreen 0:3b00827bb0b7 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
AdamGreen 0:3b00827bb0b7 408
AdamGreen 0:3b00827bb0b7 409 /* ENET Device Revision ID */
AdamGreen 0:3b00827bb0b7 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
AdamGreen 0:3b00827bb0b7 411
AdamGreen 0:3b00827bb0b7 412 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 413 * Macro defines for DP83848C PHY Registers
AdamGreen 0:3b00827bb0b7 414 **********************************************************************/
AdamGreen 0:3b00827bb0b7 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
AdamGreen 0:3b00827bb0b7 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
AdamGreen 0:3b00827bb0b7 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
AdamGreen 0:3b00827bb0b7 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
AdamGreen 0:3b00827bb0b7 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
AdamGreen 0:3b00827bb0b7 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
AdamGreen 0:3b00827bb0b7 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
AdamGreen 0:3b00827bb0b7 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
AdamGreen 0:3b00827bb0b7 423 #define EMAC_PHY_REG_LPNPA 0x08
AdamGreen 0:3b00827bb0b7 424
AdamGreen 0:3b00827bb0b7 425 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 426 * Macro defines for PHY Extended Registers
AdamGreen 0:3b00827bb0b7 427 **********************************************************************/
AdamGreen 0:3b00827bb0b7 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
AdamGreen 0:3b00827bb0b7 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
AdamGreen 0:3b00827bb0b7 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
AdamGreen 0:3b00827bb0b7 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
AdamGreen 0:3b00827bb0b7 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
AdamGreen 0:3b00827bb0b7 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
AdamGreen 0:3b00827bb0b7 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
AdamGreen 0:3b00827bb0b7 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
AdamGreen 0:3b00827bb0b7 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
AdamGreen 0:3b00827bb0b7 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
AdamGreen 0:3b00827bb0b7 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
AdamGreen 0:3b00827bb0b7 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
AdamGreen 0:3b00827bb0b7 440
AdamGreen 0:3b00827bb0b7 441 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 442 * Macro defines for PHY Basic Mode Control Register
AdamGreen 0:3b00827bb0b7 443 **********************************************************************/
AdamGreen 0:3b00827bb0b7 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
AdamGreen 0:3b00827bb0b7 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
AdamGreen 0:3b00827bb0b7 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
AdamGreen 0:3b00827bb0b7 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
AdamGreen 0:3b00827bb0b7 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
AdamGreen 0:3b00827bb0b7 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
AdamGreen 0:3b00827bb0b7 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
AdamGreen 0:3b00827bb0b7 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
AdamGreen 0:3b00827bb0b7 452
AdamGreen 0:3b00827bb0b7 453 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 454 * Macro defines for PHY Basic Mode Status Status Register
AdamGreen 0:3b00827bb0b7 455 **********************************************************************/
AdamGreen 0:3b00827bb0b7 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
AdamGreen 0:3b00827bb0b7 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
AdamGreen 0:3b00827bb0b7 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
AdamGreen 0:3b00827bb0b7 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
AdamGreen 0:3b00827bb0b7 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
AdamGreen 0:3b00827bb0b7 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
AdamGreen 0:3b00827bb0b7 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
AdamGreen 0:3b00827bb0b7 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
AdamGreen 0:3b00827bb0b7 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
AdamGreen 0:3b00827bb0b7 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
AdamGreen 0:3b00827bb0b7 466
AdamGreen 0:3b00827bb0b7 467 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 468 * Macro defines for PHY Status Register
AdamGreen 0:3b00827bb0b7 469 **********************************************************************/
AdamGreen 0:3b00827bb0b7 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
AdamGreen 0:3b00827bb0b7 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
AdamGreen 0:3b00827bb0b7 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
AdamGreen 0:3b00827bb0b7 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
AdamGreen 0:3b00827bb0b7 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
AdamGreen 0:3b00827bb0b7 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
AdamGreen 0:3b00827bb0b7 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
AdamGreen 0:3b00827bb0b7 477
AdamGreen 0:3b00827bb0b7 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
AdamGreen 0:3b00827bb0b7 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
AdamGreen 0:3b00827bb0b7 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
AdamGreen 0:3b00827bb0b7 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
AdamGreen 0:3b00827bb0b7 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
AdamGreen 0:3b00827bb0b7 483
AdamGreen 0:3b00827bb0b7 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
AdamGreen 0:3b00827bb0b7 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
AdamGreen 0:3b00827bb0b7 486
AdamGreen 0:3b00827bb0b7 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
AdamGreen 0:3b00827bb0b7 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
AdamGreen 0:3b00827bb0b7 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
AdamGreen 0:3b00827bb0b7 490
AdamGreen 0:3b00827bb0b7 491 #elif defined(IAR_LPC_1768)
AdamGreen 0:3b00827bb0b7 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
AdamGreen 0:3b00827bb0b7 493 /** PHY device reset time out definition */
AdamGreen 0:3b00827bb0b7 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
AdamGreen 0:3b00827bb0b7 495
AdamGreen 0:3b00827bb0b7 496 /* ENET Device Revision ID */
AdamGreen 0:3b00827bb0b7 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
AdamGreen 0:3b00827bb0b7 498
AdamGreen 0:3b00827bb0b7 499 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 500 * Macro defines for KSZ8721BL PHY Registers
AdamGreen 0:3b00827bb0b7 501 **********************************************************************/
AdamGreen 0:3b00827bb0b7 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
AdamGreen 0:3b00827bb0b7 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
AdamGreen 0:3b00827bb0b7 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
AdamGreen 0:3b00827bb0b7 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
AdamGreen 0:3b00827bb0b7 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
AdamGreen 0:3b00827bb0b7 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
AdamGreen 0:3b00827bb0b7 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
AdamGreen 0:3b00827bb0b7 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
AdamGreen 0:3b00827bb0b7 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
AdamGreen 0:3b00827bb0b7 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
AdamGreen 0:3b00827bb0b7 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
AdamGreen 0:3b00827bb0b7 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
AdamGreen 0:3b00827bb0b7 514
AdamGreen 0:3b00827bb0b7 515 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 516 * Macro defines for PHY Basic Mode Control Register
AdamGreen 0:3b00827bb0b7 517 **********************************************************************/
AdamGreen 0:3b00827bb0b7 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
AdamGreen 0:3b00827bb0b7 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
AdamGreen 0:3b00827bb0b7 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
AdamGreen 0:3b00827bb0b7 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
AdamGreen 0:3b00827bb0b7 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
AdamGreen 0:3b00827bb0b7 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
AdamGreen 0:3b00827bb0b7 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
AdamGreen 0:3b00827bb0b7 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
AdamGreen 0:3b00827bb0b7 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
AdamGreen 0:3b00827bb0b7 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
AdamGreen 0:3b00827bb0b7 528
AdamGreen 0:3b00827bb0b7 529 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 530 * Macro defines for PHY Basic Mode Status Register
AdamGreen 0:3b00827bb0b7 531 **********************************************************************/
AdamGreen 0:3b00827bb0b7 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
AdamGreen 0:3b00827bb0b7 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
AdamGreen 0:3b00827bb0b7 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
AdamGreen 0:3b00827bb0b7 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
AdamGreen 0:3b00827bb0b7 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
AdamGreen 0:3b00827bb0b7 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
AdamGreen 0:3b00827bb0b7 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
AdamGreen 0:3b00827bb0b7 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
AdamGreen 0:3b00827bb0b7 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
AdamGreen 0:3b00827bb0b7 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
AdamGreen 0:3b00827bb0b7 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
AdamGreen 0:3b00827bb0b7 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
AdamGreen 0:3b00827bb0b7 544
AdamGreen 0:3b00827bb0b7 545 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 546 * Macro defines for PHY Identifier
AdamGreen 0:3b00827bb0b7 547 **********************************************************************/
AdamGreen 0:3b00827bb0b7 548 /* PHY Identifier 1 bitmap definitions */
AdamGreen 0:3b00827bb0b7 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
AdamGreen 0:3b00827bb0b7 550
AdamGreen 0:3b00827bb0b7 551 /* PHY Identifier 2 bitmap definitions */
AdamGreen 0:3b00827bb0b7 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
AdamGreen 0:3b00827bb0b7 553
AdamGreen 0:3b00827bb0b7 554 /*********************************************************************//**
AdamGreen 0:3b00827bb0b7 555 * Macro defines for Auto-Negotiation Advertisement
AdamGreen 0:3b00827bb0b7 556 **********************************************************************/
AdamGreen 0:3b00827bb0b7 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
AdamGreen 0:3b00827bb0b7 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
AdamGreen 0:3b00827bb0b7 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
AdamGreen 0:3b00827bb0b7 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
AdamGreen 0:3b00827bb0b7 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
AdamGreen 0:3b00827bb0b7 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
AdamGreen 0:3b00827bb0b7 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
AdamGreen 0:3b00827bb0b7 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
AdamGreen 0:3b00827bb0b7 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
AdamGreen 0:3b00827bb0b7 566
AdamGreen 0:3b00827bb0b7 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
AdamGreen 0:3b00827bb0b7 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
AdamGreen 0:3b00827bb0b7 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
AdamGreen 0:3b00827bb0b7 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
AdamGreen 0:3b00827bb0b7 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
AdamGreen 0:3b00827bb0b7 572
AdamGreen 0:3b00827bb0b7 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
AdamGreen 0:3b00827bb0b7 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
AdamGreen 0:3b00827bb0b7 575
AdamGreen 0:3b00827bb0b7 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
AdamGreen 0:3b00827bb0b7 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
AdamGreen 0:3b00827bb0b7 578 #endif
AdamGreen 0:3b00827bb0b7 579
AdamGreen 0:3b00827bb0b7 580 /**
AdamGreen 0:3b00827bb0b7 581 * @}
AdamGreen 0:3b00827bb0b7 582 */
AdamGreen 0:3b00827bb0b7 583
AdamGreen 0:3b00827bb0b7 584
AdamGreen 0:3b00827bb0b7 585 /* Public Types --------------------------------------------------------------- */
AdamGreen 0:3b00827bb0b7 586 /** @defgroup EMAC_Public_Types EMAC Public Types
AdamGreen 0:3b00827bb0b7 587 * @{
AdamGreen 0:3b00827bb0b7 588 */
AdamGreen 0:3b00827bb0b7 589
AdamGreen 0:3b00827bb0b7 590 /* Descriptor and status formats ---------------------------------------------- */
AdamGreen 0:3b00827bb0b7 591
AdamGreen 0:3b00827bb0b7 592 /**
AdamGreen 0:3b00827bb0b7 593 * @brief RX Descriptor structure type definition
AdamGreen 0:3b00827bb0b7 594 */
AdamGreen 0:3b00827bb0b7 595 typedef struct {
AdamGreen 0:3b00827bb0b7 596 uint32_t Packet; /**< Receive Packet Descriptor */
AdamGreen 0:3b00827bb0b7 597 uint32_t Ctrl; /**< Receive Control Descriptor */
AdamGreen 0:3b00827bb0b7 598 } RX_Desc;
AdamGreen 0:3b00827bb0b7 599
AdamGreen 0:3b00827bb0b7 600 /**
AdamGreen 0:3b00827bb0b7 601 * @brief RX Status structure type definition
AdamGreen 0:3b00827bb0b7 602 */
AdamGreen 0:3b00827bb0b7 603 typedef struct {
AdamGreen 0:3b00827bb0b7 604 uint32_t Info; /**< Receive Information Status */
AdamGreen 0:3b00827bb0b7 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
AdamGreen 0:3b00827bb0b7 606 } RX_Stat;
AdamGreen 0:3b00827bb0b7 607
AdamGreen 0:3b00827bb0b7 608 /**
AdamGreen 0:3b00827bb0b7 609 * @brief TX Descriptor structure type definition
AdamGreen 0:3b00827bb0b7 610 */
AdamGreen 0:3b00827bb0b7 611 typedef struct {
AdamGreen 0:3b00827bb0b7 612 uint32_t Packet; /**< Transmit Packet Descriptor */
AdamGreen 0:3b00827bb0b7 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
AdamGreen 0:3b00827bb0b7 614 } TX_Desc;
AdamGreen 0:3b00827bb0b7 615
AdamGreen 0:3b00827bb0b7 616 /**
AdamGreen 0:3b00827bb0b7 617 * @brief TX Status structure type definition
AdamGreen 0:3b00827bb0b7 618 */
AdamGreen 0:3b00827bb0b7 619 typedef struct {
AdamGreen 0:3b00827bb0b7 620 uint32_t Info; /**< Transmit Information Status */
AdamGreen 0:3b00827bb0b7 621 } TX_Stat;
AdamGreen 0:3b00827bb0b7 622
AdamGreen 0:3b00827bb0b7 623
AdamGreen 0:3b00827bb0b7 624 /**
AdamGreen 0:3b00827bb0b7 625 * @brief TX Data Buffer structure definition
AdamGreen 0:3b00827bb0b7 626 */
AdamGreen 0:3b00827bb0b7 627 typedef struct {
AdamGreen 0:3b00827bb0b7 628 uint32_t ulDataLen; /**< Data length */
AdamGreen 0:3b00827bb0b7 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
AdamGreen 0:3b00827bb0b7 630 } EMAC_PACKETBUF_Type;
AdamGreen 0:3b00827bb0b7 631
AdamGreen 0:3b00827bb0b7 632 /**
AdamGreen 0:3b00827bb0b7 633 * @brief EMAC configuration structure definition
AdamGreen 0:3b00827bb0b7 634 */
AdamGreen 0:3b00827bb0b7 635 typedef struct {
AdamGreen 0:3b00827bb0b7 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
AdamGreen 0:3b00827bb0b7 637 - EMAC_MODE_AUTO
AdamGreen 0:3b00827bb0b7 638 - EMAC_MODE_10M_FULL
AdamGreen 0:3b00827bb0b7 639 - EMAC_MODE_10M_HALF
AdamGreen 0:3b00827bb0b7 640 - EMAC_MODE_100M_FULL
AdamGreen 0:3b00827bb0b7 641 - EMAC_MODE_100M_HALF
AdamGreen 0:3b00827bb0b7 642 */
AdamGreen 0:3b00827bb0b7 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
AdamGreen 0:3b00827bb0b7 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
AdamGreen 0:3b00827bb0b7 645 */
AdamGreen 0:3b00827bb0b7 646 } EMAC_CFG_Type;
AdamGreen 0:3b00827bb0b7 647
AdamGreen 0:3b00827bb0b7 648 /** Ethernet block power/clock control bit*/
AdamGreen 0:3b00827bb0b7 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
AdamGreen 0:3b00827bb0b7 650
AdamGreen 0:3b00827bb0b7 651 #ifdef __cplusplus
AdamGreen 0:3b00827bb0b7 652 }
AdamGreen 0:3b00827bb0b7 653 #endif
AdamGreen 0:3b00827bb0b7 654
AdamGreen 0:3b00827bb0b7 655 #endif /* LPC17XX_EMAC_H_ */
AdamGreen 0:3b00827bb0b7 656
AdamGreen 0:3b00827bb0b7 657 /**
AdamGreen 0:3b00827bb0b7 658 * @}
AdamGreen 0:3b00827bb0b7 659 */
AdamGreen 0:3b00827bb0b7 660
AdamGreen 0:3b00827bb0b7 661 /* --------------------------------- End Of File ------------------------------ */