Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file LPC17xx.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
bogdanm 0:9b334a45a8ff 4 * NXP LPC17xx Device Series
bogdanm 0:9b334a45a8ff 5 * @version: V1.09
bogdanm 0:9b334a45a8ff 6 * @date: 17. March 2010
bogdanm 0:9b334a45a8ff 7
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * @note
bogdanm 0:9b334a45a8ff 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * @par
bogdanm 0:9b334a45a8ff 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 0:9b334a45a8ff 14 * processor based microcontrollers. This file can be freely distributed
bogdanm 0:9b334a45a8ff 15 * within development tools that are supporting such ARM based processors.
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * @par
bogdanm 0:9b334a45a8ff 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 0:9b334a45a8ff 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 0:9b334a45a8ff 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 0:9b334a45a8ff 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 0:9b334a45a8ff 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 ******************************************************************************/
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 #ifndef __LPC17xx_H__
bogdanm 0:9b334a45a8ff 28 #define __LPC17xx_H__
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 /*
bogdanm 0:9b334a45a8ff 31 * ==========================================================================
bogdanm 0:9b334a45a8ff 32 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 33 * ==========================================================================
bogdanm 0:9b334a45a8ff 34 */
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 typedef enum IRQn
bogdanm 0:9b334a45a8ff 37 {
bogdanm 0:9b334a45a8ff 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
bogdanm 0:9b334a45a8ff 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 0:9b334a45a8ff 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 0:9b334a45a8ff 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 0:9b334a45a8ff 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 0:9b334a45a8ff 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
bogdanm 0:9b334a45a8ff 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 0:9b334a45a8ff 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 0:9b334a45a8ff 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 0:9b334a45a8ff 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 0:9b334a45a8ff 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 0:9b334a45a8ff 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 0:9b334a45a8ff 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 0:9b334a45a8ff 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 0:9b334a45a8ff 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 0:9b334a45a8ff 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 0:9b334a45a8ff 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 0:9b334a45a8ff 62 SPI_IRQn = 13, /*!< SPI Interrupt */
bogdanm 0:9b334a45a8ff 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 0:9b334a45a8ff 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 0:9b334a45a8ff 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 0:9b334a45a8ff 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 0:9b334a45a8ff 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 0:9b334a45a8ff 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 0:9b334a45a8ff 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 0:9b334a45a8ff 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 0:9b334a45a8ff 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 0:9b334a45a8ff 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 0:9b334a45a8ff 73 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 0:9b334a45a8ff 74 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 0:9b334a45a8ff 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 0:9b334a45a8ff 76 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 0:9b334a45a8ff 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 0:9b334a45a8ff 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
bogdanm 0:9b334a45a8ff 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 0:9b334a45a8ff 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 0:9b334a45a8ff 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 0:9b334a45a8ff 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
bogdanm 0:9b334a45a8ff 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
bogdanm 0:9b334a45a8ff 84 } IRQn_Type;
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /*
bogdanm 0:9b334a45a8ff 88 * ==========================================================================
bogdanm 0:9b334a45a8ff 89 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 90 * ==========================================================================
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 0:9b334a45a8ff 100 #include "system_LPC17xx.h" /* System Header */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /******************************************************************************/
bogdanm 0:9b334a45a8ff 104 /* Device Specific Peripheral registers structures */
bogdanm 0:9b334a45a8ff 105 /******************************************************************************/
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 108 #pragma anon_unions
bogdanm 0:9b334a45a8ff 109 #endif
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 typedef struct
bogdanm 0:9b334a45a8ff 113 {
bogdanm 0:9b334a45a8ff 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
bogdanm 0:9b334a45a8ff 115 uint32_t RESERVED0[31];
bogdanm 0:9b334a45a8ff 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 0:9b334a45a8ff 117 __IO uint32_t PLL0CFG;
bogdanm 0:9b334a45a8ff 118 __I uint32_t PLL0STAT;
bogdanm 0:9b334a45a8ff 119 __O uint32_t PLL0FEED;
bogdanm 0:9b334a45a8ff 120 uint32_t RESERVED1[4];
bogdanm 0:9b334a45a8ff 121 __IO uint32_t PLL1CON;
bogdanm 0:9b334a45a8ff 122 __IO uint32_t PLL1CFG;
bogdanm 0:9b334a45a8ff 123 __I uint32_t PLL1STAT;
bogdanm 0:9b334a45a8ff 124 __O uint32_t PLL1FEED;
bogdanm 0:9b334a45a8ff 125 uint32_t RESERVED2[4];
bogdanm 0:9b334a45a8ff 126 __IO uint32_t PCON;
bogdanm 0:9b334a45a8ff 127 __IO uint32_t PCONP;
bogdanm 0:9b334a45a8ff 128 uint32_t RESERVED3[15];
bogdanm 0:9b334a45a8ff 129 __IO uint32_t CCLKCFG;
bogdanm 0:9b334a45a8ff 130 __IO uint32_t USBCLKCFG;
bogdanm 0:9b334a45a8ff 131 __IO uint32_t CLKSRCSEL;
bogdanm 0:9b334a45a8ff 132 __IO uint32_t CANSLEEPCLR;
bogdanm 0:9b334a45a8ff 133 __IO uint32_t CANWAKEFLAGS;
bogdanm 0:9b334a45a8ff 134 uint32_t RESERVED4[10];
bogdanm 0:9b334a45a8ff 135 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 0:9b334a45a8ff 136 uint32_t RESERVED5;
bogdanm 0:9b334a45a8ff 137 __IO uint32_t EXTMODE;
bogdanm 0:9b334a45a8ff 138 __IO uint32_t EXTPOLAR;
bogdanm 0:9b334a45a8ff 139 uint32_t RESERVED6[12];
bogdanm 0:9b334a45a8ff 140 __IO uint32_t RSID; /* Reset */
bogdanm 0:9b334a45a8ff 141 uint32_t RESERVED7[7];
bogdanm 0:9b334a45a8ff 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 0:9b334a45a8ff 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 0:9b334a45a8ff 144 __IO uint32_t PCLKSEL0;
bogdanm 0:9b334a45a8ff 145 __IO uint32_t PCLKSEL1;
bogdanm 0:9b334a45a8ff 146 uint32_t RESERVED8[4];
bogdanm 0:9b334a45a8ff 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 0:9b334a45a8ff 148 __IO uint32_t DMAREQSEL;
bogdanm 0:9b334a45a8ff 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 0:9b334a45a8ff 150 } LPC_SC_TypeDef;
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 0:9b334a45a8ff 153 typedef struct
bogdanm 0:9b334a45a8ff 154 {
bogdanm 0:9b334a45a8ff 155 __IO uint32_t PINSEL0;
bogdanm 0:9b334a45a8ff 156 __IO uint32_t PINSEL1;
bogdanm 0:9b334a45a8ff 157 __IO uint32_t PINSEL2;
bogdanm 0:9b334a45a8ff 158 __IO uint32_t PINSEL3;
bogdanm 0:9b334a45a8ff 159 __IO uint32_t PINSEL4;
bogdanm 0:9b334a45a8ff 160 __IO uint32_t PINSEL5;
bogdanm 0:9b334a45a8ff 161 __IO uint32_t PINSEL6;
bogdanm 0:9b334a45a8ff 162 __IO uint32_t PINSEL7;
bogdanm 0:9b334a45a8ff 163 __IO uint32_t PINSEL8;
bogdanm 0:9b334a45a8ff 164 __IO uint32_t PINSEL9;
bogdanm 0:9b334a45a8ff 165 __IO uint32_t PINSEL10;
bogdanm 0:9b334a45a8ff 166 uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 167 __IO uint32_t PINMODE0;
bogdanm 0:9b334a45a8ff 168 __IO uint32_t PINMODE1;
bogdanm 0:9b334a45a8ff 169 __IO uint32_t PINMODE2;
bogdanm 0:9b334a45a8ff 170 __IO uint32_t PINMODE3;
bogdanm 0:9b334a45a8ff 171 __IO uint32_t PINMODE4;
bogdanm 0:9b334a45a8ff 172 __IO uint32_t PINMODE5;
bogdanm 0:9b334a45a8ff 173 __IO uint32_t PINMODE6;
bogdanm 0:9b334a45a8ff 174 __IO uint32_t PINMODE7;
bogdanm 0:9b334a45a8ff 175 __IO uint32_t PINMODE8;
bogdanm 0:9b334a45a8ff 176 __IO uint32_t PINMODE9;
bogdanm 0:9b334a45a8ff 177 __IO uint32_t PINMODE_OD0;
bogdanm 0:9b334a45a8ff 178 __IO uint32_t PINMODE_OD1;
bogdanm 0:9b334a45a8ff 179 __IO uint32_t PINMODE_OD2;
bogdanm 0:9b334a45a8ff 180 __IO uint32_t PINMODE_OD3;
bogdanm 0:9b334a45a8ff 181 __IO uint32_t PINMODE_OD4;
bogdanm 0:9b334a45a8ff 182 __IO uint32_t I2CPADCFG;
bogdanm 0:9b334a45a8ff 183 } LPC_PINCON_TypeDef;
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 0:9b334a45a8ff 186 typedef struct
bogdanm 0:9b334a45a8ff 187 {
bogdanm 0:9b334a45a8ff 188 union {
bogdanm 0:9b334a45a8ff 189 __IO uint32_t FIODIR;
bogdanm 0:9b334a45a8ff 190 struct {
bogdanm 0:9b334a45a8ff 191 __IO uint16_t FIODIRL;
bogdanm 0:9b334a45a8ff 192 __IO uint16_t FIODIRH;
bogdanm 0:9b334a45a8ff 193 };
bogdanm 0:9b334a45a8ff 194 struct {
bogdanm 0:9b334a45a8ff 195 __IO uint8_t FIODIR0;
bogdanm 0:9b334a45a8ff 196 __IO uint8_t FIODIR1;
bogdanm 0:9b334a45a8ff 197 __IO uint8_t FIODIR2;
bogdanm 0:9b334a45a8ff 198 __IO uint8_t FIODIR3;
bogdanm 0:9b334a45a8ff 199 };
bogdanm 0:9b334a45a8ff 200 };
bogdanm 0:9b334a45a8ff 201 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 202 union {
bogdanm 0:9b334a45a8ff 203 __IO uint32_t FIOMASK;
bogdanm 0:9b334a45a8ff 204 struct {
bogdanm 0:9b334a45a8ff 205 __IO uint16_t FIOMASKL;
bogdanm 0:9b334a45a8ff 206 __IO uint16_t FIOMASKH;
bogdanm 0:9b334a45a8ff 207 };
bogdanm 0:9b334a45a8ff 208 struct {
bogdanm 0:9b334a45a8ff 209 __IO uint8_t FIOMASK0;
bogdanm 0:9b334a45a8ff 210 __IO uint8_t FIOMASK1;
bogdanm 0:9b334a45a8ff 211 __IO uint8_t FIOMASK2;
bogdanm 0:9b334a45a8ff 212 __IO uint8_t FIOMASK3;
bogdanm 0:9b334a45a8ff 213 };
bogdanm 0:9b334a45a8ff 214 };
bogdanm 0:9b334a45a8ff 215 union {
bogdanm 0:9b334a45a8ff 216 __IO uint32_t FIOPIN;
bogdanm 0:9b334a45a8ff 217 struct {
bogdanm 0:9b334a45a8ff 218 __IO uint16_t FIOPINL;
bogdanm 0:9b334a45a8ff 219 __IO uint16_t FIOPINH;
bogdanm 0:9b334a45a8ff 220 };
bogdanm 0:9b334a45a8ff 221 struct {
bogdanm 0:9b334a45a8ff 222 __IO uint8_t FIOPIN0;
bogdanm 0:9b334a45a8ff 223 __IO uint8_t FIOPIN1;
bogdanm 0:9b334a45a8ff 224 __IO uint8_t FIOPIN2;
bogdanm 0:9b334a45a8ff 225 __IO uint8_t FIOPIN3;
bogdanm 0:9b334a45a8ff 226 };
bogdanm 0:9b334a45a8ff 227 };
bogdanm 0:9b334a45a8ff 228 union {
bogdanm 0:9b334a45a8ff 229 __IO uint32_t FIOSET;
bogdanm 0:9b334a45a8ff 230 struct {
bogdanm 0:9b334a45a8ff 231 __IO uint16_t FIOSETL;
bogdanm 0:9b334a45a8ff 232 __IO uint16_t FIOSETH;
bogdanm 0:9b334a45a8ff 233 };
bogdanm 0:9b334a45a8ff 234 struct {
bogdanm 0:9b334a45a8ff 235 __IO uint8_t FIOSET0;
bogdanm 0:9b334a45a8ff 236 __IO uint8_t FIOSET1;
bogdanm 0:9b334a45a8ff 237 __IO uint8_t FIOSET2;
bogdanm 0:9b334a45a8ff 238 __IO uint8_t FIOSET3;
bogdanm 0:9b334a45a8ff 239 };
bogdanm 0:9b334a45a8ff 240 };
bogdanm 0:9b334a45a8ff 241 union {
bogdanm 0:9b334a45a8ff 242 __O uint32_t FIOCLR;
bogdanm 0:9b334a45a8ff 243 struct {
bogdanm 0:9b334a45a8ff 244 __O uint16_t FIOCLRL;
bogdanm 0:9b334a45a8ff 245 __O uint16_t FIOCLRH;
bogdanm 0:9b334a45a8ff 246 };
bogdanm 0:9b334a45a8ff 247 struct {
bogdanm 0:9b334a45a8ff 248 __O uint8_t FIOCLR0;
bogdanm 0:9b334a45a8ff 249 __O uint8_t FIOCLR1;
bogdanm 0:9b334a45a8ff 250 __O uint8_t FIOCLR2;
bogdanm 0:9b334a45a8ff 251 __O uint8_t FIOCLR3;
bogdanm 0:9b334a45a8ff 252 };
bogdanm 0:9b334a45a8ff 253 };
bogdanm 0:9b334a45a8ff 254 } LPC_GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 typedef struct
bogdanm 0:9b334a45a8ff 257 {
bogdanm 0:9b334a45a8ff 258 __I uint32_t IntStatus;
bogdanm 0:9b334a45a8ff 259 __I uint32_t IO0IntStatR;
bogdanm 0:9b334a45a8ff 260 __I uint32_t IO0IntStatF;
bogdanm 0:9b334a45a8ff 261 __O uint32_t IO0IntClr;
bogdanm 0:9b334a45a8ff 262 __IO uint32_t IO0IntEnR;
bogdanm 0:9b334a45a8ff 263 __IO uint32_t IO0IntEnF;
bogdanm 0:9b334a45a8ff 264 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 265 __I uint32_t IO2IntStatR;
bogdanm 0:9b334a45a8ff 266 __I uint32_t IO2IntStatF;
bogdanm 0:9b334a45a8ff 267 __O uint32_t IO2IntClr;
bogdanm 0:9b334a45a8ff 268 __IO uint32_t IO2IntEnR;
bogdanm 0:9b334a45a8ff 269 __IO uint32_t IO2IntEnF;
bogdanm 0:9b334a45a8ff 270 } LPC_GPIOINT_TypeDef;
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 273 typedef struct
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 276 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 277 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 278 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 279 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 280 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 281 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 282 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 283 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 284 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 285 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 286 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 287 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 288 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 289 __IO uint32_t EMR;
bogdanm 0:9b334a45a8ff 290 uint32_t RESERVED1[12];
bogdanm 0:9b334a45a8ff 291 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 292 } LPC_TIM_TypeDef;
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 0:9b334a45a8ff 295 typedef struct
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 298 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 299 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 300 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 301 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 302 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 303 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 304 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 305 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 306 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 307 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 308 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 309 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 310 __I uint32_t CR2;
bogdanm 0:9b334a45a8ff 311 __I uint32_t CR3;
bogdanm 0:9b334a45a8ff 312 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 313 __IO uint32_t MR4;
bogdanm 0:9b334a45a8ff 314 __IO uint32_t MR5;
bogdanm 0:9b334a45a8ff 315 __IO uint32_t MR6;
bogdanm 0:9b334a45a8ff 316 __IO uint32_t PCR;
bogdanm 0:9b334a45a8ff 317 __IO uint32_t LER;
bogdanm 0:9b334a45a8ff 318 uint32_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 319 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 320 } LPC_PWM_TypeDef;
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 0:9b334a45a8ff 323 typedef struct
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 union {
bogdanm 0:9b334a45a8ff 326 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 327 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 328 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 329 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 330 };
bogdanm 0:9b334a45a8ff 331 union {
bogdanm 0:9b334a45a8ff 332 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 333 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 334 };
bogdanm 0:9b334a45a8ff 335 union {
bogdanm 0:9b334a45a8ff 336 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 337 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 338 };
bogdanm 0:9b334a45a8ff 339 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 340 uint8_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 341 __I uint8_t LSR;
bogdanm 0:9b334a45a8ff 342 uint8_t RESERVED2[7];
bogdanm 0:9b334a45a8ff 343 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 344 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 345 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 346 __IO uint8_t ICR;
bogdanm 0:9b334a45a8ff 347 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 348 __IO uint8_t FDR;
bogdanm 0:9b334a45a8ff 349 uint8_t RESERVED5[7];
bogdanm 0:9b334a45a8ff 350 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 351 uint8_t RESERVED6[39];
bogdanm 0:9b334a45a8ff 352 __IO uint32_t FIFOLVL;
bogdanm 0:9b334a45a8ff 353 } LPC_UART_TypeDef;
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 typedef struct
bogdanm 0:9b334a45a8ff 356 {
bogdanm 0:9b334a45a8ff 357 union {
bogdanm 0:9b334a45a8ff 358 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 359 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 360 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 361 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 362 };
bogdanm 0:9b334a45a8ff 363 union {
bogdanm 0:9b334a45a8ff 364 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 365 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 366 };
bogdanm 0:9b334a45a8ff 367 union {
bogdanm 0:9b334a45a8ff 368 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 369 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 370 };
bogdanm 0:9b334a45a8ff 371 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 372 uint8_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 373 __I uint8_t LSR;
bogdanm 0:9b334a45a8ff 374 uint8_t RESERVED2[7];
bogdanm 0:9b334a45a8ff 375 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 376 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 377 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 378 __IO uint8_t ICR;
bogdanm 0:9b334a45a8ff 379 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 380 __IO uint8_t FDR;
bogdanm 0:9b334a45a8ff 381 uint8_t RESERVED5[7];
bogdanm 0:9b334a45a8ff 382 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 383 uint8_t RESERVED6[39];
bogdanm 0:9b334a45a8ff 384 __IO uint32_t FIFOLVL;
bogdanm 0:9b334a45a8ff 385 } LPC_UART0_TypeDef;
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 typedef struct
bogdanm 0:9b334a45a8ff 388 {
bogdanm 0:9b334a45a8ff 389 union {
bogdanm 0:9b334a45a8ff 390 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 391 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 392 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 393 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 394 };
bogdanm 0:9b334a45a8ff 395 union {
bogdanm 0:9b334a45a8ff 396 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 397 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 398 };
bogdanm 0:9b334a45a8ff 399 union {
bogdanm 0:9b334a45a8ff 400 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 401 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 402 };
bogdanm 0:9b334a45a8ff 403 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 404 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 405 __IO uint8_t MCR;
bogdanm 0:9b334a45a8ff 406 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 407 __I uint8_t LSR;
bogdanm 0:9b334a45a8ff 408 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 409 __I uint8_t MSR;
bogdanm 0:9b334a45a8ff 410 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 411 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 412 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 413 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 414 uint32_t RESERVED6;
bogdanm 0:9b334a45a8ff 415 __IO uint32_t FDR;
bogdanm 0:9b334a45a8ff 416 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 417 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 418 uint8_t RESERVED8[27];
bogdanm 0:9b334a45a8ff 419 __IO uint8_t RS485CTRL;
bogdanm 0:9b334a45a8ff 420 uint8_t RESERVED9[3];
bogdanm 0:9b334a45a8ff 421 __IO uint8_t ADRMATCH;
bogdanm 0:9b334a45a8ff 422 uint8_t RESERVED10[3];
bogdanm 0:9b334a45a8ff 423 __IO uint8_t RS485DLY;
bogdanm 0:9b334a45a8ff 424 uint8_t RESERVED11[3];
bogdanm 0:9b334a45a8ff 425 __IO uint32_t FIFOLVL;
bogdanm 0:9b334a45a8ff 426 } LPC_UART1_TypeDef;
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 0:9b334a45a8ff 429 typedef struct
bogdanm 0:9b334a45a8ff 430 {
bogdanm 0:9b334a45a8ff 431 __IO uint32_t SPCR;
bogdanm 0:9b334a45a8ff 432 __I uint32_t SPSR;
bogdanm 0:9b334a45a8ff 433 __IO uint32_t SPDR;
bogdanm 0:9b334a45a8ff 434 __IO uint32_t SPCCR;
bogdanm 0:9b334a45a8ff 435 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 436 __IO uint32_t SPINT;
bogdanm 0:9b334a45a8ff 437 } LPC_SPI_TypeDef;
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 0:9b334a45a8ff 440 typedef struct
bogdanm 0:9b334a45a8ff 441 {
bogdanm 0:9b334a45a8ff 442 __IO uint32_t CR0;
bogdanm 0:9b334a45a8ff 443 __IO uint32_t CR1;
bogdanm 0:9b334a45a8ff 444 __IO uint32_t DR;
bogdanm 0:9b334a45a8ff 445 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 446 __IO uint32_t CPSR;
bogdanm 0:9b334a45a8ff 447 __IO uint32_t IMSC;
bogdanm 0:9b334a45a8ff 448 __IO uint32_t RIS;
bogdanm 0:9b334a45a8ff 449 __IO uint32_t MIS;
bogdanm 0:9b334a45a8ff 450 __IO uint32_t ICR;
bogdanm 0:9b334a45a8ff 451 __IO uint32_t DMACR;
bogdanm 0:9b334a45a8ff 452 } LPC_SSP_TypeDef;
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 0:9b334a45a8ff 455 typedef struct
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 __IO uint32_t I2CONSET;
bogdanm 0:9b334a45a8ff 458 __I uint32_t I2STAT;
bogdanm 0:9b334a45a8ff 459 __IO uint32_t I2DAT;
bogdanm 0:9b334a45a8ff 460 __IO uint32_t I2ADR0;
bogdanm 0:9b334a45a8ff 461 __IO uint32_t I2SCLH;
bogdanm 0:9b334a45a8ff 462 __IO uint32_t I2SCLL;
bogdanm 0:9b334a45a8ff 463 __O uint32_t I2CONCLR;
bogdanm 0:9b334a45a8ff 464 __IO uint32_t MMCTRL;
bogdanm 0:9b334a45a8ff 465 __IO uint32_t I2ADR1;
bogdanm 0:9b334a45a8ff 466 __IO uint32_t I2ADR2;
bogdanm 0:9b334a45a8ff 467 __IO uint32_t I2ADR3;
bogdanm 0:9b334a45a8ff 468 __I uint32_t I2DATA_BUFFER;
bogdanm 0:9b334a45a8ff 469 __IO uint32_t I2MASK0;
bogdanm 0:9b334a45a8ff 470 __IO uint32_t I2MASK1;
bogdanm 0:9b334a45a8ff 471 __IO uint32_t I2MASK2;
bogdanm 0:9b334a45a8ff 472 __IO uint32_t I2MASK3;
bogdanm 0:9b334a45a8ff 473 } LPC_I2C_TypeDef;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 476 typedef struct
bogdanm 0:9b334a45a8ff 477 {
bogdanm 0:9b334a45a8ff 478 __IO uint32_t I2SDAO;
bogdanm 0:9b334a45a8ff 479 __IO uint32_t I2SDAI;
bogdanm 0:9b334a45a8ff 480 __O uint32_t I2STXFIFO;
bogdanm 0:9b334a45a8ff 481 __I uint32_t I2SRXFIFO;
bogdanm 0:9b334a45a8ff 482 __I uint32_t I2SSTATE;
bogdanm 0:9b334a45a8ff 483 __IO uint32_t I2SDMA1;
bogdanm 0:9b334a45a8ff 484 __IO uint32_t I2SDMA2;
bogdanm 0:9b334a45a8ff 485 __IO uint32_t I2SIRQ;
bogdanm 0:9b334a45a8ff 486 __IO uint32_t I2STXRATE;
bogdanm 0:9b334a45a8ff 487 __IO uint32_t I2SRXRATE;
bogdanm 0:9b334a45a8ff 488 __IO uint32_t I2STXBITRATE;
bogdanm 0:9b334a45a8ff 489 __IO uint32_t I2SRXBITRATE;
bogdanm 0:9b334a45a8ff 490 __IO uint32_t I2STXMODE;
bogdanm 0:9b334a45a8ff 491 __IO uint32_t I2SRXMODE;
bogdanm 0:9b334a45a8ff 492 } LPC_I2S_TypeDef;
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
bogdanm 0:9b334a45a8ff 495 typedef struct
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 __IO uint32_t RICOMPVAL;
bogdanm 0:9b334a45a8ff 498 __IO uint32_t RIMASK;
bogdanm 0:9b334a45a8ff 499 __IO uint8_t RICTRL;
bogdanm 0:9b334a45a8ff 500 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 501 __IO uint32_t RICOUNTER;
bogdanm 0:9b334a45a8ff 502 } LPC_RIT_TypeDef;
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 0:9b334a45a8ff 505 typedef struct
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 __IO uint8_t ILR;
bogdanm 0:9b334a45a8ff 508 uint8_t RESERVED0[7];
bogdanm 0:9b334a45a8ff 509 __IO uint8_t CCR;
bogdanm 0:9b334a45a8ff 510 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 511 __IO uint8_t CIIR;
bogdanm 0:9b334a45a8ff 512 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 513 __IO uint8_t AMR;
bogdanm 0:9b334a45a8ff 514 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 515 __I uint32_t CTIME0;
bogdanm 0:9b334a45a8ff 516 __I uint32_t CTIME1;
bogdanm 0:9b334a45a8ff 517 __I uint32_t CTIME2;
bogdanm 0:9b334a45a8ff 518 __IO uint8_t SEC;
bogdanm 0:9b334a45a8ff 519 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 520 __IO uint8_t MIN;
bogdanm 0:9b334a45a8ff 521 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 522 __IO uint8_t HOUR;
bogdanm 0:9b334a45a8ff 523 uint8_t RESERVED6[3];
bogdanm 0:9b334a45a8ff 524 __IO uint8_t DOM;
bogdanm 0:9b334a45a8ff 525 uint8_t RESERVED7[3];
bogdanm 0:9b334a45a8ff 526 __IO uint8_t DOW;
bogdanm 0:9b334a45a8ff 527 uint8_t RESERVED8[3];
bogdanm 0:9b334a45a8ff 528 __IO uint16_t DOY;
bogdanm 0:9b334a45a8ff 529 uint16_t RESERVED9;
bogdanm 0:9b334a45a8ff 530 __IO uint8_t MONTH;
bogdanm 0:9b334a45a8ff 531 uint8_t RESERVED10[3];
bogdanm 0:9b334a45a8ff 532 __IO uint16_t YEAR;
bogdanm 0:9b334a45a8ff 533 uint16_t RESERVED11;
bogdanm 0:9b334a45a8ff 534 __IO uint32_t CALIBRATION;
bogdanm 0:9b334a45a8ff 535 __IO uint32_t GPREG0;
bogdanm 0:9b334a45a8ff 536 __IO uint32_t GPREG1;
bogdanm 0:9b334a45a8ff 537 __IO uint32_t GPREG2;
bogdanm 0:9b334a45a8ff 538 __IO uint32_t GPREG3;
bogdanm 0:9b334a45a8ff 539 __IO uint32_t GPREG4;
bogdanm 0:9b334a45a8ff 540 __IO uint8_t RTC_AUXEN;
bogdanm 0:9b334a45a8ff 541 uint8_t RESERVED12[3];
bogdanm 0:9b334a45a8ff 542 __IO uint8_t RTC_AUX;
bogdanm 0:9b334a45a8ff 543 uint8_t RESERVED13[3];
bogdanm 0:9b334a45a8ff 544 __IO uint8_t ALSEC;
bogdanm 0:9b334a45a8ff 545 uint8_t RESERVED14[3];
bogdanm 0:9b334a45a8ff 546 __IO uint8_t ALMIN;
bogdanm 0:9b334a45a8ff 547 uint8_t RESERVED15[3];
bogdanm 0:9b334a45a8ff 548 __IO uint8_t ALHOUR;
bogdanm 0:9b334a45a8ff 549 uint8_t RESERVED16[3];
bogdanm 0:9b334a45a8ff 550 __IO uint8_t ALDOM;
bogdanm 0:9b334a45a8ff 551 uint8_t RESERVED17[3];
bogdanm 0:9b334a45a8ff 552 __IO uint8_t ALDOW;
bogdanm 0:9b334a45a8ff 553 uint8_t RESERVED18[3];
bogdanm 0:9b334a45a8ff 554 __IO uint16_t ALDOY;
bogdanm 0:9b334a45a8ff 555 uint16_t RESERVED19;
bogdanm 0:9b334a45a8ff 556 __IO uint8_t ALMON;
bogdanm 0:9b334a45a8ff 557 uint8_t RESERVED20[3];
bogdanm 0:9b334a45a8ff 558 __IO uint16_t ALYEAR;
bogdanm 0:9b334a45a8ff 559 uint16_t RESERVED21;
bogdanm 0:9b334a45a8ff 560 } LPC_RTC_TypeDef;
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 563 typedef struct
bogdanm 0:9b334a45a8ff 564 {
bogdanm 0:9b334a45a8ff 565 __IO uint8_t WDMOD;
bogdanm 0:9b334a45a8ff 566 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 567 __IO uint32_t WDTC;
bogdanm 0:9b334a45a8ff 568 __O uint8_t WDFEED;
bogdanm 0:9b334a45a8ff 569 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 570 __I uint32_t WDTV;
bogdanm 0:9b334a45a8ff 571 __IO uint32_t WDCLKSEL;
bogdanm 0:9b334a45a8ff 572 } LPC_WDT_TypeDef;
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 0:9b334a45a8ff 575 typedef struct
bogdanm 0:9b334a45a8ff 576 {
bogdanm 0:9b334a45a8ff 577 __IO uint32_t ADCR;
bogdanm 0:9b334a45a8ff 578 __IO uint32_t ADGDR;
bogdanm 0:9b334a45a8ff 579 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 580 __IO uint32_t ADINTEN;
bogdanm 0:9b334a45a8ff 581 __I uint32_t ADDR0;
bogdanm 0:9b334a45a8ff 582 __I uint32_t ADDR1;
bogdanm 0:9b334a45a8ff 583 __I uint32_t ADDR2;
bogdanm 0:9b334a45a8ff 584 __I uint32_t ADDR3;
bogdanm 0:9b334a45a8ff 585 __I uint32_t ADDR4;
bogdanm 0:9b334a45a8ff 586 __I uint32_t ADDR5;
bogdanm 0:9b334a45a8ff 587 __I uint32_t ADDR6;
bogdanm 0:9b334a45a8ff 588 __I uint32_t ADDR7;
bogdanm 0:9b334a45a8ff 589 __I uint32_t ADSTAT;
bogdanm 0:9b334a45a8ff 590 __IO uint32_t ADTRM;
bogdanm 0:9b334a45a8ff 591 } LPC_ADC_TypeDef;
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 0:9b334a45a8ff 594 typedef struct
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 __IO uint32_t DACR;
bogdanm 0:9b334a45a8ff 597 __IO uint32_t DACCTRL;
bogdanm 0:9b334a45a8ff 598 __IO uint16_t DACCNTVAL;
bogdanm 0:9b334a45a8ff 599 } LPC_DAC_TypeDef;
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 0:9b334a45a8ff 602 typedef struct
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 __I uint32_t MCCON;
bogdanm 0:9b334a45a8ff 605 __O uint32_t MCCON_SET;
bogdanm 0:9b334a45a8ff 606 __O uint32_t MCCON_CLR;
bogdanm 0:9b334a45a8ff 607 __I uint32_t MCCAPCON;
bogdanm 0:9b334a45a8ff 608 __O uint32_t MCCAPCON_SET;
bogdanm 0:9b334a45a8ff 609 __O uint32_t MCCAPCON_CLR;
bogdanm 0:9b334a45a8ff 610 __IO uint32_t MCTIM0;
bogdanm 0:9b334a45a8ff 611 __IO uint32_t MCTIM1;
bogdanm 0:9b334a45a8ff 612 __IO uint32_t MCTIM2;
bogdanm 0:9b334a45a8ff 613 __IO uint32_t MCPER0;
bogdanm 0:9b334a45a8ff 614 __IO uint32_t MCPER1;
bogdanm 0:9b334a45a8ff 615 __IO uint32_t MCPER2;
bogdanm 0:9b334a45a8ff 616 __IO uint32_t MCPW0;
bogdanm 0:9b334a45a8ff 617 __IO uint32_t MCPW1;
bogdanm 0:9b334a45a8ff 618 __IO uint32_t MCPW2;
bogdanm 0:9b334a45a8ff 619 __IO uint32_t MCDEADTIME;
bogdanm 0:9b334a45a8ff 620 __IO uint32_t MCCCP;
bogdanm 0:9b334a45a8ff 621 __IO uint32_t MCCR0;
bogdanm 0:9b334a45a8ff 622 __IO uint32_t MCCR1;
bogdanm 0:9b334a45a8ff 623 __IO uint32_t MCCR2;
bogdanm 0:9b334a45a8ff 624 __I uint32_t MCINTEN;
bogdanm 0:9b334a45a8ff 625 __O uint32_t MCINTEN_SET;
bogdanm 0:9b334a45a8ff 626 __O uint32_t MCINTEN_CLR;
bogdanm 0:9b334a45a8ff 627 __I uint32_t MCCNTCON;
bogdanm 0:9b334a45a8ff 628 __O uint32_t MCCNTCON_SET;
bogdanm 0:9b334a45a8ff 629 __O uint32_t MCCNTCON_CLR;
bogdanm 0:9b334a45a8ff 630 __I uint32_t MCINTFLAG;
bogdanm 0:9b334a45a8ff 631 __O uint32_t MCINTFLAG_SET;
bogdanm 0:9b334a45a8ff 632 __O uint32_t MCINTFLAG_CLR;
bogdanm 0:9b334a45a8ff 633 __O uint32_t MCCAP_CLR;
bogdanm 0:9b334a45a8ff 634 } LPC_MCPWM_TypeDef;
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 0:9b334a45a8ff 637 typedef struct
bogdanm 0:9b334a45a8ff 638 {
bogdanm 0:9b334a45a8ff 639 __O uint32_t QEICON;
bogdanm 0:9b334a45a8ff 640 __I uint32_t QEISTAT;
bogdanm 0:9b334a45a8ff 641 __IO uint32_t QEICONF;
bogdanm 0:9b334a45a8ff 642 __I uint32_t QEIPOS;
bogdanm 0:9b334a45a8ff 643 __IO uint32_t QEIMAXPOS;
bogdanm 0:9b334a45a8ff 644 __IO uint32_t CMPOS0;
bogdanm 0:9b334a45a8ff 645 __IO uint32_t CMPOS1;
bogdanm 0:9b334a45a8ff 646 __IO uint32_t CMPOS2;
bogdanm 0:9b334a45a8ff 647 __I uint32_t INXCNT;
bogdanm 0:9b334a45a8ff 648 __IO uint32_t INXCMP;
bogdanm 0:9b334a45a8ff 649 __IO uint32_t QEILOAD;
bogdanm 0:9b334a45a8ff 650 __I uint32_t QEITIME;
bogdanm 0:9b334a45a8ff 651 __I uint32_t QEIVEL;
bogdanm 0:9b334a45a8ff 652 __I uint32_t QEICAP;
bogdanm 0:9b334a45a8ff 653 __IO uint32_t VELCOMP;
bogdanm 0:9b334a45a8ff 654 __IO uint32_t FILTER;
bogdanm 0:9b334a45a8ff 655 uint32_t RESERVED0[998];
bogdanm 0:9b334a45a8ff 656 __O uint32_t QEIIEC;
bogdanm 0:9b334a45a8ff 657 __O uint32_t QEIIES;
bogdanm 0:9b334a45a8ff 658 __I uint32_t QEIINTSTAT;
bogdanm 0:9b334a45a8ff 659 __I uint32_t QEIIE;
bogdanm 0:9b334a45a8ff 660 __O uint32_t QEICLR;
bogdanm 0:9b334a45a8ff 661 __O uint32_t QEISET;
bogdanm 0:9b334a45a8ff 662 } LPC_QEI_TypeDef;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 0:9b334a45a8ff 665 typedef struct
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 0:9b334a45a8ff 668 } LPC_CANAF_RAM_TypeDef;
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 typedef struct /* Acceptance Filter Registers */
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 __IO uint32_t AFMR;
bogdanm 0:9b334a45a8ff 673 __IO uint32_t SFF_sa;
bogdanm 0:9b334a45a8ff 674 __IO uint32_t SFF_GRP_sa;
bogdanm 0:9b334a45a8ff 675 __IO uint32_t EFF_sa;
bogdanm 0:9b334a45a8ff 676 __IO uint32_t EFF_GRP_sa;
bogdanm 0:9b334a45a8ff 677 __IO uint32_t ENDofTable;
bogdanm 0:9b334a45a8ff 678 __I uint32_t LUTerrAd;
bogdanm 0:9b334a45a8ff 679 __I uint32_t LUTerr;
bogdanm 0:9b334a45a8ff 680 __IO uint32_t FCANIE;
bogdanm 0:9b334a45a8ff 681 __IO uint32_t FCANIC0;
bogdanm 0:9b334a45a8ff 682 __IO uint32_t FCANIC1;
bogdanm 0:9b334a45a8ff 683 } LPC_CANAF_TypeDef;
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 typedef struct /* Central Registers */
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 __I uint32_t CANTxSR;
bogdanm 0:9b334a45a8ff 688 __I uint32_t CANRxSR;
bogdanm 0:9b334a45a8ff 689 __I uint32_t CANMSR;
bogdanm 0:9b334a45a8ff 690 } LPC_CANCR_TypeDef;
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 typedef struct /* Controller Registers */
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 __IO uint32_t MOD;
bogdanm 0:9b334a45a8ff 695 __O uint32_t CMR;
bogdanm 0:9b334a45a8ff 696 __IO uint32_t GSR;
bogdanm 0:9b334a45a8ff 697 __I uint32_t ICR;
bogdanm 0:9b334a45a8ff 698 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 699 __IO uint32_t BTR;
bogdanm 0:9b334a45a8ff 700 __IO uint32_t EWL;
bogdanm 0:9b334a45a8ff 701 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 702 __IO uint32_t RFS;
bogdanm 0:9b334a45a8ff 703 __IO uint32_t RID;
bogdanm 0:9b334a45a8ff 704 __IO uint32_t RDA;
bogdanm 0:9b334a45a8ff 705 __IO uint32_t RDB;
bogdanm 0:9b334a45a8ff 706 __IO uint32_t TFI1;
bogdanm 0:9b334a45a8ff 707 __IO uint32_t TID1;
bogdanm 0:9b334a45a8ff 708 __IO uint32_t TDA1;
bogdanm 0:9b334a45a8ff 709 __IO uint32_t TDB1;
bogdanm 0:9b334a45a8ff 710 __IO uint32_t TFI2;
bogdanm 0:9b334a45a8ff 711 __IO uint32_t TID2;
bogdanm 0:9b334a45a8ff 712 __IO uint32_t TDA2;
bogdanm 0:9b334a45a8ff 713 __IO uint32_t TDB2;
bogdanm 0:9b334a45a8ff 714 __IO uint32_t TFI3;
bogdanm 0:9b334a45a8ff 715 __IO uint32_t TID3;
bogdanm 0:9b334a45a8ff 716 __IO uint32_t TDA3;
bogdanm 0:9b334a45a8ff 717 __IO uint32_t TDB3;
bogdanm 0:9b334a45a8ff 718 } LPC_CAN_TypeDef;
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 0:9b334a45a8ff 721 typedef struct /* Common Registers */
bogdanm 0:9b334a45a8ff 722 {
bogdanm 0:9b334a45a8ff 723 __I uint32_t DMACIntStat;
bogdanm 0:9b334a45a8ff 724 __I uint32_t DMACIntTCStat;
bogdanm 0:9b334a45a8ff 725 __O uint32_t DMACIntTCClear;
bogdanm 0:9b334a45a8ff 726 __I uint32_t DMACIntErrStat;
bogdanm 0:9b334a45a8ff 727 __O uint32_t DMACIntErrClr;
bogdanm 0:9b334a45a8ff 728 __I uint32_t DMACRawIntTCStat;
bogdanm 0:9b334a45a8ff 729 __I uint32_t DMACRawIntErrStat;
bogdanm 0:9b334a45a8ff 730 __I uint32_t DMACEnbldChns;
bogdanm 0:9b334a45a8ff 731 __IO uint32_t DMACSoftBReq;
bogdanm 0:9b334a45a8ff 732 __IO uint32_t DMACSoftSReq;
bogdanm 0:9b334a45a8ff 733 __IO uint32_t DMACSoftLBReq;
bogdanm 0:9b334a45a8ff 734 __IO uint32_t DMACSoftLSReq;
bogdanm 0:9b334a45a8ff 735 __IO uint32_t DMACConfig;
bogdanm 0:9b334a45a8ff 736 __IO uint32_t DMACSync;
bogdanm 0:9b334a45a8ff 737 } LPC_GPDMA_TypeDef;
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 typedef struct /* Channel Registers */
bogdanm 0:9b334a45a8ff 740 {
bogdanm 0:9b334a45a8ff 741 __IO uint32_t DMACCSrcAddr;
bogdanm 0:9b334a45a8ff 742 __IO uint32_t DMACCDestAddr;
bogdanm 0:9b334a45a8ff 743 __IO uint32_t DMACCLLI;
bogdanm 0:9b334a45a8ff 744 __IO uint32_t DMACCControl;
bogdanm 0:9b334a45a8ff 745 __IO uint32_t DMACCConfig;
bogdanm 0:9b334a45a8ff 746 } LPC_GPDMACH_TypeDef;
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 0:9b334a45a8ff 749 typedef struct
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 0:9b334a45a8ff 752 __IO uint32_t HcControl;
bogdanm 0:9b334a45a8ff 753 __IO uint32_t HcCommandStatus;
bogdanm 0:9b334a45a8ff 754 __IO uint32_t HcInterruptStatus;
bogdanm 0:9b334a45a8ff 755 __IO uint32_t HcInterruptEnable;
bogdanm 0:9b334a45a8ff 756 __IO uint32_t HcInterruptDisable;
bogdanm 0:9b334a45a8ff 757 __IO uint32_t HcHCCA;
bogdanm 0:9b334a45a8ff 758 __I uint32_t HcPeriodCurrentED;
bogdanm 0:9b334a45a8ff 759 __IO uint32_t HcControlHeadED;
bogdanm 0:9b334a45a8ff 760 __IO uint32_t HcControlCurrentED;
bogdanm 0:9b334a45a8ff 761 __IO uint32_t HcBulkHeadED;
bogdanm 0:9b334a45a8ff 762 __IO uint32_t HcBulkCurrentED;
bogdanm 0:9b334a45a8ff 763 __I uint32_t HcDoneHead;
bogdanm 0:9b334a45a8ff 764 __IO uint32_t HcFmInterval;
bogdanm 0:9b334a45a8ff 765 __I uint32_t HcFmRemaining;
bogdanm 0:9b334a45a8ff 766 __I uint32_t HcFmNumber;
bogdanm 0:9b334a45a8ff 767 __IO uint32_t HcPeriodicStart;
bogdanm 0:9b334a45a8ff 768 __IO uint32_t HcLSTreshold;
bogdanm 0:9b334a45a8ff 769 __IO uint32_t HcRhDescriptorA;
bogdanm 0:9b334a45a8ff 770 __IO uint32_t HcRhDescriptorB;
bogdanm 0:9b334a45a8ff 771 __IO uint32_t HcRhStatus;
bogdanm 0:9b334a45a8ff 772 __IO uint32_t HcRhPortStatus1;
bogdanm 0:9b334a45a8ff 773 __IO uint32_t HcRhPortStatus2;
bogdanm 0:9b334a45a8ff 774 uint32_t RESERVED0[40];
bogdanm 0:9b334a45a8ff 775 __I uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 0:9b334a45a8ff 778 __IO uint32_t OTGIntEn;
bogdanm 0:9b334a45a8ff 779 __O uint32_t OTGIntSet;
bogdanm 0:9b334a45a8ff 780 __O uint32_t OTGIntClr;
bogdanm 0:9b334a45a8ff 781 __IO uint32_t OTGStCtrl;
bogdanm 0:9b334a45a8ff 782 __IO uint32_t OTGTmr;
bogdanm 0:9b334a45a8ff 783 uint32_t RESERVED1[58];
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 0:9b334a45a8ff 786 __IO uint32_t USBDevIntEn;
bogdanm 0:9b334a45a8ff 787 __O uint32_t USBDevIntClr;
bogdanm 0:9b334a45a8ff 788 __O uint32_t USBDevIntSet;
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 0:9b334a45a8ff 791 __I uint32_t USBCmdData;
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 0:9b334a45a8ff 794 __O uint32_t USBTxData;
bogdanm 0:9b334a45a8ff 795 __I uint32_t USBRxPLen;
bogdanm 0:9b334a45a8ff 796 __O uint32_t USBTxPLen;
bogdanm 0:9b334a45a8ff 797 __IO uint32_t USBCtrl;
bogdanm 0:9b334a45a8ff 798 __O uint32_t USBDevIntPri;
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 0:9b334a45a8ff 801 __IO uint32_t USBEpIntEn;
bogdanm 0:9b334a45a8ff 802 __O uint32_t USBEpIntClr;
bogdanm 0:9b334a45a8ff 803 __O uint32_t USBEpIntSet;
bogdanm 0:9b334a45a8ff 804 __O uint32_t USBEpIntPri;
bogdanm 0:9b334a45a8ff 805
bogdanm 0:9b334a45a8ff 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 0:9b334a45a8ff 807 __O uint32_t USBEpInd;
bogdanm 0:9b334a45a8ff 808 __IO uint32_t USBMaxPSize;
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 0:9b334a45a8ff 811 __O uint32_t USBDMARClr;
bogdanm 0:9b334a45a8ff 812 __O uint32_t USBDMARSet;
bogdanm 0:9b334a45a8ff 813 uint32_t RESERVED2[9];
bogdanm 0:9b334a45a8ff 814 __IO uint32_t USBUDCAH;
bogdanm 0:9b334a45a8ff 815 __I uint32_t USBEpDMASt;
bogdanm 0:9b334a45a8ff 816 __O uint32_t USBEpDMAEn;
bogdanm 0:9b334a45a8ff 817 __O uint32_t USBEpDMADis;
bogdanm 0:9b334a45a8ff 818 __I uint32_t USBDMAIntSt;
bogdanm 0:9b334a45a8ff 819 __IO uint32_t USBDMAIntEn;
bogdanm 0:9b334a45a8ff 820 uint32_t RESERVED3[2];
bogdanm 0:9b334a45a8ff 821 __I uint32_t USBEoTIntSt;
bogdanm 0:9b334a45a8ff 822 __O uint32_t USBEoTIntClr;
bogdanm 0:9b334a45a8ff 823 __O uint32_t USBEoTIntSet;
bogdanm 0:9b334a45a8ff 824 __I uint32_t USBNDDRIntSt;
bogdanm 0:9b334a45a8ff 825 __O uint32_t USBNDDRIntClr;
bogdanm 0:9b334a45a8ff 826 __O uint32_t USBNDDRIntSet;
bogdanm 0:9b334a45a8ff 827 __I uint32_t USBSysErrIntSt;
bogdanm 0:9b334a45a8ff 828 __O uint32_t USBSysErrIntClr;
bogdanm 0:9b334a45a8ff 829 __O uint32_t USBSysErrIntSet;
bogdanm 0:9b334a45a8ff 830 uint32_t RESERVED4[15];
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 union {
bogdanm 0:9b334a45a8ff 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 0:9b334a45a8ff 834 __O uint32_t I2C_TX;
bogdanm 0:9b334a45a8ff 835 };
bogdanm 0:9b334a45a8ff 836 __I uint32_t I2C_STS;
bogdanm 0:9b334a45a8ff 837 __IO uint32_t I2C_CTL;
bogdanm 0:9b334a45a8ff 838 __IO uint32_t I2C_CLKHI;
bogdanm 0:9b334a45a8ff 839 __O uint32_t I2C_CLKLO;
bogdanm 0:9b334a45a8ff 840 uint32_t RESERVED5[824];
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 union {
bogdanm 0:9b334a45a8ff 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 0:9b334a45a8ff 844 __IO uint32_t OTGClkCtrl;
bogdanm 0:9b334a45a8ff 845 };
bogdanm 0:9b334a45a8ff 846 union {
bogdanm 0:9b334a45a8ff 847 __I uint32_t USBClkSt;
bogdanm 0:9b334a45a8ff 848 __I uint32_t OTGClkSt;
bogdanm 0:9b334a45a8ff 849 };
bogdanm 0:9b334a45a8ff 850 } LPC_USB_TypeDef;
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 0:9b334a45a8ff 853 typedef struct
bogdanm 0:9b334a45a8ff 854 {
bogdanm 0:9b334a45a8ff 855 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 0:9b334a45a8ff 856 __IO uint32_t MAC2;
bogdanm 0:9b334a45a8ff 857 __IO uint32_t IPGT;
bogdanm 0:9b334a45a8ff 858 __IO uint32_t IPGR;
bogdanm 0:9b334a45a8ff 859 __IO uint32_t CLRT;
bogdanm 0:9b334a45a8ff 860 __IO uint32_t MAXF;
bogdanm 0:9b334a45a8ff 861 __IO uint32_t SUPP;
bogdanm 0:9b334a45a8ff 862 __IO uint32_t TEST;
bogdanm 0:9b334a45a8ff 863 __IO uint32_t MCFG;
bogdanm 0:9b334a45a8ff 864 __IO uint32_t MCMD;
bogdanm 0:9b334a45a8ff 865 __IO uint32_t MADR;
bogdanm 0:9b334a45a8ff 866 __O uint32_t MWTD;
bogdanm 0:9b334a45a8ff 867 __I uint32_t MRDD;
bogdanm 0:9b334a45a8ff 868 __I uint32_t MIND;
bogdanm 0:9b334a45a8ff 869 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 870 __IO uint32_t SA0;
bogdanm 0:9b334a45a8ff 871 __IO uint32_t SA1;
bogdanm 0:9b334a45a8ff 872 __IO uint32_t SA2;
bogdanm 0:9b334a45a8ff 873 uint32_t RESERVED1[45];
bogdanm 0:9b334a45a8ff 874 __IO uint32_t Command; /* Control Registers */
bogdanm 0:9b334a45a8ff 875 __I uint32_t Status;
bogdanm 0:9b334a45a8ff 876 __IO uint32_t RxDescriptor;
bogdanm 0:9b334a45a8ff 877 __IO uint32_t RxStatus;
bogdanm 0:9b334a45a8ff 878 __IO uint32_t RxDescriptorNumber;
bogdanm 0:9b334a45a8ff 879 __I uint32_t RxProduceIndex;
bogdanm 0:9b334a45a8ff 880 __IO uint32_t RxConsumeIndex;
bogdanm 0:9b334a45a8ff 881 __IO uint32_t TxDescriptor;
bogdanm 0:9b334a45a8ff 882 __IO uint32_t TxStatus;
bogdanm 0:9b334a45a8ff 883 __IO uint32_t TxDescriptorNumber;
bogdanm 0:9b334a45a8ff 884 __IO uint32_t TxProduceIndex;
bogdanm 0:9b334a45a8ff 885 __I uint32_t TxConsumeIndex;
bogdanm 0:9b334a45a8ff 886 uint32_t RESERVED2[10];
bogdanm 0:9b334a45a8ff 887 __I uint32_t TSV0;
bogdanm 0:9b334a45a8ff 888 __I uint32_t TSV1;
bogdanm 0:9b334a45a8ff 889 __I uint32_t RSV;
bogdanm 0:9b334a45a8ff 890 uint32_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 891 __IO uint32_t FlowControlCounter;
bogdanm 0:9b334a45a8ff 892 __I uint32_t FlowControlStatus;
bogdanm 0:9b334a45a8ff 893 uint32_t RESERVED4[34];
bogdanm 0:9b334a45a8ff 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 0:9b334a45a8ff 895 __IO uint32_t RxFilterWoLStatus;
bogdanm 0:9b334a45a8ff 896 __IO uint32_t RxFilterWoLClear;
bogdanm 0:9b334a45a8ff 897 uint32_t RESERVED5;
bogdanm 0:9b334a45a8ff 898 __IO uint32_t HashFilterL;
bogdanm 0:9b334a45a8ff 899 __IO uint32_t HashFilterH;
bogdanm 0:9b334a45a8ff 900 uint32_t RESERVED6[882];
bogdanm 0:9b334a45a8ff 901 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 0:9b334a45a8ff 902 __IO uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 903 __O uint32_t IntClear;
bogdanm 0:9b334a45a8ff 904 __O uint32_t IntSet;
bogdanm 0:9b334a45a8ff 905 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 906 __IO uint32_t PowerDown;
bogdanm 0:9b334a45a8ff 907 uint32_t RESERVED8;
bogdanm 0:9b334a45a8ff 908 __IO uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 909 } LPC_EMAC_TypeDef;
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 912 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 913 #endif
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915
bogdanm 0:9b334a45a8ff 916 /******************************************************************************/
bogdanm 0:9b334a45a8ff 917 /* Peripheral memory map */
bogdanm 0:9b334a45a8ff 918 /******************************************************************************/
bogdanm 0:9b334a45a8ff 919 /* Base addresses */
bogdanm 0:9b334a45a8ff 920 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 0:9b334a45a8ff 921 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 0:9b334a45a8ff 922 #define LPC_GPIO_BASE (0x2009C000UL)
bogdanm 0:9b334a45a8ff 923 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 924 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 0:9b334a45a8ff 925 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 0:9b334a45a8ff 926 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* APB0 peripherals */
bogdanm 0:9b334a45a8ff 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 0:9b334a45a8ff 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 0:9b334a45a8ff 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 0:9b334a45a8ff 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 0:9b334a45a8ff 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 0:9b334a45a8ff 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 0:9b334a45a8ff 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 0:9b334a45a8ff 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 0:9b334a45a8ff 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 0:9b334a45a8ff 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 0:9b334a45a8ff 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 0:9b334a45a8ff 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 0:9b334a45a8ff 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 0:9b334a45a8ff 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 0:9b334a45a8ff 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 0:9b334a45a8ff 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 0:9b334a45a8ff 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 0:9b334a45a8ff 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 0:9b334a45a8ff 948
bogdanm 0:9b334a45a8ff 949 /* APB1 peripherals */
bogdanm 0:9b334a45a8ff 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 0:9b334a45a8ff 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 0:9b334a45a8ff 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 0:9b334a45a8ff 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 0:9b334a45a8ff 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 0:9b334a45a8ff 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 0:9b334a45a8ff 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 0:9b334a45a8ff 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 0:9b334a45a8ff 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
bogdanm 0:9b334a45a8ff 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 0:9b334a45a8ff 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 0:9b334a45a8ff 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 0:9b334a45a8ff 962
bogdanm 0:9b334a45a8ff 963 /* AHB peripherals */
bogdanm 0:9b334a45a8ff 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 0:9b334a45a8ff 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
bogdanm 0:9b334a45a8ff 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
bogdanm 0:9b334a45a8ff 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
bogdanm 0:9b334a45a8ff 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
bogdanm 0:9b334a45a8ff 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
bogdanm 0:9b334a45a8ff 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
bogdanm 0:9b334a45a8ff 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
bogdanm 0:9b334a45a8ff 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
bogdanm 0:9b334a45a8ff 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 /* GPIOs */
bogdanm 0:9b334a45a8ff 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
bogdanm 0:9b334a45a8ff 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
bogdanm 0:9b334a45a8ff 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
bogdanm 0:9b334a45a8ff 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
bogdanm 0:9b334a45a8ff 982
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /******************************************************************************/
bogdanm 0:9b334a45a8ff 985 /* Peripheral declaration */
bogdanm 0:9b334a45a8ff 986 /******************************************************************************/
bogdanm 0:9b334a45a8ff 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 0:9b334a45a8ff 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 0:9b334a45a8ff 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 0:9b334a45a8ff 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 0:9b334a45a8ff 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 0:9b334a45a8ff 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 0:9b334a45a8ff 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 0:9b334a45a8ff 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 0:9b334a45a8ff 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 0:9b334a45a8ff 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 0:9b334a45a8ff 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 0:9b334a45a8ff 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
bogdanm 0:9b334a45a8ff 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
bogdanm 0:9b334a45a8ff 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 0:9b334a45a8ff 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 0:9b334a45a8ff 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 0:9b334a45a8ff 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 0:9b334a45a8ff 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 0:9b334a45a8ff 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 0:9b334a45a8ff 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 0:9b334a45a8ff 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 0:9b334a45a8ff 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
bogdanm 0:9b334a45a8ff 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 0:9b334a45a8ff 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 0:9b334a45a8ff 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
bogdanm 0:9b334a45a8ff 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 0:9b334a45a8ff 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 0:9b334a45a8ff 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 0:9b334a45a8ff 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 0:9b334a45a8ff 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 0:9b334a45a8ff 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 0:9b334a45a8ff 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 0:9b334a45a8ff 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 0:9b334a45a8ff 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 0:9b334a45a8ff 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 0:9b334a45a8ff 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 0:9b334a45a8ff 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 0:9b334a45a8ff 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 0:9b334a45a8ff 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 0:9b334a45a8ff 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 0:9b334a45a8ff 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 0:9b334a45a8ff 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 0:9b334a45a8ff 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 0:9b334a45a8ff 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 0:9b334a45a8ff 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 0:9b334a45a8ff 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 0:9b334a45a8ff 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 #endif // __LPC17xx_H__