u-blox / Mbed 2 deprecated IBMIoTClientEthernetExample

Port to C027 (using AppShield and Ethernet)

Dependencies:   C12832 EthernetInterface LM75B MMA7660 MQTT mbed-rtos mbed

Fork of IBMIoTClientEthernetExample by IBM Watson IoT

EthernetInterface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c@6:37b6d0d56190, 2014-08-20 (annotated)

Committer:
samdanbury
Date:
Wed Aug 20 12:45:14 2014 +0000
Revision:
6:37b6d0d56190
Code completely changed to improve the structure, flow and memory usage of the application

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samdanbury 6:37b6d0d56190 1 /**********************************************************************
samdanbury 6:37b6d0d56190 2 * $Id$ lpc17_emac.c 2011-11-20
samdanbury 6:37b6d0d56190 3 *//**
samdanbury 6:37b6d0d56190 4 * @file lpc17_emac.c
samdanbury 6:37b6d0d56190 5 * @brief LPC17 ethernet driver for LWIP
samdanbury 6:37b6d0d56190 6 * @version 1.0
samdanbury 6:37b6d0d56190 7 * @date 20. Nov. 2011
samdanbury 6:37b6d0d56190 8 * @author NXP MCU SW Application Team
samdanbury 6:37b6d0d56190 9 *
samdanbury 6:37b6d0d56190 10 * Copyright(C) 2011, NXP Semiconductor
samdanbury 6:37b6d0d56190 11 * All rights reserved.
samdanbury 6:37b6d0d56190 12 *
samdanbury 6:37b6d0d56190 13 ***********************************************************************
samdanbury 6:37b6d0d56190 14 * Software that is described herein is for illustrative purposes only
samdanbury 6:37b6d0d56190 15 * which provides customers with programming information regarding the
samdanbury 6:37b6d0d56190 16 * products. This software is supplied "AS IS" without any warranties.
samdanbury 6:37b6d0d56190 17 * NXP Semiconductors assumes no responsibility or liability for the
samdanbury 6:37b6d0d56190 18 * use of the software, conveys no license or title under any patent,
samdanbury 6:37b6d0d56190 19 * copyright, or mask work right to the product. NXP Semiconductors
samdanbury 6:37b6d0d56190 20 * reserves the right to make changes in the software without
samdanbury 6:37b6d0d56190 21 * notification. NXP Semiconductors also make no representation or
samdanbury 6:37b6d0d56190 22 * warranty that such application will be suitable for the specified
samdanbury 6:37b6d0d56190 23 * use without further testing or modification.
samdanbury 6:37b6d0d56190 24 **********************************************************************/
samdanbury 6:37b6d0d56190 25
samdanbury 6:37b6d0d56190 26 #include "lwip/opt.h"
samdanbury 6:37b6d0d56190 27 #include "lwip/sys.h"
samdanbury 6:37b6d0d56190 28 #include "lwip/def.h"
samdanbury 6:37b6d0d56190 29 #include "lwip/mem.h"
samdanbury 6:37b6d0d56190 30 #include "lwip/pbuf.h"
samdanbury 6:37b6d0d56190 31 #include "lwip/stats.h"
samdanbury 6:37b6d0d56190 32 #include "lwip/snmp.h"
samdanbury 6:37b6d0d56190 33 #include "netif/etharp.h"
samdanbury 6:37b6d0d56190 34 #include "netif/ppp_oe.h"
samdanbury 6:37b6d0d56190 35
samdanbury 6:37b6d0d56190 36 #include "lpc17xx_emac.h"
samdanbury 6:37b6d0d56190 37 #include "eth_arch.h"
samdanbury 6:37b6d0d56190 38 #include "lpc_emac_config.h"
samdanbury 6:37b6d0d56190 39 #include "lpc_phy.h"
samdanbury 6:37b6d0d56190 40 #include "sys_arch.h"
samdanbury 6:37b6d0d56190 41
samdanbury 6:37b6d0d56190 42 #include "mbed_interface.h"
samdanbury 6:37b6d0d56190 43 #include <string.h>
samdanbury 6:37b6d0d56190 44
samdanbury 6:37b6d0d56190 45 #ifndef LPC_EMAC_RMII
samdanbury 6:37b6d0d56190 46 #error LPC_EMAC_RMII is not defined!
samdanbury 6:37b6d0d56190 47 #endif
samdanbury 6:37b6d0d56190 48
samdanbury 6:37b6d0d56190 49 #if LPC_NUM_BUFF_TXDESCS < 2
samdanbury 6:37b6d0d56190 50 #error LPC_NUM_BUFF_TXDESCS must be at least 2
samdanbury 6:37b6d0d56190 51 #endif
samdanbury 6:37b6d0d56190 52
samdanbury 6:37b6d0d56190 53 #if LPC_NUM_BUFF_RXDESCS < 3
samdanbury 6:37b6d0d56190 54 #error LPC_NUM_BUFF_RXDESCS must be at least 3
samdanbury 6:37b6d0d56190 55 #endif
samdanbury 6:37b6d0d56190 56
samdanbury 6:37b6d0d56190 57 /** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
samdanbury 6:37b6d0d56190 58 * @ingroup lwip_emac
samdanbury 6:37b6d0d56190 59 *
samdanbury 6:37b6d0d56190 60 * @{
samdanbury 6:37b6d0d56190 61 */
samdanbury 6:37b6d0d56190 62
samdanbury 6:37b6d0d56190 63 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 64 /** \brief Driver transmit and receive thread priorities
samdanbury 6:37b6d0d56190 65 *
samdanbury 6:37b6d0d56190 66 * Thread priorities for receive thread and TX cleanup thread. Alter
samdanbury 6:37b6d0d56190 67 * to prioritize receive or transmit bandwidth. In a heavily loaded
samdanbury 6:37b6d0d56190 68 * system or with LEIP_DEBUG enabled, the priorities might be better
samdanbury 6:37b6d0d56190 69 * the same. */
samdanbury 6:37b6d0d56190 70 #define RX_PRIORITY (osPriorityNormal)
samdanbury 6:37b6d0d56190 71 #define TX_PRIORITY (osPriorityNormal)
samdanbury 6:37b6d0d56190 72
samdanbury 6:37b6d0d56190 73 /** \brief Debug output formatter lock define
samdanbury 6:37b6d0d56190 74 *
samdanbury 6:37b6d0d56190 75 * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
samdanbury 6:37b6d0d56190 76 * define will allow RX debug messages to not interleave with the
samdanbury 6:37b6d0d56190 77 * TX messages (so they are actually readable). Not enabling this
samdanbury 6:37b6d0d56190 78 * define when the system is under load will cause the output to
samdanbury 6:37b6d0d56190 79 * be unreadable. There is a small tradeoff in performance for this
samdanbury 6:37b6d0d56190 80 * so use it only for debug. */
samdanbury 6:37b6d0d56190 81 //#define LOCK_RX_THREAD
samdanbury 6:37b6d0d56190 82
samdanbury 6:37b6d0d56190 83 /** \brief Receive group interrupts
samdanbury 6:37b6d0d56190 84 */
samdanbury 6:37b6d0d56190 85 #define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
samdanbury 6:37b6d0d56190 86
samdanbury 6:37b6d0d56190 87 /** \brief Transmit group interrupts
samdanbury 6:37b6d0d56190 88 */
samdanbury 6:37b6d0d56190 89 #define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
samdanbury 6:37b6d0d56190 90
samdanbury 6:37b6d0d56190 91 /** \brief Signal used for ethernet ISR to signal packet_rx() thread.
samdanbury 6:37b6d0d56190 92 */
samdanbury 6:37b6d0d56190 93 #define RX_SIGNAL 1
samdanbury 6:37b6d0d56190 94
samdanbury 6:37b6d0d56190 95 #else
samdanbury 6:37b6d0d56190 96 #define RXINTGROUP 0
samdanbury 6:37b6d0d56190 97 #define TXINTGROUP 0
samdanbury 6:37b6d0d56190 98 #endif
samdanbury 6:37b6d0d56190 99
samdanbury 6:37b6d0d56190 100 /** \brief Structure of a TX/RX descriptor
samdanbury 6:37b6d0d56190 101 */
samdanbury 6:37b6d0d56190 102 typedef struct
samdanbury 6:37b6d0d56190 103 {
samdanbury 6:37b6d0d56190 104 volatile u32_t packet; /**< Pointer to buffer */
samdanbury 6:37b6d0d56190 105 volatile u32_t control; /**< Control word */
samdanbury 6:37b6d0d56190 106 } LPC_TXRX_DESC_T;
samdanbury 6:37b6d0d56190 107
samdanbury 6:37b6d0d56190 108 /** \brief Structure of a RX status entry
samdanbury 6:37b6d0d56190 109 */
samdanbury 6:37b6d0d56190 110 typedef struct
samdanbury 6:37b6d0d56190 111 {
samdanbury 6:37b6d0d56190 112 volatile u32_t statusinfo; /**< RX status word */
samdanbury 6:37b6d0d56190 113 volatile u32_t statushashcrc; /**< RX hash CRC */
samdanbury 6:37b6d0d56190 114 } LPC_TXRX_STATUS_T;
samdanbury 6:37b6d0d56190 115
samdanbury 6:37b6d0d56190 116 /* LPC EMAC driver data structure */
samdanbury 6:37b6d0d56190 117 struct lpc_enetdata {
samdanbury 6:37b6d0d56190 118 /* prxs must be 8 byte aligned! */
samdanbury 6:37b6d0d56190 119 LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
samdanbury 6:37b6d0d56190 120 struct netif *netif; /**< Reference back to LWIP parent netif */
samdanbury 6:37b6d0d56190 121 LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
samdanbury 6:37b6d0d56190 122 LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
samdanbury 6:37b6d0d56190 123 LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
samdanbury 6:37b6d0d56190 124 struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
samdanbury 6:37b6d0d56190 125 u32_t rx_fill_desc_index; /**< RX descriptor next available index */
samdanbury 6:37b6d0d56190 126 volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
samdanbury 6:37b6d0d56190 127 struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
samdanbury 6:37b6d0d56190 128 u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
samdanbury 6:37b6d0d56190 129 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 130 sys_thread_t RxThread; /**< RX receive thread data object pointer */
samdanbury 6:37b6d0d56190 131 sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */
samdanbury 6:37b6d0d56190 132 sys_mutex_t TXLockMutex; /**< TX critical section mutex */
samdanbury 6:37b6d0d56190 133 sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
samdanbury 6:37b6d0d56190 134 #endif
samdanbury 6:37b6d0d56190 135 };
samdanbury 6:37b6d0d56190 136
samdanbury 6:37b6d0d56190 137 #if defined(TARGET_LPC4088)
samdanbury 6:37b6d0d56190 138 # if defined (__ICCARM__)
samdanbury 6:37b6d0d56190 139 # define ETHMEM_SECTION
samdanbury 6:37b6d0d56190 140 # elif defined(TOOLCHAIN_GCC_CR)
samdanbury 6:37b6d0d56190 141 # define ETHMEM_SECTION __attribute__((section(".data.$RamPeriph32"), aligned))
samdanbury 6:37b6d0d56190 142 # else
samdanbury 6:37b6d0d56190 143 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
samdanbury 6:37b6d0d56190 144 # endif
samdanbury 6:37b6d0d56190 145 #elif defined(TARGET_LPC1768)
samdanbury 6:37b6d0d56190 146 # if defined(TOOLCHAIN_GCC_ARM)
samdanbury 6:37b6d0d56190 147 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
samdanbury 6:37b6d0d56190 148 # endif
samdanbury 6:37b6d0d56190 149 #endif
samdanbury 6:37b6d0d56190 150
samdanbury 6:37b6d0d56190 151 #ifndef ETHMEM_SECTION
samdanbury 6:37b6d0d56190 152 #define ETHMEM_SECTION ALIGNED(8)
samdanbury 6:37b6d0d56190 153 #endif
samdanbury 6:37b6d0d56190 154
samdanbury 6:37b6d0d56190 155 /** \brief LPC EMAC driver work data
samdanbury 6:37b6d0d56190 156 */
samdanbury 6:37b6d0d56190 157 ETHMEM_SECTION struct lpc_enetdata lpc_enetdata;
samdanbury 6:37b6d0d56190 158
samdanbury 6:37b6d0d56190 159 /** \brief Queues a pbuf into the RX descriptor list
samdanbury 6:37b6d0d56190 160 *
samdanbury 6:37b6d0d56190 161 * \param[in] lpc_enetif Pointer to the drvier data structure
samdanbury 6:37b6d0d56190 162 * \param[in] p Pointer to pbuf to queue
samdanbury 6:37b6d0d56190 163 */
samdanbury 6:37b6d0d56190 164 static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
samdanbury 6:37b6d0d56190 165 {
samdanbury 6:37b6d0d56190 166 u32_t idx;
samdanbury 6:37b6d0d56190 167
samdanbury 6:37b6d0d56190 168 /* Get next free descriptor index */
samdanbury 6:37b6d0d56190 169 idx = lpc_enetif->rx_fill_desc_index;
samdanbury 6:37b6d0d56190 170
samdanbury 6:37b6d0d56190 171 /* Setup descriptor and clear statuses */
samdanbury 6:37b6d0d56190 172 lpc_enetif->prxd[idx].control = EMAC_RCTRL_INT | ((u32_t) (p->len - 1));
samdanbury 6:37b6d0d56190 173 lpc_enetif->prxd[idx].packet = (u32_t) p->payload;
samdanbury 6:37b6d0d56190 174 lpc_enetif->prxs[idx].statusinfo = 0xFFFFFFFF;
samdanbury 6:37b6d0d56190 175 lpc_enetif->prxs[idx].statushashcrc = 0xFFFFFFFF;
samdanbury 6:37b6d0d56190 176
samdanbury 6:37b6d0d56190 177 /* Save pbuf pointer for push to network layer later */
samdanbury 6:37b6d0d56190 178 lpc_enetif->rxb[idx] = p;
samdanbury 6:37b6d0d56190 179
samdanbury 6:37b6d0d56190 180 /* Wrap at end of descriptor list */
samdanbury 6:37b6d0d56190 181 idx++;
samdanbury 6:37b6d0d56190 182 if (idx >= LPC_NUM_BUFF_RXDESCS)
samdanbury 6:37b6d0d56190 183 idx = 0;
samdanbury 6:37b6d0d56190 184
samdanbury 6:37b6d0d56190 185 /* Queue descriptor(s) */
samdanbury 6:37b6d0d56190 186 lpc_enetif->rx_free_descs -= 1;
samdanbury 6:37b6d0d56190 187 lpc_enetif->rx_fill_desc_index = idx;
samdanbury 6:37b6d0d56190 188 LPC_EMAC->RxConsumeIndex = idx;
samdanbury 6:37b6d0d56190 189
samdanbury 6:37b6d0d56190 190 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 191 ("lpc_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p,
samdanbury 6:37b6d0d56190 192 lpc_enetif->rx_free_descs));
samdanbury 6:37b6d0d56190 193 }
samdanbury 6:37b6d0d56190 194
samdanbury 6:37b6d0d56190 195 /** \brief Attempt to allocate and requeue a new pbuf for RX
samdanbury 6:37b6d0d56190 196 *
samdanbury 6:37b6d0d56190 197 * \param[in] netif Pointer to the netif structure
samdanbury 6:37b6d0d56190 198 * \returns 1 if a packet was allocated and requeued, otherwise 0
samdanbury 6:37b6d0d56190 199 */
samdanbury 6:37b6d0d56190 200 s32_t lpc_rx_queue(struct netif *netif)
samdanbury 6:37b6d0d56190 201 {
samdanbury 6:37b6d0d56190 202 struct lpc_enetdata *lpc_enetif = netif->state;
samdanbury 6:37b6d0d56190 203 struct pbuf *p;
samdanbury 6:37b6d0d56190 204 s32_t queued = 0;
samdanbury 6:37b6d0d56190 205
samdanbury 6:37b6d0d56190 206 /* Attempt to requeue as many packets as possible */
samdanbury 6:37b6d0d56190 207 while (lpc_enetif->rx_free_descs > 0) {
samdanbury 6:37b6d0d56190 208 /* Allocate a pbuf from the pool. We need to allocate at the
samdanbury 6:37b6d0d56190 209 maximum size as we don't know the size of the yet to be
samdanbury 6:37b6d0d56190 210 received packet. */
samdanbury 6:37b6d0d56190 211 p = pbuf_alloc(PBUF_RAW, (u16_t) EMAC_ETH_MAX_FLEN, PBUF_RAM);
samdanbury 6:37b6d0d56190 212 if (p == NULL) {
samdanbury 6:37b6d0d56190 213 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 214 ("lpc_rx_queue: could not allocate RX pbuf (free desc=%d)\n",
samdanbury 6:37b6d0d56190 215 lpc_enetif->rx_free_descs));
samdanbury 6:37b6d0d56190 216 return queued;
samdanbury 6:37b6d0d56190 217 }
samdanbury 6:37b6d0d56190 218
samdanbury 6:37b6d0d56190 219 /* pbufs allocated from the RAM pool should be non-chained. */
samdanbury 6:37b6d0d56190 220 LWIP_ASSERT("lpc_rx_queue: pbuf is not contiguous (chained)",
samdanbury 6:37b6d0d56190 221 pbuf_clen(p) <= 1);
samdanbury 6:37b6d0d56190 222
samdanbury 6:37b6d0d56190 223 /* Queue packet */
samdanbury 6:37b6d0d56190 224 lpc_rxqueue_pbuf(lpc_enetif, p);
samdanbury 6:37b6d0d56190 225
samdanbury 6:37b6d0d56190 226 /* Update queued count */
samdanbury 6:37b6d0d56190 227 queued++;
samdanbury 6:37b6d0d56190 228 }
samdanbury 6:37b6d0d56190 229
samdanbury 6:37b6d0d56190 230 return queued;
samdanbury 6:37b6d0d56190 231 }
samdanbury 6:37b6d0d56190 232
samdanbury 6:37b6d0d56190 233 /** \brief Sets up the RX descriptor ring buffers.
samdanbury 6:37b6d0d56190 234 *
samdanbury 6:37b6d0d56190 235 * This function sets up the descriptor list used for receive packets.
samdanbury 6:37b6d0d56190 236 *
samdanbury 6:37b6d0d56190 237 * \param[in] lpc_enetif Pointer to driver data structure
samdanbury 6:37b6d0d56190 238 * \returns Always returns ERR_OK
samdanbury 6:37b6d0d56190 239 */
samdanbury 6:37b6d0d56190 240 static err_t lpc_rx_setup(struct lpc_enetdata *lpc_enetif)
samdanbury 6:37b6d0d56190 241 {
samdanbury 6:37b6d0d56190 242 /* Setup pointers to RX structures */
samdanbury 6:37b6d0d56190 243 LPC_EMAC->RxDescriptor = (u32_t) &lpc_enetif->prxd[0];
samdanbury 6:37b6d0d56190 244 LPC_EMAC->RxStatus = (u32_t) &lpc_enetif->prxs[0];
samdanbury 6:37b6d0d56190 245 LPC_EMAC->RxDescriptorNumber = LPC_NUM_BUFF_RXDESCS - 1;
samdanbury 6:37b6d0d56190 246
samdanbury 6:37b6d0d56190 247 lpc_enetif->rx_free_descs = LPC_NUM_BUFF_RXDESCS;
samdanbury 6:37b6d0d56190 248 lpc_enetif->rx_fill_desc_index = 0;
samdanbury 6:37b6d0d56190 249
samdanbury 6:37b6d0d56190 250 /* Build RX buffer and descriptors */
samdanbury 6:37b6d0d56190 251 lpc_rx_queue(lpc_enetif->netif);
samdanbury 6:37b6d0d56190 252
samdanbury 6:37b6d0d56190 253 return ERR_OK;
samdanbury 6:37b6d0d56190 254 }
samdanbury 6:37b6d0d56190 255
samdanbury 6:37b6d0d56190 256 /** \brief Allocates a pbuf and returns the data from the incoming packet.
samdanbury 6:37b6d0d56190 257 *
samdanbury 6:37b6d0d56190 258 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 259 * \return a pbuf filled with the received packet (including MAC header)
samdanbury 6:37b6d0d56190 260 * NULL on memory error
samdanbury 6:37b6d0d56190 261 */
samdanbury 6:37b6d0d56190 262 static struct pbuf *lpc_low_level_input(struct netif *netif)
samdanbury 6:37b6d0d56190 263 {
samdanbury 6:37b6d0d56190 264 struct lpc_enetdata *lpc_enetif = netif->state;
samdanbury 6:37b6d0d56190 265 struct pbuf *p = NULL;
samdanbury 6:37b6d0d56190 266 u32_t idx, length;
samdanbury 6:37b6d0d56190 267 u16_t origLength;
samdanbury 6:37b6d0d56190 268
samdanbury 6:37b6d0d56190 269 #ifdef LOCK_RX_THREAD
samdanbury 6:37b6d0d56190 270 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 271 /* Get exclusive access */
samdanbury 6:37b6d0d56190 272 sys_mutex_lock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 273 #endif
samdanbury 6:37b6d0d56190 274 #endif
samdanbury 6:37b6d0d56190 275
samdanbury 6:37b6d0d56190 276 /* Monitor RX overrun status. This should never happen unless
samdanbury 6:37b6d0d56190 277 (possibly) the internal bus is behing held up by something.
samdanbury 6:37b6d0d56190 278 Unless your system is running at a very low clock speed or
samdanbury 6:37b6d0d56190 279 there are possibilities that the internal buses may be held
samdanbury 6:37b6d0d56190 280 up for a long time, this can probably safely be removed. */
samdanbury 6:37b6d0d56190 281 if (LPC_EMAC->IntStatus & EMAC_INT_RX_OVERRUN) {
samdanbury 6:37b6d0d56190 282 LINK_STATS_INC(link.err);
samdanbury 6:37b6d0d56190 283 LINK_STATS_INC(link.drop);
samdanbury 6:37b6d0d56190 284
samdanbury 6:37b6d0d56190 285 /* Temporarily disable RX */
samdanbury 6:37b6d0d56190 286 LPC_EMAC->MAC1 &= ~EMAC_MAC1_REC_EN;
samdanbury 6:37b6d0d56190 287
samdanbury 6:37b6d0d56190 288 /* Reset the RX side */
samdanbury 6:37b6d0d56190 289 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_RX;
samdanbury 6:37b6d0d56190 290 LPC_EMAC->IntClear = EMAC_INT_RX_OVERRUN;
samdanbury 6:37b6d0d56190 291
samdanbury 6:37b6d0d56190 292 /* De-allocate all queued RX pbufs */
samdanbury 6:37b6d0d56190 293 for (idx = 0; idx < LPC_NUM_BUFF_RXDESCS; idx++) {
samdanbury 6:37b6d0d56190 294 if (lpc_enetif->rxb[idx] != NULL) {
samdanbury 6:37b6d0d56190 295 pbuf_free(lpc_enetif->rxb[idx]);
samdanbury 6:37b6d0d56190 296 lpc_enetif->rxb[idx] = NULL;
samdanbury 6:37b6d0d56190 297 }
samdanbury 6:37b6d0d56190 298 }
samdanbury 6:37b6d0d56190 299
samdanbury 6:37b6d0d56190 300 /* Start RX side again */
samdanbury 6:37b6d0d56190 301 lpc_rx_setup(lpc_enetif);
samdanbury 6:37b6d0d56190 302
samdanbury 6:37b6d0d56190 303 /* Re-enable RX */
samdanbury 6:37b6d0d56190 304 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
samdanbury 6:37b6d0d56190 305
samdanbury 6:37b6d0d56190 306 #ifdef LOCK_RX_THREAD
samdanbury 6:37b6d0d56190 307 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 308 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 309 #endif
samdanbury 6:37b6d0d56190 310 #endif
samdanbury 6:37b6d0d56190 311
samdanbury 6:37b6d0d56190 312 return NULL;
samdanbury 6:37b6d0d56190 313 }
samdanbury 6:37b6d0d56190 314
samdanbury 6:37b6d0d56190 315 /* Determine if a frame has been received */
samdanbury 6:37b6d0d56190 316 length = 0;
samdanbury 6:37b6d0d56190 317 idx = LPC_EMAC->RxConsumeIndex;
samdanbury 6:37b6d0d56190 318 if (LPC_EMAC->RxProduceIndex != idx) {
samdanbury 6:37b6d0d56190 319 /* Handle errors */
samdanbury 6:37b6d0d56190 320 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
samdanbury 6:37b6d0d56190 321 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_LEN_ERR)) {
samdanbury 6:37b6d0d56190 322 #if LINK_STATS
samdanbury 6:37b6d0d56190 323 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
samdanbury 6:37b6d0d56190 324 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR))
samdanbury 6:37b6d0d56190 325 LINK_STATS_INC(link.chkerr);
samdanbury 6:37b6d0d56190 326 if (lpc_enetif->prxs[idx].statusinfo & EMAC_RINFO_LEN_ERR)
samdanbury 6:37b6d0d56190 327 LINK_STATS_INC(link.lenerr);
samdanbury 6:37b6d0d56190 328 #endif
samdanbury 6:37b6d0d56190 329
samdanbury 6:37b6d0d56190 330 /* Drop the frame */
samdanbury 6:37b6d0d56190 331 LINK_STATS_INC(link.drop);
samdanbury 6:37b6d0d56190 332
samdanbury 6:37b6d0d56190 333 /* Re-queue the pbuf for receive */
samdanbury 6:37b6d0d56190 334 lpc_enetif->rx_free_descs++;
samdanbury 6:37b6d0d56190 335 p = lpc_enetif->rxb[idx];
samdanbury 6:37b6d0d56190 336 lpc_enetif->rxb[idx] = NULL;
samdanbury 6:37b6d0d56190 337 lpc_rxqueue_pbuf(lpc_enetif, p);
samdanbury 6:37b6d0d56190 338
samdanbury 6:37b6d0d56190 339 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 340 ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
samdanbury 6:37b6d0d56190 341 lpc_enetif->prxs[idx].statusinfo));
samdanbury 6:37b6d0d56190 342
samdanbury 6:37b6d0d56190 343 p = NULL;
samdanbury 6:37b6d0d56190 344 } else {
samdanbury 6:37b6d0d56190 345 /* A packet is waiting, get length */
samdanbury 6:37b6d0d56190 346 length = (lpc_enetif->prxs[idx].statusinfo & 0x7FF) + 1;
samdanbury 6:37b6d0d56190 347
samdanbury 6:37b6d0d56190 348 /* Zero-copy */
samdanbury 6:37b6d0d56190 349 p = lpc_enetif->rxb[idx];
samdanbury 6:37b6d0d56190 350 origLength = p->len;
samdanbury 6:37b6d0d56190 351 p->len = (u16_t) length;
samdanbury 6:37b6d0d56190 352
samdanbury 6:37b6d0d56190 353 /* Free pbuf from descriptor */
samdanbury 6:37b6d0d56190 354 lpc_enetif->rxb[idx] = NULL;
samdanbury 6:37b6d0d56190 355 lpc_enetif->rx_free_descs++;
samdanbury 6:37b6d0d56190 356
samdanbury 6:37b6d0d56190 357 /* Attempt to queue new buffer(s) */
samdanbury 6:37b6d0d56190 358 if (lpc_rx_queue(lpc_enetif->netif) == 0) {
samdanbury 6:37b6d0d56190 359 /* Drop the frame due to OOM. */
samdanbury 6:37b6d0d56190 360 LINK_STATS_INC(link.drop);
samdanbury 6:37b6d0d56190 361
samdanbury 6:37b6d0d56190 362 /* Re-queue the pbuf for receive */
samdanbury 6:37b6d0d56190 363 p->len = origLength;
samdanbury 6:37b6d0d56190 364 lpc_rxqueue_pbuf(lpc_enetif, p);
samdanbury 6:37b6d0d56190 365
samdanbury 6:37b6d0d56190 366 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 367 ("lpc_low_level_input: Packet index %d dropped for OOM\n",
samdanbury 6:37b6d0d56190 368 idx));
samdanbury 6:37b6d0d56190 369
samdanbury 6:37b6d0d56190 370 #ifdef LOCK_RX_THREAD
samdanbury 6:37b6d0d56190 371 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 372 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 373 #endif
samdanbury 6:37b6d0d56190 374 #endif
samdanbury 6:37b6d0d56190 375
samdanbury 6:37b6d0d56190 376 return NULL;
samdanbury 6:37b6d0d56190 377 }
samdanbury 6:37b6d0d56190 378
samdanbury 6:37b6d0d56190 379 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 380 ("lpc_low_level_input: Packet received: %p, size %d (index=%d)\n",
samdanbury 6:37b6d0d56190 381 p, length, idx));
samdanbury 6:37b6d0d56190 382
samdanbury 6:37b6d0d56190 383 /* Save size */
samdanbury 6:37b6d0d56190 384 p->tot_len = (u16_t) length;
samdanbury 6:37b6d0d56190 385 LINK_STATS_INC(link.recv);
samdanbury 6:37b6d0d56190 386 }
samdanbury 6:37b6d0d56190 387 }
samdanbury 6:37b6d0d56190 388
samdanbury 6:37b6d0d56190 389 #ifdef LOCK_RX_THREAD
samdanbury 6:37b6d0d56190 390 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 391 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 392 #endif
samdanbury 6:37b6d0d56190 393 #endif
samdanbury 6:37b6d0d56190 394
samdanbury 6:37b6d0d56190 395 return p;
samdanbury 6:37b6d0d56190 396 }
samdanbury 6:37b6d0d56190 397
samdanbury 6:37b6d0d56190 398 /** \brief Attempt to read a packet from the EMAC interface.
samdanbury 6:37b6d0d56190 399 *
samdanbury 6:37b6d0d56190 400 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 401 */
samdanbury 6:37b6d0d56190 402 void lpc_enetif_input(struct netif *netif)
samdanbury 6:37b6d0d56190 403 {
samdanbury 6:37b6d0d56190 404 struct eth_hdr *ethhdr;
samdanbury 6:37b6d0d56190 405 struct pbuf *p;
samdanbury 6:37b6d0d56190 406
samdanbury 6:37b6d0d56190 407 /* move received packet into a new pbuf */
samdanbury 6:37b6d0d56190 408 p = lpc_low_level_input(netif);
samdanbury 6:37b6d0d56190 409 if (p == NULL)
samdanbury 6:37b6d0d56190 410 return;
samdanbury 6:37b6d0d56190 411
samdanbury 6:37b6d0d56190 412 /* points to packet payload, which starts with an Ethernet header */
samdanbury 6:37b6d0d56190 413 ethhdr = p->payload;
samdanbury 6:37b6d0d56190 414
samdanbury 6:37b6d0d56190 415 switch (htons(ethhdr->type)) {
samdanbury 6:37b6d0d56190 416 case ETHTYPE_IP:
samdanbury 6:37b6d0d56190 417 case ETHTYPE_ARP:
samdanbury 6:37b6d0d56190 418 #if PPPOE_SUPPORT
samdanbury 6:37b6d0d56190 419 case ETHTYPE_PPPOEDISC:
samdanbury 6:37b6d0d56190 420 case ETHTYPE_PPPOE:
samdanbury 6:37b6d0d56190 421 #endif /* PPPOE_SUPPORT */
samdanbury 6:37b6d0d56190 422 /* full packet send to tcpip_thread to process */
samdanbury 6:37b6d0d56190 423 if (netif->input(p, netif) != ERR_OK) {
samdanbury 6:37b6d0d56190 424 LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
samdanbury 6:37b6d0d56190 425 /* Free buffer */
samdanbury 6:37b6d0d56190 426 pbuf_free(p);
samdanbury 6:37b6d0d56190 427 }
samdanbury 6:37b6d0d56190 428 break;
samdanbury 6:37b6d0d56190 429
samdanbury 6:37b6d0d56190 430 default:
samdanbury 6:37b6d0d56190 431 /* Return buffer */
samdanbury 6:37b6d0d56190 432 pbuf_free(p);
samdanbury 6:37b6d0d56190 433 break;
samdanbury 6:37b6d0d56190 434 }
samdanbury 6:37b6d0d56190 435 }
samdanbury 6:37b6d0d56190 436
samdanbury 6:37b6d0d56190 437 /** \brief Determine if the passed address is usable for the ethernet
samdanbury 6:37b6d0d56190 438 * DMA controller.
samdanbury 6:37b6d0d56190 439 *
samdanbury 6:37b6d0d56190 440 * \param[in] addr Address of packet to check for DMA safe operation
samdanbury 6:37b6d0d56190 441 * \return 1 if the packet address is not safe, otherwise 0
samdanbury 6:37b6d0d56190 442 */
samdanbury 6:37b6d0d56190 443 static s32_t lpc_packet_addr_notsafe(void *addr) {
samdanbury 6:37b6d0d56190 444 /* Check for legal address ranges */
samdanbury 6:37b6d0d56190 445 #if defined(TARGET_LPC1768)
samdanbury 6:37b6d0d56190 446 if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
samdanbury 6:37b6d0d56190 447 #elif defined(TARGET_LPC4088)
samdanbury 6:37b6d0d56190 448 if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
samdanbury 6:37b6d0d56190 449 #endif
samdanbury 6:37b6d0d56190 450 return 0;
samdanbury 6:37b6d0d56190 451 }
samdanbury 6:37b6d0d56190 452 return 1;
samdanbury 6:37b6d0d56190 453 }
samdanbury 6:37b6d0d56190 454
samdanbury 6:37b6d0d56190 455 /** \brief Sets up the TX descriptor ring buffers.
samdanbury 6:37b6d0d56190 456 *
samdanbury 6:37b6d0d56190 457 * This function sets up the descriptor list used for transmit packets.
samdanbury 6:37b6d0d56190 458 *
samdanbury 6:37b6d0d56190 459 * \param[in] lpc_enetif Pointer to driver data structure
samdanbury 6:37b6d0d56190 460 */
samdanbury 6:37b6d0d56190 461 static err_t lpc_tx_setup(struct lpc_enetdata *lpc_enetif)
samdanbury 6:37b6d0d56190 462 {
samdanbury 6:37b6d0d56190 463 s32_t idx;
samdanbury 6:37b6d0d56190 464
samdanbury 6:37b6d0d56190 465 /* Build TX descriptors for local buffers */
samdanbury 6:37b6d0d56190 466 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
samdanbury 6:37b6d0d56190 467 lpc_enetif->ptxd[idx].control = 0;
samdanbury 6:37b6d0d56190 468 lpc_enetif->ptxs[idx].statusinfo = 0xFFFFFFFF;
samdanbury 6:37b6d0d56190 469 }
samdanbury 6:37b6d0d56190 470
samdanbury 6:37b6d0d56190 471 /* Setup pointers to TX structures */
samdanbury 6:37b6d0d56190 472 LPC_EMAC->TxDescriptor = (u32_t) &lpc_enetif->ptxd[0];
samdanbury 6:37b6d0d56190 473 LPC_EMAC->TxStatus = (u32_t) &lpc_enetif->ptxs[0];
samdanbury 6:37b6d0d56190 474 LPC_EMAC->TxDescriptorNumber = LPC_NUM_BUFF_TXDESCS - 1;
samdanbury 6:37b6d0d56190 475
samdanbury 6:37b6d0d56190 476 lpc_enetif->lpc_last_tx_idx = 0;
samdanbury 6:37b6d0d56190 477
samdanbury 6:37b6d0d56190 478 return ERR_OK;
samdanbury 6:37b6d0d56190 479 }
samdanbury 6:37b6d0d56190 480
samdanbury 6:37b6d0d56190 481 /** \brief Free TX buffers that are complete
samdanbury 6:37b6d0d56190 482 *
samdanbury 6:37b6d0d56190 483 * \param[in] lpc_enetif Pointer to driver data structure
samdanbury 6:37b6d0d56190 484 * \param[in] cidx EMAC current descriptor comsumer index
samdanbury 6:37b6d0d56190 485 */
samdanbury 6:37b6d0d56190 486 static void lpc_tx_reclaim_st(struct lpc_enetdata *lpc_enetif, u32_t cidx)
samdanbury 6:37b6d0d56190 487 {
samdanbury 6:37b6d0d56190 488 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 489 /* Get exclusive access */
samdanbury 6:37b6d0d56190 490 sys_mutex_lock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 491 #endif
samdanbury 6:37b6d0d56190 492
samdanbury 6:37b6d0d56190 493 while (cidx != lpc_enetif->lpc_last_tx_idx) {
samdanbury 6:37b6d0d56190 494 if (lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] != NULL) {
samdanbury 6:37b6d0d56190 495 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 496 ("lpc_tx_reclaim_st: Freeing packet %p (index %d)\n",
samdanbury 6:37b6d0d56190 497 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx],
samdanbury 6:37b6d0d56190 498 lpc_enetif->lpc_last_tx_idx));
samdanbury 6:37b6d0d56190 499 pbuf_free(lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx]);
samdanbury 6:37b6d0d56190 500 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] = NULL;
samdanbury 6:37b6d0d56190 501 }
samdanbury 6:37b6d0d56190 502
samdanbury 6:37b6d0d56190 503 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 504 osSemaphoreRelease(lpc_enetif->xTXDCountSem.id);
samdanbury 6:37b6d0d56190 505 #endif
samdanbury 6:37b6d0d56190 506 lpc_enetif->lpc_last_tx_idx++;
samdanbury 6:37b6d0d56190 507 if (lpc_enetif->lpc_last_tx_idx >= LPC_NUM_BUFF_TXDESCS)
samdanbury 6:37b6d0d56190 508 lpc_enetif->lpc_last_tx_idx = 0;
samdanbury 6:37b6d0d56190 509 }
samdanbury 6:37b6d0d56190 510
samdanbury 6:37b6d0d56190 511 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 512 /* Restore access */
samdanbury 6:37b6d0d56190 513 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 514 #endif
samdanbury 6:37b6d0d56190 515 }
samdanbury 6:37b6d0d56190 516
samdanbury 6:37b6d0d56190 517 /** \brief User call for freeingTX buffers that are complete
samdanbury 6:37b6d0d56190 518 *
samdanbury 6:37b6d0d56190 519 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 520 */
samdanbury 6:37b6d0d56190 521 void lpc_tx_reclaim(struct netif *netif)
samdanbury 6:37b6d0d56190 522 {
samdanbury 6:37b6d0d56190 523 lpc_tx_reclaim_st((struct lpc_enetdata *) netif->state,
samdanbury 6:37b6d0d56190 524 LPC_EMAC->TxConsumeIndex);
samdanbury 6:37b6d0d56190 525 }
samdanbury 6:37b6d0d56190 526
samdanbury 6:37b6d0d56190 527 /** \brief Polls if an available TX descriptor is ready. Can be used to
samdanbury 6:37b6d0d56190 528 * determine if the low level transmit function will block.
samdanbury 6:37b6d0d56190 529 *
samdanbury 6:37b6d0d56190 530 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 531 * \return 0 if no descriptors are read, or >0
samdanbury 6:37b6d0d56190 532 */
samdanbury 6:37b6d0d56190 533 s32_t lpc_tx_ready(struct netif *netif)
samdanbury 6:37b6d0d56190 534 {
samdanbury 6:37b6d0d56190 535 s32_t fb;
samdanbury 6:37b6d0d56190 536 u32_t idx, cidx;
samdanbury 6:37b6d0d56190 537
samdanbury 6:37b6d0d56190 538 cidx = LPC_EMAC->TxConsumeIndex;
samdanbury 6:37b6d0d56190 539 idx = LPC_EMAC->TxProduceIndex;
samdanbury 6:37b6d0d56190 540
samdanbury 6:37b6d0d56190 541 /* Determine number of free buffers */
samdanbury 6:37b6d0d56190 542 if (idx == cidx)
samdanbury 6:37b6d0d56190 543 fb = LPC_NUM_BUFF_TXDESCS;
samdanbury 6:37b6d0d56190 544 else if (cidx > idx)
samdanbury 6:37b6d0d56190 545 fb = (LPC_NUM_BUFF_TXDESCS - 1) -
samdanbury 6:37b6d0d56190 546 ((idx + LPC_NUM_BUFF_TXDESCS) - cidx);
samdanbury 6:37b6d0d56190 547 else
samdanbury 6:37b6d0d56190 548 fb = (LPC_NUM_BUFF_TXDESCS - 1) - (cidx - idx);
samdanbury 6:37b6d0d56190 549
samdanbury 6:37b6d0d56190 550 return fb;
samdanbury 6:37b6d0d56190 551 }
samdanbury 6:37b6d0d56190 552
samdanbury 6:37b6d0d56190 553 /** \brief Low level output of a packet. Never call this from an
samdanbury 6:37b6d0d56190 554 * interrupt context, as it may block until TX descriptors
samdanbury 6:37b6d0d56190 555 * become available.
samdanbury 6:37b6d0d56190 556 *
samdanbury 6:37b6d0d56190 557 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 558 * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
samdanbury 6:37b6d0d56190 559 * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
samdanbury 6:37b6d0d56190 560 */
samdanbury 6:37b6d0d56190 561 static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
samdanbury 6:37b6d0d56190 562 {
samdanbury 6:37b6d0d56190 563 struct lpc_enetdata *lpc_enetif = netif->state;
samdanbury 6:37b6d0d56190 564 struct pbuf *q;
samdanbury 6:37b6d0d56190 565 u8_t *dst;
samdanbury 6:37b6d0d56190 566 u32_t idx, notdmasafe = 0;
samdanbury 6:37b6d0d56190 567 struct pbuf *np;
samdanbury 6:37b6d0d56190 568 s32_t dn;
samdanbury 6:37b6d0d56190 569
samdanbury 6:37b6d0d56190 570 /* Zero-copy TX buffers may be fragmented across mutliple payload
samdanbury 6:37b6d0d56190 571 chains. Determine the number of descriptors needed for the
samdanbury 6:37b6d0d56190 572 transfer. The pbuf chaining can be a mess! */
samdanbury 6:37b6d0d56190 573 dn = (s32_t) pbuf_clen(p);
samdanbury 6:37b6d0d56190 574
samdanbury 6:37b6d0d56190 575 /* Test to make sure packet addresses are DMA safe. A DMA safe
samdanbury 6:37b6d0d56190 576 address is once that uses external memory or periphheral RAM.
samdanbury 6:37b6d0d56190 577 IRAM and FLASH are not safe! */
samdanbury 6:37b6d0d56190 578 for (q = p; q != NULL; q = q->next)
samdanbury 6:37b6d0d56190 579 notdmasafe += lpc_packet_addr_notsafe(q->payload);
samdanbury 6:37b6d0d56190 580
samdanbury 6:37b6d0d56190 581 #if LPC_TX_PBUF_BOUNCE_EN==1
samdanbury 6:37b6d0d56190 582 /* If the pbuf is not DMA safe, a new bounce buffer (pbuf) will be
samdanbury 6:37b6d0d56190 583 created that will be used instead. This requires an copy from the
samdanbury 6:37b6d0d56190 584 non-safe DMA region to the new pbuf */
samdanbury 6:37b6d0d56190 585 if (notdmasafe) {
samdanbury 6:37b6d0d56190 586 /* Allocate a pbuf in DMA memory */
samdanbury 6:37b6d0d56190 587 np = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
samdanbury 6:37b6d0d56190 588 if (np == NULL)
samdanbury 6:37b6d0d56190 589 return ERR_MEM;
samdanbury 6:37b6d0d56190 590
samdanbury 6:37b6d0d56190 591 /* This buffer better be contiguous! */
samdanbury 6:37b6d0d56190 592 LWIP_ASSERT("lpc_low_level_output: New transmit pbuf is chained",
samdanbury 6:37b6d0d56190 593 (pbuf_clen(np) == 1));
samdanbury 6:37b6d0d56190 594
samdanbury 6:37b6d0d56190 595 /* Copy to DMA safe pbuf */
samdanbury 6:37b6d0d56190 596 dst = (u8_t *) np->payload;
samdanbury 6:37b6d0d56190 597 for(q = p; q != NULL; q = q->next) {
samdanbury 6:37b6d0d56190 598 /* Copy the buffer to the descriptor's buffer */
samdanbury 6:37b6d0d56190 599 MEMCPY(dst, (u8_t *) q->payload, q->len);
samdanbury 6:37b6d0d56190 600 dst += q->len;
samdanbury 6:37b6d0d56190 601 }
samdanbury 6:37b6d0d56190 602 np->len = p->tot_len;
samdanbury 6:37b6d0d56190 603
samdanbury 6:37b6d0d56190 604 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 605 ("lpc_low_level_output: Switched to DMA safe buffer, old=%p, new=%p\n",
samdanbury 6:37b6d0d56190 606 q, np));
samdanbury 6:37b6d0d56190 607
samdanbury 6:37b6d0d56190 608 /* use the new buffer for descrptor queueing. The original pbuf will
samdanbury 6:37b6d0d56190 609 be de-allocated outsuide this driver. */
samdanbury 6:37b6d0d56190 610 p = np;
samdanbury 6:37b6d0d56190 611 dn = 1;
samdanbury 6:37b6d0d56190 612 }
samdanbury 6:37b6d0d56190 613 #else
samdanbury 6:37b6d0d56190 614 if (notdmasafe)
samdanbury 6:37b6d0d56190 615 LWIP_ASSERT("lpc_low_level_output: Not a DMA safe pbuf",
samdanbury 6:37b6d0d56190 616 (notdmasafe == 0));
samdanbury 6:37b6d0d56190 617 #endif
samdanbury 6:37b6d0d56190 618
samdanbury 6:37b6d0d56190 619 /* Wait until enough descriptors are available for the transfer. */
samdanbury 6:37b6d0d56190 620 /* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
samdanbury 6:37b6d0d56190 621 while (dn > lpc_tx_ready(netif))
samdanbury 6:37b6d0d56190 622 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 623 osSemaphoreWait(lpc_enetif->xTXDCountSem.id, osWaitForever);
samdanbury 6:37b6d0d56190 624 #else
samdanbury 6:37b6d0d56190 625 osDelay(1);
samdanbury 6:37b6d0d56190 626 #endif
samdanbury 6:37b6d0d56190 627
samdanbury 6:37b6d0d56190 628 /* Get free TX buffer index */
samdanbury 6:37b6d0d56190 629 idx = LPC_EMAC->TxProduceIndex;
samdanbury 6:37b6d0d56190 630
samdanbury 6:37b6d0d56190 631 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 632 /* Get exclusive access */
samdanbury 6:37b6d0d56190 633 sys_mutex_lock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 634 #endif
samdanbury 6:37b6d0d56190 635
samdanbury 6:37b6d0d56190 636 /* Prevent LWIP from de-allocating this pbuf. The driver will
samdanbury 6:37b6d0d56190 637 free it once it's been transmitted. */
samdanbury 6:37b6d0d56190 638 if (!notdmasafe)
samdanbury 6:37b6d0d56190 639 pbuf_ref(p);
samdanbury 6:37b6d0d56190 640
samdanbury 6:37b6d0d56190 641 /* Setup transfers */
samdanbury 6:37b6d0d56190 642 q = p;
samdanbury 6:37b6d0d56190 643 while (dn > 0) {
samdanbury 6:37b6d0d56190 644 dn--;
samdanbury 6:37b6d0d56190 645
samdanbury 6:37b6d0d56190 646 /* Only save pointer to free on last descriptor */
samdanbury 6:37b6d0d56190 647 if (dn == 0) {
samdanbury 6:37b6d0d56190 648 /* Save size of packet and signal it's ready */
samdanbury 6:37b6d0d56190 649 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT |
samdanbury 6:37b6d0d56190 650 EMAC_TCTRL_LAST;
samdanbury 6:37b6d0d56190 651 lpc_enetif->txb[idx] = p;
samdanbury 6:37b6d0d56190 652 }
samdanbury 6:37b6d0d56190 653 else {
samdanbury 6:37b6d0d56190 654 /* Save size of packet, descriptor is not last */
samdanbury 6:37b6d0d56190 655 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT;
samdanbury 6:37b6d0d56190 656 lpc_enetif->txb[idx] = NULL;
samdanbury 6:37b6d0d56190 657 }
samdanbury 6:37b6d0d56190 658
samdanbury 6:37b6d0d56190 659 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
samdanbury 6:37b6d0d56190 660 ("lpc_low_level_output: pbuf packet(%p) sent, chain#=%d,"
samdanbury 6:37b6d0d56190 661 " size = %d (index=%d)\n", q->payload, dn, q->len, idx));
samdanbury 6:37b6d0d56190 662
samdanbury 6:37b6d0d56190 663 lpc_enetif->ptxd[idx].packet = (u32_t) q->payload;
samdanbury 6:37b6d0d56190 664
samdanbury 6:37b6d0d56190 665 q = q->next;
samdanbury 6:37b6d0d56190 666
samdanbury 6:37b6d0d56190 667 idx++;
samdanbury 6:37b6d0d56190 668 if (idx >= LPC_NUM_BUFF_TXDESCS)
samdanbury 6:37b6d0d56190 669 idx = 0;
samdanbury 6:37b6d0d56190 670 }
samdanbury 6:37b6d0d56190 671
samdanbury 6:37b6d0d56190 672 LPC_EMAC->TxProduceIndex = idx;
samdanbury 6:37b6d0d56190 673
samdanbury 6:37b6d0d56190 674 LINK_STATS_INC(link.xmit);
samdanbury 6:37b6d0d56190 675
samdanbury 6:37b6d0d56190 676 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 677 /* Restore access */
samdanbury 6:37b6d0d56190 678 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 679 #endif
samdanbury 6:37b6d0d56190 680
samdanbury 6:37b6d0d56190 681 return ERR_OK;
samdanbury 6:37b6d0d56190 682 }
samdanbury 6:37b6d0d56190 683
samdanbury 6:37b6d0d56190 684 /** \brief LPC EMAC interrupt handler.
samdanbury 6:37b6d0d56190 685 *
samdanbury 6:37b6d0d56190 686 * This function handles the transmit, receive, and error interrupt of
samdanbury 6:37b6d0d56190 687 * the LPC177x_8x. This is meant to be used when NO_SYS=0.
samdanbury 6:37b6d0d56190 688 */
samdanbury 6:37b6d0d56190 689 void ENET_IRQHandler(void)
samdanbury 6:37b6d0d56190 690 {
samdanbury 6:37b6d0d56190 691 #if NO_SYS == 1
samdanbury 6:37b6d0d56190 692 /* Interrupts are not used without an RTOS */
samdanbury 6:37b6d0d56190 693 NVIC_DisableIRQ(ENET_IRQn);
samdanbury 6:37b6d0d56190 694 #else
samdanbury 6:37b6d0d56190 695 uint32_t ints;
samdanbury 6:37b6d0d56190 696
samdanbury 6:37b6d0d56190 697 /* Interrupts are of 2 groups - transmit or receive. Based on the
samdanbury 6:37b6d0d56190 698 interrupt, kick off the receive or transmit (cleanup) task */
samdanbury 6:37b6d0d56190 699
samdanbury 6:37b6d0d56190 700 /* Get pending interrupts */
samdanbury 6:37b6d0d56190 701 ints = LPC_EMAC->IntStatus;
samdanbury 6:37b6d0d56190 702
samdanbury 6:37b6d0d56190 703 if (ints & RXINTGROUP) {
samdanbury 6:37b6d0d56190 704 /* RX group interrupt(s): Give signal to wakeup RX receive task.*/
samdanbury 6:37b6d0d56190 705 osSignalSet(lpc_enetdata.RxThread->id, RX_SIGNAL);
samdanbury 6:37b6d0d56190 706 }
samdanbury 6:37b6d0d56190 707
samdanbury 6:37b6d0d56190 708 if (ints & TXINTGROUP) {
samdanbury 6:37b6d0d56190 709 /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
samdanbury 6:37b6d0d56190 710 sys_sem_signal(&lpc_enetdata.TxCleanSem);
samdanbury 6:37b6d0d56190 711 }
samdanbury 6:37b6d0d56190 712
samdanbury 6:37b6d0d56190 713 /* Clear pending interrupts */
samdanbury 6:37b6d0d56190 714 LPC_EMAC->IntClear = ints;
samdanbury 6:37b6d0d56190 715 #endif
samdanbury 6:37b6d0d56190 716 }
samdanbury 6:37b6d0d56190 717
samdanbury 6:37b6d0d56190 718 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 719 /** \brief Packet reception task
samdanbury 6:37b6d0d56190 720 *
samdanbury 6:37b6d0d56190 721 * This task is called when a packet is received. It will
samdanbury 6:37b6d0d56190 722 * pass the packet to the LWIP core.
samdanbury 6:37b6d0d56190 723 *
samdanbury 6:37b6d0d56190 724 * \param[in] pvParameters Not used yet
samdanbury 6:37b6d0d56190 725 */
samdanbury 6:37b6d0d56190 726 static void packet_rx(void* pvParameters) {
samdanbury 6:37b6d0d56190 727 struct lpc_enetdata *lpc_enetif = pvParameters;
samdanbury 6:37b6d0d56190 728
samdanbury 6:37b6d0d56190 729 while (1) {
samdanbury 6:37b6d0d56190 730 /* Wait for receive task to wakeup */
samdanbury 6:37b6d0d56190 731 osSignalWait(RX_SIGNAL, osWaitForever);
samdanbury 6:37b6d0d56190 732
samdanbury 6:37b6d0d56190 733 /* Process packets until all empty */
samdanbury 6:37b6d0d56190 734 while (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex)
samdanbury 6:37b6d0d56190 735 lpc_enetif_input(lpc_enetif->netif);
samdanbury 6:37b6d0d56190 736 }
samdanbury 6:37b6d0d56190 737 }
samdanbury 6:37b6d0d56190 738
samdanbury 6:37b6d0d56190 739 /** \brief Transmit cleanup task
samdanbury 6:37b6d0d56190 740 *
samdanbury 6:37b6d0d56190 741 * This task is called when a transmit interrupt occurs and
samdanbury 6:37b6d0d56190 742 * reclaims the pbuf and descriptor used for the packet once
samdanbury 6:37b6d0d56190 743 * the packet has been transferred.
samdanbury 6:37b6d0d56190 744 *
samdanbury 6:37b6d0d56190 745 * \param[in] pvParameters Not used yet
samdanbury 6:37b6d0d56190 746 */
samdanbury 6:37b6d0d56190 747 static void packet_tx(void* pvParameters) {
samdanbury 6:37b6d0d56190 748 struct lpc_enetdata *lpc_enetif = pvParameters;
samdanbury 6:37b6d0d56190 749 s32_t idx;
samdanbury 6:37b6d0d56190 750
samdanbury 6:37b6d0d56190 751 while (1) {
samdanbury 6:37b6d0d56190 752 /* Wait for transmit cleanup task to wakeup */
samdanbury 6:37b6d0d56190 753 sys_arch_sem_wait(&lpc_enetif->TxCleanSem, 0);
samdanbury 6:37b6d0d56190 754
samdanbury 6:37b6d0d56190 755 /* Error handling for TX underruns. This should never happen unless
samdanbury 6:37b6d0d56190 756 something is holding the bus or the clocks are going too slow. It
samdanbury 6:37b6d0d56190 757 can probably be safely removed. */
samdanbury 6:37b6d0d56190 758 if (LPC_EMAC->IntStatus & EMAC_INT_TX_UNDERRUN) {
samdanbury 6:37b6d0d56190 759 LINK_STATS_INC(link.err);
samdanbury 6:37b6d0d56190 760 LINK_STATS_INC(link.drop);
samdanbury 6:37b6d0d56190 761
samdanbury 6:37b6d0d56190 762 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 763 /* Get exclusive access */
samdanbury 6:37b6d0d56190 764 sys_mutex_lock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 765 #endif
samdanbury 6:37b6d0d56190 766 /* Reset the TX side */
samdanbury 6:37b6d0d56190 767 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_TX;
samdanbury 6:37b6d0d56190 768 LPC_EMAC->IntClear = EMAC_INT_TX_UNDERRUN;
samdanbury 6:37b6d0d56190 769
samdanbury 6:37b6d0d56190 770 /* De-allocate all queued TX pbufs */
samdanbury 6:37b6d0d56190 771 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
samdanbury 6:37b6d0d56190 772 if (lpc_enetif->txb[idx] != NULL) {
samdanbury 6:37b6d0d56190 773 pbuf_free(lpc_enetif->txb[idx]);
samdanbury 6:37b6d0d56190 774 lpc_enetif->txb[idx] = NULL;
samdanbury 6:37b6d0d56190 775 }
samdanbury 6:37b6d0d56190 776 }
samdanbury 6:37b6d0d56190 777
samdanbury 6:37b6d0d56190 778 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 779 /* Restore access */
samdanbury 6:37b6d0d56190 780 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
samdanbury 6:37b6d0d56190 781 #endif
samdanbury 6:37b6d0d56190 782 /* Start TX side again */
samdanbury 6:37b6d0d56190 783 lpc_tx_setup(lpc_enetif);
samdanbury 6:37b6d0d56190 784 } else {
samdanbury 6:37b6d0d56190 785 /* Free TX buffers that are done sending */
samdanbury 6:37b6d0d56190 786 lpc_tx_reclaim(lpc_enetdata.netif);
samdanbury 6:37b6d0d56190 787 }
samdanbury 6:37b6d0d56190 788 }
samdanbury 6:37b6d0d56190 789 }
samdanbury 6:37b6d0d56190 790 #endif
samdanbury 6:37b6d0d56190 791
samdanbury 6:37b6d0d56190 792 /** \brief Low level init of the MAC and PHY.
samdanbury 6:37b6d0d56190 793 *
samdanbury 6:37b6d0d56190 794 * \param[in] netif Pointer to LWIP netif structure
samdanbury 6:37b6d0d56190 795 */
samdanbury 6:37b6d0d56190 796 static err_t low_level_init(struct netif *netif)
samdanbury 6:37b6d0d56190 797 {
samdanbury 6:37b6d0d56190 798 struct lpc_enetdata *lpc_enetif = netif->state;
samdanbury 6:37b6d0d56190 799 err_t err = ERR_OK;
samdanbury 6:37b6d0d56190 800
samdanbury 6:37b6d0d56190 801 /* Enable MII clocking */
samdanbury 6:37b6d0d56190 802 LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
samdanbury 6:37b6d0d56190 803
samdanbury 6:37b6d0d56190 804 #if defined(TARGET_LPC1768)
samdanbury 6:37b6d0d56190 805 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
samdanbury 6:37b6d0d56190 806 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
samdanbury 6:37b6d0d56190 807 #elif defined(TARGET_LPC4088)
samdanbury 6:37b6d0d56190 808 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
samdanbury 6:37b6d0d56190 809 LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
samdanbury 6:37b6d0d56190 810 LPC_IOCON->P1_1 &= ~0x07;
samdanbury 6:37b6d0d56190 811 LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
samdanbury 6:37b6d0d56190 812 LPC_IOCON->P1_4 &= ~0x07;
samdanbury 6:37b6d0d56190 813 LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
samdanbury 6:37b6d0d56190 814 LPC_IOCON->P1_8 &= ~0x07;
samdanbury 6:37b6d0d56190 815 LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
samdanbury 6:37b6d0d56190 816 LPC_IOCON->P1_9 &= ~0x07;
samdanbury 6:37b6d0d56190 817 LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
samdanbury 6:37b6d0d56190 818 LPC_IOCON->P1_10 &= ~0x07;
samdanbury 6:37b6d0d56190 819 LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
samdanbury 6:37b6d0d56190 820 LPC_IOCON->P1_14 &= ~0x07;
samdanbury 6:37b6d0d56190 821 LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
samdanbury 6:37b6d0d56190 822 LPC_IOCON->P1_15 &= ~0x07;
samdanbury 6:37b6d0d56190 823 LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
samdanbury 6:37b6d0d56190 824 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
samdanbury 6:37b6d0d56190 825 LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
samdanbury 6:37b6d0d56190 826 LPC_IOCON->P1_17 &= ~0x07;
samdanbury 6:37b6d0d56190 827 LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
samdanbury 6:37b6d0d56190 828 #endif
samdanbury 6:37b6d0d56190 829
samdanbury 6:37b6d0d56190 830 /* Reset all MAC logic */
samdanbury 6:37b6d0d56190 831 LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
samdanbury 6:37b6d0d56190 832 EMAC_MAC1_RES_RX | EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES |
samdanbury 6:37b6d0d56190 833 EMAC_MAC1_SOFT_RES;
samdanbury 6:37b6d0d56190 834 LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
samdanbury 6:37b6d0d56190 835 EMAC_CR_PASS_RUNT_FRM;
samdanbury 6:37b6d0d56190 836 osDelay(10);
samdanbury 6:37b6d0d56190 837
samdanbury 6:37b6d0d56190 838 /* Initial MAC initialization */
samdanbury 6:37b6d0d56190 839 LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
samdanbury 6:37b6d0d56190 840 LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN |
samdanbury 6:37b6d0d56190 841 EMAC_MAC2_VLAN_PAD_EN;
samdanbury 6:37b6d0d56190 842 LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
samdanbury 6:37b6d0d56190 843
samdanbury 6:37b6d0d56190 844 /* Set RMII management clock rate to lowest speed */
samdanbury 6:37b6d0d56190 845 LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(11) | EMAC_MCFG_RES_MII;
samdanbury 6:37b6d0d56190 846 LPC_EMAC->MCFG &= ~EMAC_MCFG_RES_MII;
samdanbury 6:37b6d0d56190 847
samdanbury 6:37b6d0d56190 848 /* Maximum number of retries, 0x37 collision window, gap */
samdanbury 6:37b6d0d56190 849 LPC_EMAC->CLRT = EMAC_CLRT_DEF;
samdanbury 6:37b6d0d56190 850 LPC_EMAC->IPGR = EMAC_IPGR_P1_DEF | EMAC_IPGR_P2_DEF;
samdanbury 6:37b6d0d56190 851
samdanbury 6:37b6d0d56190 852 #if LPC_EMAC_RMII
samdanbury 6:37b6d0d56190 853 /* RMII setup */
samdanbury 6:37b6d0d56190 854 LPC_EMAC->Command = EMAC_CR_PASS_RUNT_FRM | EMAC_CR_RMII;
samdanbury 6:37b6d0d56190 855 #else
samdanbury 6:37b6d0d56190 856 /* MII setup */
samdanbury 6:37b6d0d56190 857 LPC_EMAC->CR = EMAC_CR_PASS_RUNT_FRM;
samdanbury 6:37b6d0d56190 858 #endif
samdanbury 6:37b6d0d56190 859
samdanbury 6:37b6d0d56190 860 /* Initialize the PHY and reset */
samdanbury 6:37b6d0d56190 861 err = lpc_phy_init(netif, LPC_EMAC_RMII);
samdanbury 6:37b6d0d56190 862 if (err != ERR_OK)
samdanbury 6:37b6d0d56190 863 return err;
samdanbury 6:37b6d0d56190 864
samdanbury 6:37b6d0d56190 865 /* Save station address */
samdanbury 6:37b6d0d56190 866 LPC_EMAC->SA2 = (u32_t) netif->hwaddr[0] |
samdanbury 6:37b6d0d56190 867 (((u32_t) netif->hwaddr[1]) << 8);
samdanbury 6:37b6d0d56190 868 LPC_EMAC->SA1 = (u32_t) netif->hwaddr[2] |
samdanbury 6:37b6d0d56190 869 (((u32_t) netif->hwaddr[3]) << 8);
samdanbury 6:37b6d0d56190 870 LPC_EMAC->SA0 = (u32_t) netif->hwaddr[4] |
samdanbury 6:37b6d0d56190 871 (((u32_t) netif->hwaddr[5]) << 8);
samdanbury 6:37b6d0d56190 872
samdanbury 6:37b6d0d56190 873 /* Setup transmit and receive descriptors */
samdanbury 6:37b6d0d56190 874 if (lpc_tx_setup(lpc_enetif) != ERR_OK)
samdanbury 6:37b6d0d56190 875 return ERR_BUF;
samdanbury 6:37b6d0d56190 876 if (lpc_rx_setup(lpc_enetif) != ERR_OK)
samdanbury 6:37b6d0d56190 877 return ERR_BUF;
samdanbury 6:37b6d0d56190 878
samdanbury 6:37b6d0d56190 879 /* Enable packet reception */
samdanbury 6:37b6d0d56190 880 #if IP_SOF_BROADCAST_RECV
samdanbury 6:37b6d0d56190 881 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_MCAST_EN;
samdanbury 6:37b6d0d56190 882 #else
samdanbury 6:37b6d0d56190 883 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN;
samdanbury 6:37b6d0d56190 884 #endif
samdanbury 6:37b6d0d56190 885
samdanbury 6:37b6d0d56190 886 /* Clear and enable rx/tx interrupts */
samdanbury 6:37b6d0d56190 887 LPC_EMAC->IntClear = 0xFFFF;
samdanbury 6:37b6d0d56190 888 LPC_EMAC->IntEnable = RXINTGROUP | TXINTGROUP;
samdanbury 6:37b6d0d56190 889
samdanbury 6:37b6d0d56190 890 /* Enable RX and TX */
samdanbury 6:37b6d0d56190 891 LPC_EMAC->Command |= EMAC_CR_RX_EN | EMAC_CR_TX_EN;
samdanbury 6:37b6d0d56190 892 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
samdanbury 6:37b6d0d56190 893
samdanbury 6:37b6d0d56190 894 return err;
samdanbury 6:37b6d0d56190 895 }
samdanbury 6:37b6d0d56190 896
samdanbury 6:37b6d0d56190 897 /* This function provides a method for the PHY to setup the EMAC
samdanbury 6:37b6d0d56190 898 for the PHY negotiated duplex mode */
samdanbury 6:37b6d0d56190 899 void lpc_emac_set_duplex(int full_duplex)
samdanbury 6:37b6d0d56190 900 {
samdanbury 6:37b6d0d56190 901 if (full_duplex) {
samdanbury 6:37b6d0d56190 902 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
samdanbury 6:37b6d0d56190 903 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
samdanbury 6:37b6d0d56190 904 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
samdanbury 6:37b6d0d56190 905 } else {
samdanbury 6:37b6d0d56190 906 LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
samdanbury 6:37b6d0d56190 907 LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
samdanbury 6:37b6d0d56190 908 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
samdanbury 6:37b6d0d56190 909 }
samdanbury 6:37b6d0d56190 910 }
samdanbury 6:37b6d0d56190 911
samdanbury 6:37b6d0d56190 912 /* This function provides a method for the PHY to setup the EMAC
samdanbury 6:37b6d0d56190 913 for the PHY negotiated bit rate */
samdanbury 6:37b6d0d56190 914 void lpc_emac_set_speed(int mbs_100)
samdanbury 6:37b6d0d56190 915 {
samdanbury 6:37b6d0d56190 916 if (mbs_100)
samdanbury 6:37b6d0d56190 917 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
samdanbury 6:37b6d0d56190 918 else
samdanbury 6:37b6d0d56190 919 LPC_EMAC->SUPP = 0;
samdanbury 6:37b6d0d56190 920 }
samdanbury 6:37b6d0d56190 921
samdanbury 6:37b6d0d56190 922 /**
samdanbury 6:37b6d0d56190 923 * This function is the ethernet packet send function. It calls
samdanbury 6:37b6d0d56190 924 * etharp_output after checking link status.
samdanbury 6:37b6d0d56190 925 *
samdanbury 6:37b6d0d56190 926 * \param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 927 * \param[in] q Pointer to pbug to send
samdanbury 6:37b6d0d56190 928 * \param[in] ipaddr IP address
samdanbury 6:37b6d0d56190 929 * \return ERR_OK or error code
samdanbury 6:37b6d0d56190 930 */
samdanbury 6:37b6d0d56190 931 err_t lpc_etharp_output(struct netif *netif, struct pbuf *q,
samdanbury 6:37b6d0d56190 932 ip_addr_t *ipaddr)
samdanbury 6:37b6d0d56190 933 {
samdanbury 6:37b6d0d56190 934 /* Only send packet is link is up */
samdanbury 6:37b6d0d56190 935 if (netif->flags & NETIF_FLAG_LINK_UP)
samdanbury 6:37b6d0d56190 936 return etharp_output(netif, q, ipaddr);
samdanbury 6:37b6d0d56190 937
samdanbury 6:37b6d0d56190 938 return ERR_CONN;
samdanbury 6:37b6d0d56190 939 }
samdanbury 6:37b6d0d56190 940
samdanbury 6:37b6d0d56190 941 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 942 /* periodic PHY status update */
samdanbury 6:37b6d0d56190 943 void phy_update(void const *nif) {
samdanbury 6:37b6d0d56190 944 lpc_phy_sts_sm((struct netif*)nif);
samdanbury 6:37b6d0d56190 945 }
samdanbury 6:37b6d0d56190 946 osTimerDef(phy_update, phy_update);
samdanbury 6:37b6d0d56190 947 #endif
samdanbury 6:37b6d0d56190 948
samdanbury 6:37b6d0d56190 949 /**
samdanbury 6:37b6d0d56190 950 * Should be called at the beginning of the program to set up the
samdanbury 6:37b6d0d56190 951 * network interface.
samdanbury 6:37b6d0d56190 952 *
samdanbury 6:37b6d0d56190 953 * This function should be passed as a parameter to netif_add().
samdanbury 6:37b6d0d56190 954 *
samdanbury 6:37b6d0d56190 955 * @param[in] netif the lwip network interface structure for this lpc_enetif
samdanbury 6:37b6d0d56190 956 * @return ERR_OK if the loopif is initialized
samdanbury 6:37b6d0d56190 957 * ERR_MEM if private data couldn't be allocated
samdanbury 6:37b6d0d56190 958 * any other err_t on error
samdanbury 6:37b6d0d56190 959 */
samdanbury 6:37b6d0d56190 960 err_t eth_arch_enetif_init(struct netif *netif)
samdanbury 6:37b6d0d56190 961 {
samdanbury 6:37b6d0d56190 962 err_t err;
samdanbury 6:37b6d0d56190 963
samdanbury 6:37b6d0d56190 964 LWIP_ASSERT("netif != NULL", (netif != NULL));
samdanbury 6:37b6d0d56190 965
samdanbury 6:37b6d0d56190 966 lpc_enetdata.netif = netif;
samdanbury 6:37b6d0d56190 967
samdanbury 6:37b6d0d56190 968 /* set MAC hardware address */
samdanbury 6:37b6d0d56190 969 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
samdanbury 6:37b6d0d56190 970 netif->hwaddr[0] = MBED_MAC_ADDR_0;
samdanbury 6:37b6d0d56190 971 netif->hwaddr[1] = MBED_MAC_ADDR_1;
samdanbury 6:37b6d0d56190 972 netif->hwaddr[2] = MBED_MAC_ADDR_2;
samdanbury 6:37b6d0d56190 973 netif->hwaddr[3] = MBED_MAC_ADDR_3;
samdanbury 6:37b6d0d56190 974 netif->hwaddr[4] = MBED_MAC_ADDR_4;
samdanbury 6:37b6d0d56190 975 netif->hwaddr[5] = MBED_MAC_ADDR_5;
samdanbury 6:37b6d0d56190 976 #else
samdanbury 6:37b6d0d56190 977 mbed_mac_address((char *)netif->hwaddr);
samdanbury 6:37b6d0d56190 978 #endif
samdanbury 6:37b6d0d56190 979 netif->hwaddr_len = ETHARP_HWADDR_LEN;
samdanbury 6:37b6d0d56190 980
samdanbury 6:37b6d0d56190 981 /* maximum transfer unit */
samdanbury 6:37b6d0d56190 982 netif->mtu = 1500;
samdanbury 6:37b6d0d56190 983
samdanbury 6:37b6d0d56190 984 /* device capabilities */
samdanbury 6:37b6d0d56190 985 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
samdanbury 6:37b6d0d56190 986
samdanbury 6:37b6d0d56190 987 /* Initialize the hardware */
samdanbury 6:37b6d0d56190 988 netif->state = &lpc_enetdata;
samdanbury 6:37b6d0d56190 989 err = low_level_init(netif);
samdanbury 6:37b6d0d56190 990 if (err != ERR_OK)
samdanbury 6:37b6d0d56190 991 return err;
samdanbury 6:37b6d0d56190 992
samdanbury 6:37b6d0d56190 993 #if LWIP_NETIF_HOSTNAME
samdanbury 6:37b6d0d56190 994 /* Initialize interface hostname */
samdanbury 6:37b6d0d56190 995 netif->hostname = "lwiplpc";
samdanbury 6:37b6d0d56190 996 #endif /* LWIP_NETIF_HOSTNAME */
samdanbury 6:37b6d0d56190 997
samdanbury 6:37b6d0d56190 998 netif->name[0] = 'e';
samdanbury 6:37b6d0d56190 999 netif->name[1] = 'n';
samdanbury 6:37b6d0d56190 1000
samdanbury 6:37b6d0d56190 1001 netif->output = lpc_etharp_output;
samdanbury 6:37b6d0d56190 1002 netif->linkoutput = lpc_low_level_output;
samdanbury 6:37b6d0d56190 1003
samdanbury 6:37b6d0d56190 1004 /* CMSIS-RTOS, start tasks */
samdanbury 6:37b6d0d56190 1005 #if NO_SYS == 0
samdanbury 6:37b6d0d56190 1006 #ifdef CMSIS_OS_RTX
samdanbury 6:37b6d0d56190 1007 memset(lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
samdanbury 6:37b6d0d56190 1008 lpc_enetdata.xTXDCountSem.def.semaphore = lpc_enetdata.xTXDCountSem.data;
samdanbury 6:37b6d0d56190 1009 #endif
samdanbury 6:37b6d0d56190 1010 lpc_enetdata.xTXDCountSem.id = osSemaphoreCreate(&lpc_enetdata.xTXDCountSem.def, LPC_NUM_BUFF_TXDESCS);
samdanbury 6:37b6d0d56190 1011 LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
samdanbury 6:37b6d0d56190 1012
samdanbury 6:37b6d0d56190 1013 err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
samdanbury 6:37b6d0d56190 1014 LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
samdanbury 6:37b6d0d56190 1015
samdanbury 6:37b6d0d56190 1016 /* Packet receive task */
samdanbury 6:37b6d0d56190 1017 lpc_enetdata.RxThread = sys_thread_new("receive_thread", packet_rx, netif->state, DEFAULT_THREAD_STACKSIZE, RX_PRIORITY);
samdanbury 6:37b6d0d56190 1018 LWIP_ASSERT("RxThread creation error", (lpc_enetdata.RxThread));
samdanbury 6:37b6d0d56190 1019
samdanbury 6:37b6d0d56190 1020 /* Transmit cleanup task */
samdanbury 6:37b6d0d56190 1021 err = sys_sem_new(&lpc_enetdata.TxCleanSem, 0);
samdanbury 6:37b6d0d56190 1022 LWIP_ASSERT("TxCleanSem creation error", (err == ERR_OK));
samdanbury 6:37b6d0d56190 1023 sys_thread_new("txclean_thread", packet_tx, netif->state, DEFAULT_THREAD_STACKSIZE, TX_PRIORITY);
samdanbury 6:37b6d0d56190 1024
samdanbury 6:37b6d0d56190 1025 /* periodic PHY status update */
samdanbury 6:37b6d0d56190 1026 osTimerId phy_timer = osTimerCreate(osTimer(phy_update), osTimerPeriodic, (void *)netif);
samdanbury 6:37b6d0d56190 1027 osTimerStart(phy_timer, 250);
samdanbury 6:37b6d0d56190 1028 #endif
samdanbury 6:37b6d0d56190 1029
samdanbury 6:37b6d0d56190 1030 return ERR_OK;
samdanbury 6:37b6d0d56190 1031 }
samdanbury 6:37b6d0d56190 1032
samdanbury 6:37b6d0d56190 1033 void eth_arch_enable_interrupts(void) {
samdanbury 6:37b6d0d56190 1034 NVIC_SetPriority(ENET_IRQn, ((0x01 << 3) | 0x01));
samdanbury 6:37b6d0d56190 1035 NVIC_EnableIRQ(ENET_IRQn);
samdanbury 6:37b6d0d56190 1036 }
samdanbury 6:37b6d0d56190 1037
samdanbury 6:37b6d0d56190 1038 void eth_arch_disable_interrupts(void) {
samdanbury 6:37b6d0d56190 1039 NVIC_DisableIRQ(ENET_IRQn);
samdanbury 6:37b6d0d56190 1040 }
samdanbury 6:37b6d0d56190 1041
samdanbury 6:37b6d0d56190 1042 /**
samdanbury 6:37b6d0d56190 1043 * @}
samdanbury 6:37b6d0d56190 1044 */
samdanbury 6:37b6d0d56190 1045
samdanbury 6:37b6d0d56190 1046 /* --------------------------------- End Of File ------------------------------ */