raspiezo / mbed-dev

hal_tick.h changed for the L432KC target in TARGET/../device/ in order to reassign the system ticker from TIM2 to TIM7, since TIM2 was needed as a 32bit encoder counter.

Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

Fork of mbed-dev by mbed official

hal/i2c_api.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
119:3921aeca8633
Child:
149:156823d33999
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #ifndef MBED_I2C_API_H
<> 144:ef7eb2e8f9f7 17 #define MBED_I2C_API_H
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "device.h"
<> 144:ef7eb2e8f9f7 20 #include "buffer.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #if DEVICE_I2C_ASYNCH
<> 144:ef7eb2e8f9f7 23 #include "dma_api.h"
<> 144:ef7eb2e8f9f7 24 #endif
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #if DEVICE_I2C
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /**
<> 144:ef7eb2e8f9f7 29 * @defgroup hal_I2CEvents I2C Events Macros
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * @{
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33 #define I2C_EVENT_ERROR (1 << 1)
<> 144:ef7eb2e8f9f7 34 #define I2C_EVENT_ERROR_NO_SLAVE (1 << 2)
<> 144:ef7eb2e8f9f7 35 #define I2C_EVENT_TRANSFER_COMPLETE (1 << 3)
<> 144:ef7eb2e8f9f7 36 #define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
<> 144:ef7eb2e8f9f7 37 #define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /**@}*/
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #if DEVICE_I2C_ASYNCH
<> 144:ef7eb2e8f9f7 42 /** Asynch I2C HAL structure
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44 typedef struct {
<> 144:ef7eb2e8f9f7 45 struct i2c_s i2c; /**< Target specific I2C structure */
<> 144:ef7eb2e8f9f7 46 struct buffer_s tx_buff; /**< Tx buffer */
<> 144:ef7eb2e8f9f7 47 struct buffer_s rx_buff; /**< Rx buffer */
<> 144:ef7eb2e8f9f7 48 } i2c_t;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #else
<> 144:ef7eb2e8f9f7 51 /** Non-asynch I2C HAL structure
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53 typedef struct i2c_s i2c_t;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #endif
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 enum {
<> 144:ef7eb2e8f9f7 58 I2C_ERROR_NO_SLAVE = -1,
<> 144:ef7eb2e8f9f7 59 I2C_ERROR_BUS_BUSY = -2
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 63 extern "C" {
<> 144:ef7eb2e8f9f7 64 #endif
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * \defgroup hal_GeneralI2C I2C Configuration Functions
<> 144:ef7eb2e8f9f7 68 * @{
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /** Initialize the I2C peripheral. It sets the default parameters for I2C
<> 144:ef7eb2e8f9f7 72 * peripheral, and configures its specifieds pins.
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 75 * @param sda The sda pin
<> 144:ef7eb2e8f9f7 76 * @param scl The scl pin
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78 void i2c_init(i2c_t *obj, PinName sda, PinName scl);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** Configure the I2C frequency
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 83 * @param hz Frequency in Hz
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85 void i2c_frequency(i2c_t *obj, int hz);
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** Send START command
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 int i2c_start(i2c_t *obj);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** Send STOP command
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 int i2c_stop(i2c_t *obj);
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** Blocking reading data
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 102 * @param address 7-bit address (last bit is 1)
<> 144:ef7eb2e8f9f7 103 * @param data The buffer for receiving
<> 144:ef7eb2e8f9f7 104 * @param length Number of bytes to read
<> 144:ef7eb2e8f9f7 105 * @param stop Stop to be generated after the transfer is done
<> 144:ef7eb2e8f9f7 106 * @return Number of read bytes
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** Blocking sending data
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 113 * @param address 7-bit address (last bit is 0)
<> 144:ef7eb2e8f9f7 114 * @param data The buffer for sending
<> 144:ef7eb2e8f9f7 115 * @param length Number of bytes to write
<> 144:ef7eb2e8f9f7 116 * @param stop Stop to be generated after the transfer is done
<> 144:ef7eb2e8f9f7 117 * @return Number of written bytes
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 void i2c_reset(i2c_t *obj);
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** Read one byte
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 130 * @param last Acknoledge
<> 144:ef7eb2e8f9f7 131 * @return The read byte
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 int i2c_byte_read(i2c_t *obj, int last);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** Write one byte
<> 144:ef7eb2e8f9f7 136 *
<> 144:ef7eb2e8f9f7 137 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 138 * @param data Byte to be written
<> 144:ef7eb2e8f9f7 139 * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 int i2c_byte_write(i2c_t *obj, int data);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**@}*/
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #if DEVICE_I2CSLAVE
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** Configure I2C as slave or master.
<> 144:ef7eb2e8f9f7 153 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 154 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 void i2c_slave_mode(i2c_t *obj, int enable_slave);
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** Check to see if the I2C slave has been addressed.
<> 144:ef7eb2e8f9f7 159 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 160 * @return The status - 1 - read addresses, 2 - write to all slaves,
<> 144:ef7eb2e8f9f7 161 * 3 write addressed, 0 - the slave has not been addressed
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 int i2c_slave_receive(i2c_t *obj);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** Configure I2C as slave or master.
<> 144:ef7eb2e8f9f7 166 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 167 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 int i2c_slave_read(i2c_t *obj, char *data, int length);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** Configure I2C as slave or master.
<> 144:ef7eb2e8f9f7 172 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 173 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 int i2c_slave_write(i2c_t *obj, const char *data, int length);
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /** Configure I2C address.
<> 144:ef7eb2e8f9f7 178 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 179 * @param idx Currently not used
<> 144:ef7eb2e8f9f7 180 * @param address The address to be set
<> 144:ef7eb2e8f9f7 181 * @param mask Currently not used
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 #endif
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**@}*/
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #if DEVICE_I2C_ASYNCH
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** Start I2C asynchronous transfer
<> 144:ef7eb2e8f9f7 197 *
<> 144:ef7eb2e8f9f7 198 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 199 * @param tx The transmit buffer
<> 144:ef7eb2e8f9f7 200 * @param tx_length The number of bytes to transmit
<> 144:ef7eb2e8f9f7 201 * @param rx The receive buffer
<> 144:ef7eb2e8f9f7 202 * @param rx_length The number of bytes to receive
<> 144:ef7eb2e8f9f7 203 * @param address The address to be set - 7bit or 9bit
<> 144:ef7eb2e8f9f7 204 * @param stop If true, stop will be generated after the transfer is done
<> 144:ef7eb2e8f9f7 205 * @param handler The I2C IRQ handler to be set
<> 144:ef7eb2e8f9f7 206 * @param hint DMA hint usage
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** The asynchronous IRQ handler
<> 144:ef7eb2e8f9f7 211 *
<> 144:ef7eb2e8f9f7 212 * @param obj The I2C object which holds the transfer information
<> 144:ef7eb2e8f9f7 213 * @return Event flags if a transfer termination condition was met, otherwise return 0.
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 uint32_t i2c_irq_handler_asynch(i2c_t *obj);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** Attempts to determine if the I2C peripheral is already in use
<> 144:ef7eb2e8f9f7 218 *
<> 144:ef7eb2e8f9f7 219 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 220 * @return Non-zero if the I2C module is active or zero if it is not
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 uint8_t i2c_active(i2c_t *obj);
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /** Abort asynchronous transfer
<> 144:ef7eb2e8f9f7 225 *
<> 144:ef7eb2e8f9f7 226 * This function does not perform any check - that should happen in upper layers.
<> 144:ef7eb2e8f9f7 227 * @param obj The I2C object
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 void i2c_abort_asynch(i2c_t *obj);
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #endif
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /**@}*/
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237 #endif
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #endif
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #endif