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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 *******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file sleep.c
group-onsemi 0:098463de4c5d 4 * @brief Implementation of an sleep functionality
group-onsemi 0:098463de4c5d 5 * @internal
group-onsemi 0:098463de4c5d 6 * @author ON Semiconductor
group-onsemi 0:098463de4c5d 7 * $Rev: 0.1 $
group-onsemi 0:098463de4c5d 8 * $Date: 01-21-2016 $
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
group-onsemi 0:098463de4c5d 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
group-onsemi 0:098463de4c5d 12 * under limited terms and conditions. The terms and conditions pertaining to the software
group-onsemi 0:098463de4c5d 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
group-onsemi 0:098463de4c5d 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
group-onsemi 0:098463de4c5d 15 * if applicable the software license agreement. Do not use this software and/or
group-onsemi 0:098463de4c5d 16 * documentation unless you have carefully read and you agree to the limited terms and
group-onsemi 0:098463de4c5d 17 * conditions. By using this software and/or documentation, you agree to the limited
group-onsemi 0:098463de4c5d 18 * terms and conditions.
group-onsemi 0:098463de4c5d 19 *
group-onsemi 0:098463de4c5d 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
group-onsemi 0:098463de4c5d 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 25 * @endinternal
group-onsemi 0:098463de4c5d 26 *
group-onsemi 0:098463de4c5d 27 * @ingroup sleep
group-onsemi 0:098463de4c5d 28 *
group-onsemi 0:098463de4c5d 29 * @details
group-onsemi 0:098463de4c5d 30 * Sleep implementation
group-onsemi 0:098463de4c5d 31 *
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33 #if DEVICE_SLEEP
group-onsemi 0:098463de4c5d 34 #include "sleep.h"
group-onsemi 0:098463de4c5d 35 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 36 #include "cmsis_nvic.h"
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #define ENABLE (uint8_t)0x01
group-onsemi 0:098463de4c5d 39 #define DISABLE (uint8_t)0x00
group-onsemi 0:098463de4c5d 40 #define MAC_LUT_SIZE (uint8_t)96
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
group-onsemi 0:098463de4c5d 43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
group-onsemi 0:098463de4c5d 44 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
group-onsemi 0:098463de4c5d 45 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 void fncs36510_sleep(void)
group-onsemi 0:098463de4c5d 48 {
group-onsemi 0:098463de4c5d 49 /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
group-onsemi 0:098463de4c5d 50 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 51 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 /* Enter into sleep mode */
group-onsemi 0:098463de4c5d 54 __ISB();
group-onsemi 0:098463de4c5d 55 __WFI();
group-onsemi 0:098463de4c5d 56 }
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 void fncs36510_deepsleep(void)
group-onsemi 0:098463de4c5d 59 {
group-onsemi 0:098463de4c5d 60 /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
group-onsemi 0:098463de4c5d 61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 62 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 /** Enter into deep sleep mode */
group-onsemi 0:098463de4c5d 65 __ISB();
group-onsemi 0:098463de4c5d 66 __WFI();
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 /** Wait for the external 32MHz to be power-ed up & running
group-onsemi 0:098463de4c5d 69 * Re-power down the 32MHz internal osc
group-onsemi 0:098463de4c5d 70 */
group-onsemi 0:098463de4c5d 71 while (!CLOCKREG->CSR.BITS.XTAL32M);
group-onsemi 0:098463de4c5d 72 PMUREG->CONTROL.BITS.INT32M = 1;
group-onsemi 0:098463de4c5d 73 }
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 void fncs36510_coma(void)
group-onsemi 0:098463de4c5d 76 {
group-onsemi 0:098463de4c5d 77 /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
group-onsemi 0:098463de4c5d 78 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 79 PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /* TODO Wait till MAC is idle */
group-onsemi 0:098463de4c5d 82 // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 /* TODO Back up MAC_LUT *
group-onsemi 0:098463de4c5d 85 uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
group-onsemi 0:098463de4c5d 86 fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 /* Disable UART 1 & 2 FIFO during coma*/
group-onsemi 0:098463de4c5d 89 UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
group-onsemi 0:098463de4c5d 90 UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 /** Enter into coma mode */
group-onsemi 0:098463de4c5d 93 __ISB();
group-onsemi 0:098463de4c5d 94 __WFI();
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 /** Wait for the external 32MHz to be power-ed up & running
group-onsemi 0:098463de4c5d 97 * Re-power down the 32MHz internal osc
group-onsemi 0:098463de4c5d 98 */
group-onsemi 0:098463de4c5d 99 while (!CLOCKREG->CSR.BITS.XTAL32M);
group-onsemi 0:098463de4c5d 100 PMUREG->CONTROL.BITS.INT32M = 1;
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 /** Trim the oscillators */
group-onsemi 0:098463de4c5d 103 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
group-onsemi 0:098463de4c5d 104 CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
group-onsemi 0:098463de4c5d 105 }
group-onsemi 0:098463de4c5d 106 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
group-onsemi 0:098463de4c5d 107 CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
group-onsemi 0:098463de4c5d 108 }
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 /* Enable UART 1 & 2 FIFO */
group-onsemi 0:098463de4c5d 111 UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
group-onsemi 0:098463de4c5d 112 UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 /* TODO Restore MAC_LUT *
group-onsemi 0:098463de4c5d 115 fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
group-onsemi 0:098463de4c5d 116 }
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 #endif /* DEVICE_SLEEP */