ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2015-2016 Nuvoton
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #include "lp_ticker_api.h"
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #if DEVICE_LOWPOWERTIMER
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #include "sleep_api.h"
group-onsemi 0:098463de4c5d 22 #include "nu_modutil.h"
group-onsemi 0:098463de4c5d 23 #include "nu_miscutil.h"
group-onsemi 0:098463de4c5d 24 #include "critical.h"
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 // lp_ticker tick = us = timestamp
group-onsemi 0:098463de4c5d 27 #define US_PER_TICK (1)
group-onsemi 0:098463de4c5d 28 #define US_PER_SEC (1000 * 1000)
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 #define US_PER_TMR2_INT (US_PER_SEC * 10)
group-onsemi 0:098463de4c5d 31 #define TMR2_CLK_PER_SEC (__LXT)
group-onsemi 0:098463de4c5d 32 #define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
group-onsemi 0:098463de4c5d 33 #define TMR3_CLK_PER_SEC (__LXT)
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 static void tmr2_vec(void);
group-onsemi 0:098463de4c5d 36 static void tmr3_vec(void);
group-onsemi 0:098463de4c5d 37 static void lp_ticker_arm_cd(void);
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 static int lp_ticker_inited = 0;
group-onsemi 0:098463de4c5d 40 static volatile uint32_t counter_major = 0;
group-onsemi 0:098463de4c5d 41 static volatile uint32_t cd_major_minor_clks = 0;
group-onsemi 0:098463de4c5d 42 static volatile uint32_t cd_minor_clks = 0;
group-onsemi 0:098463de4c5d 43 static volatile uint32_t wakeup_tick = (uint32_t) -1;
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
group-onsemi 0:098463de4c5d 46 // NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
group-onsemi 0:098463de4c5d 47 static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
group-onsemi 0:098463de4c5d 48 static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 #define TMR_CMP_MIN 2
group-onsemi 0:098463de4c5d 51 #define TMR_CMP_MAX 0xFFFFFFu
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 void lp_ticker_init(void)
group-onsemi 0:098463de4c5d 54 {
group-onsemi 0:098463de4c5d 55 if (lp_ticker_inited) {
group-onsemi 0:098463de4c5d 56 return;
group-onsemi 0:098463de4c5d 57 }
group-onsemi 0:098463de4c5d 58 lp_ticker_inited = 1;
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 counter_major = 0;
group-onsemi 0:098463de4c5d 61 cd_major_minor_clks = 0;
group-onsemi 0:098463de4c5d 62 cd_minor_clks = 0;
group-onsemi 0:098463de4c5d 63 wakeup_tick = (uint32_t) -1;
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 // Reset module
group-onsemi 0:098463de4c5d 66 SYS_ResetModule(timer2_modinit.rsetidx);
group-onsemi 0:098463de4c5d 67 SYS_ResetModule(timer3_modinit.rsetidx);
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 // Select IP clock source
group-onsemi 0:098463de4c5d 70 CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
group-onsemi 0:098463de4c5d 71 CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
group-onsemi 0:098463de4c5d 72 // Enable IP clock
group-onsemi 0:098463de4c5d 73 CLK_EnableModuleClock(timer2_modinit.clkidx);
group-onsemi 0:098463de4c5d 74 CLK_EnableModuleClock(timer3_modinit.clkidx);
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 // Configure clock
group-onsemi 0:098463de4c5d 77 uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 78 uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
group-onsemi 0:098463de4c5d 79 MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
group-onsemi 0:098463de4c5d 80 MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
group-onsemi 0:098463de4c5d 81 uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
group-onsemi 0:098463de4c5d 82 MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
group-onsemi 0:098463de4c5d 83 // Continuous mode
group-onsemi 0:098463de4c5d 84 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
group-onsemi 0:098463de4c5d 85 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
group-onsemi 0:098463de4c5d 86 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 // Set vector
group-onsemi 0:098463de4c5d 89 NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
group-onsemi 0:098463de4c5d 90 NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 NVIC_EnableIRQ(timer2_modinit.irq_n);
group-onsemi 0:098463de4c5d 93 NVIC_EnableIRQ(timer3_modinit.irq_n);
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 96 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
group-onsemi 0:098463de4c5d 99 // timer is not running.
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 // Start timer
group-onsemi 0:098463de4c5d 102 TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
group-onsemi 0:098463de4c5d 105 lp_ticker_set_interrupt(wakeup_tick);
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 timestamp_t lp_ticker_read()
group-onsemi 0:098463de4c5d 109 {
group-onsemi 0:098463de4c5d 110 if (! lp_ticker_inited) {
group-onsemi 0:098463de4c5d 111 lp_ticker_init();
group-onsemi 0:098463de4c5d 112 }
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 do {
group-onsemi 0:098463de4c5d 117 uint64_t major_minor_clks;
group-onsemi 0:098463de4c5d 118 uint32_t minor_clks;
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
group-onsemi 0:098463de4c5d 121 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
group-onsemi 0:098463de4c5d 122 do {
group-onsemi 0:098463de4c5d 123 core_util_critical_section_enter();
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 // NOTE: Order of reading minor_us/carry here is significant.
group-onsemi 0:098463de4c5d 126 minor_clks = TIMER_GetCounter(timer2_base);
group-onsemi 0:098463de4c5d 127 uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
group-onsemi 0:098463de4c5d 128 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
group-onsemi 0:098463de4c5d 129 if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
group-onsemi 0:098463de4c5d 130 major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132 else {
group-onsemi 0:098463de4c5d 133 major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
group-onsemi 0:098463de4c5d 134 }
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 core_util_critical_section_exit();
group-onsemi 0:098463de4c5d 137 }
group-onsemi 0:098463de4c5d 138 while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 // Add power-down compensation
group-onsemi 0:098463de4c5d 141 return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
group-onsemi 0:098463de4c5d 142 }
group-onsemi 0:098463de4c5d 143 while (0);
group-onsemi 0:098463de4c5d 144 }
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 void lp_ticker_set_interrupt(timestamp_t timestamp)
group-onsemi 0:098463de4c5d 147 {
group-onsemi 0:098463de4c5d 148 uint32_t now = lp_ticker_read();
group-onsemi 0:098463de4c5d 149 wakeup_tick = timestamp;
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 /**
group-onsemi 0:098463de4c5d 154 * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
group-onsemi 0:098463de4c5d 155 * Conditions in which delta is negative:
group-onsemi 0:098463de4c5d 156 * 1. Wrap around
group-onsemi 0:098463de4c5d 157 * 2. Newly scheduled alarm is behind now
group-onsemi 0:098463de4c5d 158 */
group-onsemi 0:098463de4c5d 159 //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
group-onsemi 0:098463de4c5d 160 int delta = (int) (timestamp - now);
group-onsemi 0:098463de4c5d 161 if (delta > 0) {
group-onsemi 0:098463de4c5d 162 cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
group-onsemi 0:098463de4c5d 163 lp_ticker_arm_cd();
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165 else {
group-onsemi 0:098463de4c5d 166 cd_major_minor_clks = cd_minor_clks = 0;
group-onsemi 0:098463de4c5d 167 /**
group-onsemi 0:098463de4c5d 168 * This event was in the past. Set the interrupt as pending, but don't process it here.
group-onsemi 0:098463de4c5d 169 * This prevents a recurive loop under heavy load which can lead to a stack overflow.
group-onsemi 0:098463de4c5d 170 */
group-onsemi 0:098463de4c5d 171 NVIC_SetPendingIRQ(timer3_modinit.irq_n);
group-onsemi 0:098463de4c5d 172 }
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 void lp_ticker_disable_interrupt(void)
group-onsemi 0:098463de4c5d 176 {
group-onsemi 0:098463de4c5d 177 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 178 }
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 void lp_ticker_clear_interrupt(void)
group-onsemi 0:098463de4c5d 181 {
group-onsemi 0:098463de4c5d 182 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 183 }
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 static void tmr2_vec(void)
group-onsemi 0:098463de4c5d 186 {
group-onsemi 0:098463de4c5d 187 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 188 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
group-onsemi 0:098463de4c5d 189 counter_major ++;
group-onsemi 0:098463de4c5d 190 }
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 static void tmr3_vec(void)
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 195 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 196 cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
group-onsemi 0:098463de4c5d 197 if (cd_major_minor_clks == 0) {
group-onsemi 0:098463de4c5d 198 // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
group-onsemi 0:098463de4c5d 199 lp_ticker_irq_handler();
group-onsemi 0:098463de4c5d 200 }
group-onsemi 0:098463de4c5d 201 else {
group-onsemi 0:098463de4c5d 202 lp_ticker_arm_cd();
group-onsemi 0:098463de4c5d 203 }
group-onsemi 0:098463de4c5d 204 }
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 static void lp_ticker_arm_cd(void)
group-onsemi 0:098463de4c5d 207 {
group-onsemi 0:098463de4c5d 208 TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
group-onsemi 0:098463de4c5d 211 timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
group-onsemi 0:098463de4c5d 212 // One-shot mode, Clock = 1 KHz
group-onsemi 0:098463de4c5d 213 uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 214 uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
group-onsemi 0:098463de4c5d 215 MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
group-onsemi 0:098463de4c5d 216 MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
group-onsemi 0:098463de4c5d 217 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
group-onsemi 0:098463de4c5d 218 timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
group-onsemi 0:098463de4c5d 219 timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 cd_minor_clks = cd_major_minor_clks;
group-onsemi 0:098463de4c5d 222 cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
group-onsemi 0:098463de4c5d 223 timer3_base->CMP = cd_minor_clks;
group-onsemi 0:098463de4c5d 224
group-onsemi 0:098463de4c5d 225 TIMER_EnableInt(timer3_base);
group-onsemi 0:098463de4c5d 226 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
group-onsemi 0:098463de4c5d 227 TIMER_Start(timer3_base);
group-onsemi 0:098463de4c5d 228 }
group-onsemi 0:098463de4c5d 229 #endif