ON Semiconductor / mbed-os

5.2.1 - Updated I2C files

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

hal/gpio_irq_api.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1
group-onsemi 0:098463de4c5d 2 /** \addtogroup hal */
group-onsemi 0:098463de4c5d 3 /** @{*/
group-onsemi 0:098463de4c5d 4 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 5 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 8 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 9 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 12 *
group-onsemi 0:098463de4c5d 13 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 14 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 16 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 17 * limitations under the License.
group-onsemi 0:098463de4c5d 18 */
group-onsemi 0:098463de4c5d 19 #ifndef MBED_GPIO_IRQ_API_H
group-onsemi 0:098463de4c5d 20 #define MBED_GPIO_IRQ_API_H
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 #include "device.h"
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 #if DEVICE_INTERRUPTIN
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 27 extern "C" {
group-onsemi 0:098463de4c5d 28 #endif
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 /** GPIO IRQ events
group-onsemi 0:098463de4c5d 31 */
group-onsemi 0:098463de4c5d 32 typedef enum {
group-onsemi 0:098463de4c5d 33 IRQ_NONE,
group-onsemi 0:098463de4c5d 34 IRQ_RISE,
group-onsemi 0:098463de4c5d 35 IRQ_FALL
group-onsemi 0:098463de4c5d 36 } gpio_irq_event;
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 /** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
group-onsemi 0:098463de4c5d 39 */
group-onsemi 0:098463de4c5d 40 typedef struct gpio_irq_s gpio_irq_t;
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 /**
group-onsemi 0:098463de4c5d 45 * \defgroup hal_gpioirq GPIO IRQ HAL functions
group-onsemi 0:098463de4c5d 46 * @{
group-onsemi 0:098463de4c5d 47 */
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /** Initialize the GPIO IRQ pin
group-onsemi 0:098463de4c5d 50 *
group-onsemi 0:098463de4c5d 51 * @param obj The GPIO object to initialize
group-onsemi 0:098463de4c5d 52 * @param pin The GPIO pin name
group-onsemi 0:098463de4c5d 53 * @param handler The handler to be attached to GPIO IRQ
group-onsemi 0:098463de4c5d 54 * @param id The object ID (id != 0, 0 is reserved)
group-onsemi 0:098463de4c5d 55 * @return -1 if pin is NC, 0 otherwise
group-onsemi 0:098463de4c5d 56 */
group-onsemi 0:098463de4c5d 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 /** Release the GPIO IRQ PIN
group-onsemi 0:098463de4c5d 60 *
group-onsemi 0:098463de4c5d 61 * @param obj The gpio object
group-onsemi 0:098463de4c5d 62 */
group-onsemi 0:098463de4c5d 63 void gpio_irq_free(gpio_irq_t *obj);
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 /** Enable/disable pin IRQ event
group-onsemi 0:098463de4c5d 66 *
group-onsemi 0:098463de4c5d 67 * @param obj The GPIO object
group-onsemi 0:098463de4c5d 68 * @param event The GPIO IRQ event
group-onsemi 0:098463de4c5d 69 * @param enable The enable flag
group-onsemi 0:098463de4c5d 70 */
group-onsemi 0:098463de4c5d 71 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 /** Enable GPIO IRQ
group-onsemi 0:098463de4c5d 74 *
group-onsemi 0:098463de4c5d 75 * This is target dependent, as it might enable the entire port or just a pin
group-onsemi 0:098463de4c5d 76 * @param obj The GPIO object
group-onsemi 0:098463de4c5d 77 */
group-onsemi 0:098463de4c5d 78 void gpio_irq_enable(gpio_irq_t *obj);
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 /** Disable GPIO IRQ
group-onsemi 0:098463de4c5d 81 *
group-onsemi 0:098463de4c5d 82 * This is target dependent, as it might disable the entire port or just a pin
group-onsemi 0:098463de4c5d 83 * @param obj The GPIO object
group-onsemi 0:098463de4c5d 84 */
group-onsemi 0:098463de4c5d 85 void gpio_irq_disable(gpio_irq_t *obj);
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 /**@}*/
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 90 }
group-onsemi 0:098463de4c5d 91 #endif
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 #endif
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 #endif
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /** @}*/