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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

features/unsupported/tests/KL25Z/rtc/main.cpp@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 #include "mbed.h"
group-onsemi 0:098463de4c5d 2
group-onsemi 0:098463de4c5d 3 DigitalOut status_led(LED_BLUE);
group-onsemi 0:098463de4c5d 4 DigitalOut error_led(LED_RED);
group-onsemi 0:098463de4c5d 5
group-onsemi 0:098463de4c5d 6 extern "C" void RTC_IRQHandler(void) {
group-onsemi 0:098463de4c5d 7 error_led = 0;
group-onsemi 0:098463de4c5d 8 }
group-onsemi 0:098463de4c5d 9
group-onsemi 0:098463de4c5d 10 extern "C" void RTC_Seconds_IRQHandler(void) {
group-onsemi 0:098463de4c5d 11 error_led = 0;
group-onsemi 0:098463de4c5d 12 }
group-onsemi 0:098463de4c5d 13
group-onsemi 0:098463de4c5d 14 extern "C" void HardFault_Handler(void) {
group-onsemi 0:098463de4c5d 15 error_led = 0;
group-onsemi 0:098463de4c5d 16 }
group-onsemi 0:098463de4c5d 17
group-onsemi 0:098463de4c5d 18 extern "C" void NMI_Handler_Handler(void) {
group-onsemi 0:098463de4c5d 19 error_led = 0;
group-onsemi 0:098463de4c5d 20 }
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 void rtc_init(void) {
group-onsemi 0:098463de4c5d 23 // enable the clock to SRTC module register space
group-onsemi 0:098463de4c5d 24 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
group-onsemi 0:098463de4c5d 25 SIM->SOPT1 = (SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(0);
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 // disable interrupts
group-onsemi 0:098463de4c5d 28 NVIC_DisableIRQ(RTC_Seconds_IRQn);
group-onsemi 0:098463de4c5d 29 NVIC_DisableIRQ(RTC_IRQn);
group-onsemi 0:098463de4c5d 30
group-onsemi 0:098463de4c5d 31 // Reset
group-onsemi 0:098463de4c5d 32 RTC->CR = RTC_CR_SWR_MASK;
group-onsemi 0:098463de4c5d 33 RTC->CR &= ~RTC_CR_SWR_MASK;
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 // Allow write
group-onsemi 0:098463de4c5d 36 RTC->CR = RTC_CR_UM_MASK | RTC_CR_SUP_MASK;
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 NVIC_EnableIRQ(RTC_Seconds_IRQn);
group-onsemi 0:098463de4c5d 39 NVIC_EnableIRQ(RTC_Seconds_IRQn);
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 printf("LR: 0x%x\n", RTC->LR);
group-onsemi 0:098463de4c5d 42 printf("CR: 0x%x\n", RTC->CR);
group-onsemi 0:098463de4c5d 43 wait(1);
group-onsemi 0:098463de4c5d 44 if (RTC->SR & RTC_SR_TIF_MASK){
group-onsemi 0:098463de4c5d 45 RTC->TSR = 0;
group-onsemi 0:098463de4c5d 46 }
group-onsemi 0:098463de4c5d 47 RTC->TCR = 0;
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 // After setting this bit, wait the oscillator startup time before enabling
group-onsemi 0:098463de4c5d 50 // the time counter to allow the clock time to stabilize
group-onsemi 0:098463de4c5d 51 RTC->CR |= RTC_CR_OSCE_MASK;
group-onsemi 0:098463de4c5d 52 for (volatile int i=0; i<0x600000; i++);
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54 //enable seconds interrupts
group-onsemi 0:098463de4c5d 55 RTC->IER |= RTC_IER_TSIE_MASK;
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 // enable time counter
group-onsemi 0:098463de4c5d 58 RTC->SR |= RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 }
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 int main() {
group-onsemi 0:098463de4c5d 64 error_led = 1;
group-onsemi 0:098463de4c5d 65 rtc_init();
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 while (true) {
group-onsemi 0:098463de4c5d 68 wait(1);
group-onsemi 0:098463de4c5d 69 status_led = !status_led;
group-onsemi 0:098463de4c5d 70 printf("%u\n", RTC->TSR);
group-onsemi 0:098463de4c5d 71 }
group-onsemi 0:098463de4c5d 72 }