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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2015 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "rtc_api.h"
group-onsemi 0:098463de4c5d 17
group-onsemi 0:098463de4c5d 18 static void init(void) {
group-onsemi 0:098463de4c5d 19 // enable PORTC clock
group-onsemi 0:098463de4c5d 20 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 // enable RTC clock
group-onsemi 0:098463de4c5d 23 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 // OSC32 as source
group-onsemi 0:098463de4c5d 26 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
group-onsemi 0:098463de4c5d 27 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0);
group-onsemi 0:098463de4c5d 28 }
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 void rtc_init(void) {
group-onsemi 0:098463de4c5d 31 init();
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 // Enable the oscillator
group-onsemi 0:098463de4c5d 34 #if defined (TARGET_K20D50M)
group-onsemi 0:098463de4c5d 35 RTC->CR |= RTC_CR_OSCE_MASK;
group-onsemi 0:098463de4c5d 36 #else
group-onsemi 0:098463de4c5d 37 // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator
group-onsemi 0:098463de4c5d 38 /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */
group-onsemi 0:098463de4c5d 39 RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK;
group-onsemi 0:098463de4c5d 40 #endif
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 //Configure the TSR. default value: 1
group-onsemi 0:098463de4c5d 43 RTC->TSR = 1;
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 // enable counter
group-onsemi 0:098463de4c5d 46 RTC->SR |= RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 47 }
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 void rtc_free(void) {
group-onsemi 0:098463de4c5d 50 // [TODO]
group-onsemi 0:098463de4c5d 51 }
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 /*
group-onsemi 0:098463de4c5d 54 * Little check routine to see if the RTC has been enabled
group-onsemi 0:098463de4c5d 55 * 0 = Disabled, 1 = Enabled
group-onsemi 0:098463de4c5d 56 */
group-onsemi 0:098463de4c5d 57 int rtc_isenabled(void) {
group-onsemi 0:098463de4c5d 58 // even if the RTC module is enabled,
group-onsemi 0:098463de4c5d 59 // as we use RTC_CLKIN and an external clock,
group-onsemi 0:098463de4c5d 60 // we need to reconfigure the pins. That is why we
group-onsemi 0:098463de4c5d 61 // call init() if the rtc is enabled
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 // if RTC not enabled return 0
group-onsemi 0:098463de4c5d 64 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
group-onsemi 0:098463de4c5d 65 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
group-onsemi 0:098463de4c5d 66 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
group-onsemi 0:098463de4c5d 67 return 0;
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 init();
group-onsemi 0:098463de4c5d 70 return 1;
group-onsemi 0:098463de4c5d 71 }
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 time_t rtc_read(void) {
group-onsemi 0:098463de4c5d 74 return RTC->TSR;
group-onsemi 0:098463de4c5d 75 }
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 void rtc_write(time_t t) {
group-onsemi 0:098463de4c5d 78 // disable counter
group-onsemi 0:098463de4c5d 79 RTC->SR &= ~RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 // we do not write 0 into TSR
group-onsemi 0:098463de4c5d 82 // to avoid invalid time
group-onsemi 0:098463de4c5d 83 if (t == 0)
group-onsemi 0:098463de4c5d 84 t = 1;
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 // write seconds
group-onsemi 0:098463de4c5d 87 RTC->TSR = t;
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 // re-enable counter
group-onsemi 0:098463de4c5d 90 RTC->SR |= RTC_SR_TCE_MASK;
group-onsemi 0:098463de4c5d 91 }