ON Semiconductor / mbed-os

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32F2/serial_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 *******************************************************************************
group-onsemi 0:098463de4c5d 3 * Copyright (c) 2016, STMicroelectronics
group-onsemi 0:098463de4c5d 4 * All rights reserved.
group-onsemi 0:098463de4c5d 5 *
group-onsemi 0:098463de4c5d 6 * Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 7 * modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 10 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 12 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 13 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 15 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 16 * without specific prior written permission.
group-onsemi 0:098463de4c5d 17 *
group-onsemi 0:098463de4c5d 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 28 *******************************************************************************
group-onsemi 0:098463de4c5d 29 */
group-onsemi 0:098463de4c5d 30 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 31 #include "serial_api.h"
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 #if DEVICE_SERIAL
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 #include "cmsis.h"
group-onsemi 0:098463de4c5d 36 #include "pinmap.h"
group-onsemi 0:098463de4c5d 37 #include <string.h>
group-onsemi 0:098463de4c5d 38 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 39 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #define UART_NUM (8)
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static uint32_t serial_irq_ids[UART_NUM] = {0};
group-onsemi 0:098463de4c5d 44 static UART_HandleTypeDef uart_handlers[UART_NUM];
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 int stdio_uart_inited = 0;
group-onsemi 0:098463de4c5d 49 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 #if DEVICE_SERIAL_ASYNCH
group-onsemi 0:098463de4c5d 52 #define SERIAL_S(obj) (&((obj)->serial))
group-onsemi 0:098463de4c5d 53 #else
group-onsemi 0:098463de4c5d 54 #define SERIAL_S(obj) (obj)
group-onsemi 0:098463de4c5d 55 #endif
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 static void init_uart(serial_t *obj)
group-onsemi 0:098463de4c5d 58 {
group-onsemi 0:098463de4c5d 59 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 60 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 61 huart->Instance = (USART_TypeDef *)(obj_s->uart);
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 huart->Init.BaudRate = obj_s->baudrate;
group-onsemi 0:098463de4c5d 64 huart->Init.WordLength = obj_s->databits;
group-onsemi 0:098463de4c5d 65 huart->Init.StopBits = obj_s->stopbits;
group-onsemi 0:098463de4c5d 66 huart->Init.Parity = obj_s->parity;
group-onsemi 0:098463de4c5d 67 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 68 huart->Init.HwFlowCtl = obj_s->hw_flow_ctl;
group-onsemi 0:098463de4c5d 69 #else
group-onsemi 0:098463de4c5d 70 huart->Init.HwFlowCtl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 71 #endif
group-onsemi 0:098463de4c5d 72 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 73 huart->TxXferSize = 0;
group-onsemi 0:098463de4c5d 74 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 75 huart->RxXferSize = 0;
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 if (obj_s->pin_rx == NC) {
group-onsemi 0:098463de4c5d 78 huart->Init.Mode = UART_MODE_TX;
group-onsemi 0:098463de4c5d 79 } else if (obj_s->pin_tx == NC) {
group-onsemi 0:098463de4c5d 80 huart->Init.Mode = UART_MODE_RX;
group-onsemi 0:098463de4c5d 81 } else {
group-onsemi 0:098463de4c5d 82 huart->Init.Mode = UART_MODE_TX_RX;
group-onsemi 0:098463de4c5d 83 }
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 if (HAL_UART_Init(huart) != HAL_OK) {
group-onsemi 0:098463de4c5d 86 error("Cannot initialize UART\n");
group-onsemi 0:098463de4c5d 87 }
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 91 {
group-onsemi 0:098463de4c5d 92 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 // Determine the UART to use (UART_1, UART_2, ...)
group-onsemi 0:098463de4c5d 95 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 96 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
group-onsemi 0:098463de4c5d 99 obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
group-onsemi 0:098463de4c5d 100 MBED_ASSERT(obj_s->uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 // Enable USART clock
group-onsemi 0:098463de4c5d 103 switch (obj_s->uart) {
group-onsemi 0:098463de4c5d 104 case UART_1:
group-onsemi 0:098463de4c5d 105 __HAL_RCC_USART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 106 __HAL_RCC_USART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 107 __HAL_RCC_USART1_CLK_ENABLE();
group-onsemi 0:098463de4c5d 108 obj_s->index = 0;
group-onsemi 0:098463de4c5d 109 break;
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 case UART_2:
group-onsemi 0:098463de4c5d 112 __HAL_RCC_USART2_FORCE_RESET();
group-onsemi 0:098463de4c5d 113 __HAL_RCC_USART2_RELEASE_RESET();
group-onsemi 0:098463de4c5d 114 __HAL_RCC_USART2_CLK_ENABLE();
group-onsemi 0:098463de4c5d 115 obj_s->index = 1;
group-onsemi 0:098463de4c5d 116 break;
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 #if defined(USART3_BASE)
group-onsemi 0:098463de4c5d 119 case UART_3:
group-onsemi 0:098463de4c5d 120 __HAL_RCC_USART3_FORCE_RESET();
group-onsemi 0:098463de4c5d 121 __HAL_RCC_USART3_RELEASE_RESET();
group-onsemi 0:098463de4c5d 122 __HAL_RCC_USART3_CLK_ENABLE();
group-onsemi 0:098463de4c5d 123 obj_s->index = 2;
group-onsemi 0:098463de4c5d 124 break;
group-onsemi 0:098463de4c5d 125 #endif
group-onsemi 0:098463de4c5d 126 #if defined(UART4_BASE)
group-onsemi 0:098463de4c5d 127 case UART_4:
group-onsemi 0:098463de4c5d 128 __HAL_RCC_UART4_FORCE_RESET();
group-onsemi 0:098463de4c5d 129 __HAL_RCC_UART4_RELEASE_RESET();
group-onsemi 0:098463de4c5d 130 __HAL_RCC_UART4_CLK_ENABLE();
group-onsemi 0:098463de4c5d 131 obj_s->index = 3;
group-onsemi 0:098463de4c5d 132 break;
group-onsemi 0:098463de4c5d 133 #endif
group-onsemi 0:098463de4c5d 134 #if defined(UART5_BASE)
group-onsemi 0:098463de4c5d 135 case UART_5:
group-onsemi 0:098463de4c5d 136 __HAL_RCC_UART5_FORCE_RESET();
group-onsemi 0:098463de4c5d 137 __HAL_RCC_UART5_RELEASE_RESET();
group-onsemi 0:098463de4c5d 138 __HAL_RCC_UART5_CLK_ENABLE();
group-onsemi 0:098463de4c5d 139 obj_s->index = 4;
group-onsemi 0:098463de4c5d 140 break;
group-onsemi 0:098463de4c5d 141 #endif
group-onsemi 0:098463de4c5d 142 #if defined(USART6_BASE)
group-onsemi 0:098463de4c5d 143 case UART_6:
group-onsemi 0:098463de4c5d 144 __HAL_RCC_USART6_FORCE_RESET();
group-onsemi 0:098463de4c5d 145 __HAL_RCC_USART6_RELEASE_RESET();
group-onsemi 0:098463de4c5d 146 __HAL_RCC_USART6_CLK_ENABLE();
group-onsemi 0:098463de4c5d 147 obj_s->index = 5;
group-onsemi 0:098463de4c5d 148 break;
group-onsemi 0:098463de4c5d 149 #endif
group-onsemi 0:098463de4c5d 150 #if defined(UART7_BASE)
group-onsemi 0:098463de4c5d 151 case UART_7:
group-onsemi 0:098463de4c5d 152 __HAL_RCC_UART7_FORCE_RESET();
group-onsemi 0:098463de4c5d 153 __HAL_RCC_UART7_RELEASE_RESET();
group-onsemi 0:098463de4c5d 154 __HAL_RCC_UART7_CLK_ENABLE();
group-onsemi 0:098463de4c5d 155 obj_s->index = 6;
group-onsemi 0:098463de4c5d 156 break;
group-onsemi 0:098463de4c5d 157 #endif
group-onsemi 0:098463de4c5d 158 #if defined(UART8_BASE)
group-onsemi 0:098463de4c5d 159 case UART_8:
group-onsemi 0:098463de4c5d 160 __HAL_RCC_UART8_FORCE_RESET();
group-onsemi 0:098463de4c5d 161 __HAL_RCC_UART8_RELEASE_RESET();
group-onsemi 0:098463de4c5d 162 __HAL_RCC_UART8_CLK_ENABLE();
group-onsemi 0:098463de4c5d 163 obj_s->index = 7;
group-onsemi 0:098463de4c5d 164 break;
group-onsemi 0:098463de4c5d 165 #endif
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 // Configure the UART pins
group-onsemi 0:098463de4c5d 169 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 170 pinmap_pinout(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 if (tx != NC) {
group-onsemi 0:098463de4c5d 173 pin_mode(tx, PullUp);
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175 if (rx != NC) {
group-onsemi 0:098463de4c5d 176 pin_mode(rx, PullUp);
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 // Configure UART
group-onsemi 0:098463de4c5d 180 obj_s->baudrate = 9600;
group-onsemi 0:098463de4c5d 181 obj_s->databits = UART_WORDLENGTH_8B;
group-onsemi 0:098463de4c5d 182 obj_s->stopbits = UART_STOPBITS_1;
group-onsemi 0:098463de4c5d 183 obj_s->parity = UART_PARITY_NONE;
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 186 obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 187 #endif
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 obj_s->pin_tx = tx;
group-onsemi 0:098463de4c5d 190 obj_s->pin_rx = rx;
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 init_uart(obj);
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 // For stdio management
group-onsemi 0:098463de4c5d 195 if (obj_s->uart == STDIO_UART) {
group-onsemi 0:098463de4c5d 196 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 197 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 198 }
group-onsemi 0:098463de4c5d 199 }
group-onsemi 0:098463de4c5d 200
group-onsemi 0:098463de4c5d 201 void serial_free(serial_t *obj)
group-onsemi 0:098463de4c5d 202 {
group-onsemi 0:098463de4c5d 203 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 // Reset UART and disable clock
group-onsemi 0:098463de4c5d 206 switch (obj_s->index) {
group-onsemi 0:098463de4c5d 207 case 0:
group-onsemi 0:098463de4c5d 208 __USART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 209 __USART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 210 __USART1_CLK_DISABLE();
group-onsemi 0:098463de4c5d 211 break;
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 case 1:
group-onsemi 0:098463de4c5d 214 __USART2_FORCE_RESET();
group-onsemi 0:098463de4c5d 215 __USART2_RELEASE_RESET();
group-onsemi 0:098463de4c5d 216 __USART2_CLK_DISABLE();
group-onsemi 0:098463de4c5d 217 break;
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 #if defined(USART3_BASE)
group-onsemi 0:098463de4c5d 220 case 2:
group-onsemi 0:098463de4c5d 221 __USART3_FORCE_RESET();
group-onsemi 0:098463de4c5d 222 __USART3_RELEASE_RESET();
group-onsemi 0:098463de4c5d 223 __USART3_CLK_DISABLE();
group-onsemi 0:098463de4c5d 224 break;
group-onsemi 0:098463de4c5d 225 #endif
group-onsemi 0:098463de4c5d 226 #if defined(UART4_BASE)
group-onsemi 0:098463de4c5d 227 case 3:
group-onsemi 0:098463de4c5d 228 __UART4_FORCE_RESET();
group-onsemi 0:098463de4c5d 229 __UART4_RELEASE_RESET();
group-onsemi 0:098463de4c5d 230 __UART4_CLK_DISABLE();
group-onsemi 0:098463de4c5d 231 break;
group-onsemi 0:098463de4c5d 232 #endif
group-onsemi 0:098463de4c5d 233 #if defined(UART5_BASE)
group-onsemi 0:098463de4c5d 234 case 4:
group-onsemi 0:098463de4c5d 235 __UART5_FORCE_RESET();
group-onsemi 0:098463de4c5d 236 __UART5_RELEASE_RESET();
group-onsemi 0:098463de4c5d 237 __UART5_CLK_DISABLE();
group-onsemi 0:098463de4c5d 238 break;
group-onsemi 0:098463de4c5d 239 #endif
group-onsemi 0:098463de4c5d 240 #if defined(USART6_BASE)
group-onsemi 0:098463de4c5d 241 case 5:
group-onsemi 0:098463de4c5d 242 __USART6_FORCE_RESET();
group-onsemi 0:098463de4c5d 243 __USART6_RELEASE_RESET();
group-onsemi 0:098463de4c5d 244 __USART6_CLK_DISABLE();
group-onsemi 0:098463de4c5d 245 break;
group-onsemi 0:098463de4c5d 246 #endif
group-onsemi 0:098463de4c5d 247 #if defined(UART7_BASE)
group-onsemi 0:098463de4c5d 248 case 6:
group-onsemi 0:098463de4c5d 249 __UART7_FORCE_RESET();
group-onsemi 0:098463de4c5d 250 __UART7_RELEASE_RESET();
group-onsemi 0:098463de4c5d 251 __UART7_CLK_DISABLE();
group-onsemi 0:098463de4c5d 252 break;
group-onsemi 0:098463de4c5d 253 #endif
group-onsemi 0:098463de4c5d 254 #if defined(UART8_BASE)
group-onsemi 0:098463de4c5d 255 case 7:
group-onsemi 0:098463de4c5d 256 __UART8_FORCE_RESET();
group-onsemi 0:098463de4c5d 257 __UART8_RELEASE_RESET();
group-onsemi 0:098463de4c5d 258 __UART8_CLK_DISABLE();
group-onsemi 0:098463de4c5d 259 break;
group-onsemi 0:098463de4c5d 260 #endif
group-onsemi 0:098463de4c5d 261 }
group-onsemi 0:098463de4c5d 262
group-onsemi 0:098463de4c5d 263 // Configure GPIOs
group-onsemi 0:098463de4c5d 264 pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
group-onsemi 0:098463de4c5d 265 pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 serial_irq_ids[obj_s->index] = 0;
group-onsemi 0:098463de4c5d 268 }
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 271 {
group-onsemi 0:098463de4c5d 272 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 obj_s->baudrate = baudrate;
group-onsemi 0:098463de4c5d 275 init_uart(obj);
group-onsemi 0:098463de4c5d 276 }
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 279 {
group-onsemi 0:098463de4c5d 280 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 281
group-onsemi 0:098463de4c5d 282 if (data_bits == 9) {
group-onsemi 0:098463de4c5d 283 obj_s->databits = UART_WORDLENGTH_9B;
group-onsemi 0:098463de4c5d 284 } else {
group-onsemi 0:098463de4c5d 285 obj_s->databits = UART_WORDLENGTH_8B;
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287
group-onsemi 0:098463de4c5d 288 switch (parity) {
group-onsemi 0:098463de4c5d 289 case ParityOdd:
group-onsemi 0:098463de4c5d 290 obj_s->parity = UART_PARITY_ODD;
group-onsemi 0:098463de4c5d 291 break;
group-onsemi 0:098463de4c5d 292 case ParityEven:
group-onsemi 0:098463de4c5d 293 obj_s->parity = UART_PARITY_EVEN;
group-onsemi 0:098463de4c5d 294 break;
group-onsemi 0:098463de4c5d 295 default: // ParityNone
group-onsemi 0:098463de4c5d 296 case ParityForced0: // unsupported!
group-onsemi 0:098463de4c5d 297 case ParityForced1: // unsupported!
group-onsemi 0:098463de4c5d 298 obj_s->parity = UART_PARITY_NONE;
group-onsemi 0:098463de4c5d 299 break;
group-onsemi 0:098463de4c5d 300 }
group-onsemi 0:098463de4c5d 301
group-onsemi 0:098463de4c5d 302 if (stop_bits == 2) {
group-onsemi 0:098463de4c5d 303 obj_s->stopbits = UART_STOPBITS_2;
group-onsemi 0:098463de4c5d 304 } else {
group-onsemi 0:098463de4c5d 305 obj_s->stopbits = UART_STOPBITS_1;
group-onsemi 0:098463de4c5d 306 }
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 init_uart(obj);
group-onsemi 0:098463de4c5d 309 }
group-onsemi 0:098463de4c5d 310
group-onsemi 0:098463de4c5d 311 /******************************************************************************
group-onsemi 0:098463de4c5d 312 * INTERRUPTS HANDLING
group-onsemi 0:098463de4c5d 313 ******************************************************************************/
group-onsemi 0:098463de4c5d 314
group-onsemi 0:098463de4c5d 315 static void uart_irq(int id)
group-onsemi 0:098463de4c5d 316 {
group-onsemi 0:098463de4c5d 317 UART_HandleTypeDef * huart = &uart_handlers[id];
group-onsemi 0:098463de4c5d 318
group-onsemi 0:098463de4c5d 319 if (serial_irq_ids[id] != 0) {
group-onsemi 0:098463de4c5d 320 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 321 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
group-onsemi 0:098463de4c5d 322 irq_handler(serial_irq_ids[id], TxIrq);
group-onsemi 0:098463de4c5d 323 __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
group-onsemi 0:098463de4c5d 324 }
group-onsemi 0:098463de4c5d 325 }
group-onsemi 0:098463de4c5d 326 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
group-onsemi 0:098463de4c5d 327 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
group-onsemi 0:098463de4c5d 328 irq_handler(serial_irq_ids[id], RxIrq);
group-onsemi 0:098463de4c5d 329 __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
group-onsemi 0:098463de4c5d 330 }
group-onsemi 0:098463de4c5d 331 }
group-onsemi 0:098463de4c5d 332 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
group-onsemi 0:098463de4c5d 333 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 334 volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
group-onsemi 0:098463de4c5d 335 }
group-onsemi 0:098463de4c5d 336 }
group-onsemi 0:098463de4c5d 337 }
group-onsemi 0:098463de4c5d 338 }
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 static void uart1_irq(void)
group-onsemi 0:098463de4c5d 341 {
group-onsemi 0:098463de4c5d 342 uart_irq(0);
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 static void uart2_irq(void)
group-onsemi 0:098463de4c5d 346 {
group-onsemi 0:098463de4c5d 347 uart_irq(1);
group-onsemi 0:098463de4c5d 348 }
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 #if defined(USART3_BASE)
group-onsemi 0:098463de4c5d 351 static void uart3_irq(void)
group-onsemi 0:098463de4c5d 352 {
group-onsemi 0:098463de4c5d 353 uart_irq(2);
group-onsemi 0:098463de4c5d 354 }
group-onsemi 0:098463de4c5d 355 #endif
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 #if defined(UART4_BASE)
group-onsemi 0:098463de4c5d 358 static void uart4_irq(void)
group-onsemi 0:098463de4c5d 359 {
group-onsemi 0:098463de4c5d 360 uart_irq(3);
group-onsemi 0:098463de4c5d 361 }
group-onsemi 0:098463de4c5d 362 #endif
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 #if defined(UART5_BASE)
group-onsemi 0:098463de4c5d 365 static void uart5_irq(void)
group-onsemi 0:098463de4c5d 366 {
group-onsemi 0:098463de4c5d 367 uart_irq(4);
group-onsemi 0:098463de4c5d 368 }
group-onsemi 0:098463de4c5d 369 #endif
group-onsemi 0:098463de4c5d 370
group-onsemi 0:098463de4c5d 371 #if defined(USART6_BASE)
group-onsemi 0:098463de4c5d 372 static void uart6_irq(void)
group-onsemi 0:098463de4c5d 373 {
group-onsemi 0:098463de4c5d 374 uart_irq(5);
group-onsemi 0:098463de4c5d 375 }
group-onsemi 0:098463de4c5d 376 #endif
group-onsemi 0:098463de4c5d 377
group-onsemi 0:098463de4c5d 378 #if defined(UART7_BASE)
group-onsemi 0:098463de4c5d 379 static void uart7_irq(void)
group-onsemi 0:098463de4c5d 380 {
group-onsemi 0:098463de4c5d 381 uart_irq(6);
group-onsemi 0:098463de4c5d 382 }
group-onsemi 0:098463de4c5d 383 #endif
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 #if defined(UART8_BASE)
group-onsemi 0:098463de4c5d 386 static void uart8_irq(void)
group-onsemi 0:098463de4c5d 387 {
group-onsemi 0:098463de4c5d 388 uart_irq(7);
group-onsemi 0:098463de4c5d 389 }
group-onsemi 0:098463de4c5d 390 #endif
group-onsemi 0:098463de4c5d 391
group-onsemi 0:098463de4c5d 392 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 393 {
group-onsemi 0:098463de4c5d 394 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 395
group-onsemi 0:098463de4c5d 396 irq_handler = handler;
group-onsemi 0:098463de4c5d 397 serial_irq_ids[obj_s->index] = id;
group-onsemi 0:098463de4c5d 398 }
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 401 {
group-onsemi 0:098463de4c5d 402 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 403 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 404 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 405 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 406
group-onsemi 0:098463de4c5d 407 switch (obj_s->index) {
group-onsemi 0:098463de4c5d 408 case 0:
group-onsemi 0:098463de4c5d 409 irq_n = USART1_IRQn;
group-onsemi 0:098463de4c5d 410 vector = (uint32_t)&uart1_irq;
group-onsemi 0:098463de4c5d 411 break;
group-onsemi 0:098463de4c5d 412
group-onsemi 0:098463de4c5d 413 case 1:
group-onsemi 0:098463de4c5d 414 irq_n = USART2_IRQn;
group-onsemi 0:098463de4c5d 415 vector = (uint32_t)&uart2_irq;
group-onsemi 0:098463de4c5d 416 break;
group-onsemi 0:098463de4c5d 417 #if defined(USART3_BASE)
group-onsemi 0:098463de4c5d 418 case 2:
group-onsemi 0:098463de4c5d 419 irq_n = USART3_IRQn;
group-onsemi 0:098463de4c5d 420 vector = (uint32_t)&uart3_irq;
group-onsemi 0:098463de4c5d 421 break;
group-onsemi 0:098463de4c5d 422 #endif
group-onsemi 0:098463de4c5d 423 #if defined(UART4_BASE)
group-onsemi 0:098463de4c5d 424 case 3:
group-onsemi 0:098463de4c5d 425 irq_n = UART4_IRQn;
group-onsemi 0:098463de4c5d 426 vector = (uint32_t)&uart4_irq;
group-onsemi 0:098463de4c5d 427 break;
group-onsemi 0:098463de4c5d 428 #endif
group-onsemi 0:098463de4c5d 429 #if defined(UART5_BASE)
group-onsemi 0:098463de4c5d 430 case 4:
group-onsemi 0:098463de4c5d 431 irq_n = UART5_IRQn;
group-onsemi 0:098463de4c5d 432 vector = (uint32_t)&uart5_irq;
group-onsemi 0:098463de4c5d 433 break;
group-onsemi 0:098463de4c5d 434 #endif
group-onsemi 0:098463de4c5d 435 #if defined(USART6_BASE)
group-onsemi 0:098463de4c5d 436 case 5:
group-onsemi 0:098463de4c5d 437 irq_n = USART6_IRQn;
group-onsemi 0:098463de4c5d 438 vector = (uint32_t)&uart6_irq;
group-onsemi 0:098463de4c5d 439 break;
group-onsemi 0:098463de4c5d 440 #endif
group-onsemi 0:098463de4c5d 441 #if defined(UART7_BASE)
group-onsemi 0:098463de4c5d 442 case 6:
group-onsemi 0:098463de4c5d 443 irq_n = UART7_IRQn;
group-onsemi 0:098463de4c5d 444 vector = (uint32_t)&uart7_irq;
group-onsemi 0:098463de4c5d 445 break;
group-onsemi 0:098463de4c5d 446 #endif
group-onsemi 0:098463de4c5d 447 #if defined(UART8_BASE)
group-onsemi 0:098463de4c5d 448 case 7:
group-onsemi 0:098463de4c5d 449 irq_n = UART8_IRQn;
group-onsemi 0:098463de4c5d 450 vector = (uint32_t)&uart8_irq;
group-onsemi 0:098463de4c5d 451 break;
group-onsemi 0:098463de4c5d 452 #endif
group-onsemi 0:098463de4c5d 453 }
group-onsemi 0:098463de4c5d 454
group-onsemi 0:098463de4c5d 455 if (enable) {
group-onsemi 0:098463de4c5d 456 if (irq == RxIrq) {
group-onsemi 0:098463de4c5d 457 __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 458 } else { // TxIrq
group-onsemi 0:098463de4c5d 459 __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 460 }
group-onsemi 0:098463de4c5d 461 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 462 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464 } else { // disable
group-onsemi 0:098463de4c5d 465 int all_disabled = 0;
group-onsemi 0:098463de4c5d 466 if (irq == RxIrq) {
group-onsemi 0:098463de4c5d 467 __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 468 // Check if TxIrq is disabled too
group-onsemi 0:098463de4c5d 469 if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) {
group-onsemi 0:098463de4c5d 470 all_disabled = 1;
group-onsemi 0:098463de4c5d 471 }
group-onsemi 0:098463de4c5d 472 } else { // TxIrq
group-onsemi 0:098463de4c5d 473 __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 474 // Check if RxIrq is disabled too
group-onsemi 0:098463de4c5d 475 if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
group-onsemi 0:098463de4c5d 476 all_disabled = 1;
group-onsemi 0:098463de4c5d 477 }
group-onsemi 0:098463de4c5d 478 }
group-onsemi 0:098463de4c5d 479
group-onsemi 0:098463de4c5d 480 if (all_disabled) {
group-onsemi 0:098463de4c5d 481 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 482 }
group-onsemi 0:098463de4c5d 483 }
group-onsemi 0:098463de4c5d 484 }
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 /******************************************************************************
group-onsemi 0:098463de4c5d 487 * READ/WRITE
group-onsemi 0:098463de4c5d 488 ******************************************************************************/
group-onsemi 0:098463de4c5d 489
group-onsemi 0:098463de4c5d 490 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 491 {
group-onsemi 0:098463de4c5d 492 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 493 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 while (!serial_readable(obj));
group-onsemi 0:098463de4c5d 496 return (int)(huart->Instance->DR & (uint16_t)0x1FF);
group-onsemi 0:098463de4c5d 497 }
group-onsemi 0:098463de4c5d 498
group-onsemi 0:098463de4c5d 499 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 500 {
group-onsemi 0:098463de4c5d 501 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 502 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 503
group-onsemi 0:098463de4c5d 504 while (!serial_writable(obj));
group-onsemi 0:098463de4c5d 505 huart->Instance->DR = (uint32_t)(c & (uint16_t)0x1FF);
group-onsemi 0:098463de4c5d 506 }
group-onsemi 0:098463de4c5d 507
group-onsemi 0:098463de4c5d 508 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 509 {
group-onsemi 0:098463de4c5d 510 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 511 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 512
group-onsemi 0:098463de4c5d 513 // Check if data is received
group-onsemi 0:098463de4c5d 514 return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0;
group-onsemi 0:098463de4c5d 515 }
group-onsemi 0:098463de4c5d 516
group-onsemi 0:098463de4c5d 517 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 518 {
group-onsemi 0:098463de4c5d 519 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 520 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 521
group-onsemi 0:098463de4c5d 522 // Check if data is transmitted
group-onsemi 0:098463de4c5d 523 return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0;
group-onsemi 0:098463de4c5d 524 }
group-onsemi 0:098463de4c5d 525
group-onsemi 0:098463de4c5d 526 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 527 {
group-onsemi 0:098463de4c5d 528 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 529 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 530
group-onsemi 0:098463de4c5d 531 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 532 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 533 }
group-onsemi 0:098463de4c5d 534
group-onsemi 0:098463de4c5d 535 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 536 {
group-onsemi 0:098463de4c5d 537 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 538 }
group-onsemi 0:098463de4c5d 539
group-onsemi 0:098463de4c5d 540 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 541 {
group-onsemi 0:098463de4c5d 542 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 543 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 544
group-onsemi 0:098463de4c5d 545 HAL_LIN_SendBreak(huart);
group-onsemi 0:098463de4c5d 546 }
group-onsemi 0:098463de4c5d 547
group-onsemi 0:098463de4c5d 548 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 549 {
group-onsemi 0:098463de4c5d 550 (void)obj;
group-onsemi 0:098463de4c5d 551 }
group-onsemi 0:098463de4c5d 552
group-onsemi 0:098463de4c5d 553 #if DEVICE_SERIAL_ASYNCH
group-onsemi 0:098463de4c5d 554
group-onsemi 0:098463de4c5d 555 /******************************************************************************
group-onsemi 0:098463de4c5d 556 * LOCAL HELPER FUNCTIONS
group-onsemi 0:098463de4c5d 557 ******************************************************************************/
group-onsemi 0:098463de4c5d 558
group-onsemi 0:098463de4c5d 559 /**
group-onsemi 0:098463de4c5d 560 * Configure the TX buffer for an asynchronous write serial transaction
group-onsemi 0:098463de4c5d 561 *
group-onsemi 0:098463de4c5d 562 * @param obj The serial object.
group-onsemi 0:098463de4c5d 563 * @param tx The buffer for sending.
group-onsemi 0:098463de4c5d 564 * @param tx_length The number of words to transmit.
group-onsemi 0:098463de4c5d 565 */
group-onsemi 0:098463de4c5d 566 static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
group-onsemi 0:098463de4c5d 567 {
group-onsemi 0:098463de4c5d 568 (void)width;
group-onsemi 0:098463de4c5d 569
group-onsemi 0:098463de4c5d 570 // Exit if a transmit is already on-going
group-onsemi 0:098463de4c5d 571 if (serial_tx_active(obj)) {
group-onsemi 0:098463de4c5d 572 return;
group-onsemi 0:098463de4c5d 573 }
group-onsemi 0:098463de4c5d 574
group-onsemi 0:098463de4c5d 575 obj->tx_buff.buffer = tx;
group-onsemi 0:098463de4c5d 576 obj->tx_buff.length = tx_length;
group-onsemi 0:098463de4c5d 577 obj->tx_buff.pos = 0;
group-onsemi 0:098463de4c5d 578 }
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580 /**
group-onsemi 0:098463de4c5d 581 * Configure the RX buffer for an asynchronous write serial transaction
group-onsemi 0:098463de4c5d 582 *
group-onsemi 0:098463de4c5d 583 * @param obj The serial object.
group-onsemi 0:098463de4c5d 584 * @param tx The buffer for sending.
group-onsemi 0:098463de4c5d 585 * @param tx_length The number of words to transmit.
group-onsemi 0:098463de4c5d 586 */
group-onsemi 0:098463de4c5d 587 static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
group-onsemi 0:098463de4c5d 588 {
group-onsemi 0:098463de4c5d 589 (void)width;
group-onsemi 0:098463de4c5d 590
group-onsemi 0:098463de4c5d 591 // Exit if a reception is already on-going
group-onsemi 0:098463de4c5d 592 if (serial_rx_active(obj)) {
group-onsemi 0:098463de4c5d 593 return;
group-onsemi 0:098463de4c5d 594 }
group-onsemi 0:098463de4c5d 595
group-onsemi 0:098463de4c5d 596 obj->rx_buff.buffer = rx;
group-onsemi 0:098463de4c5d 597 obj->rx_buff.length = rx_length;
group-onsemi 0:098463de4c5d 598 obj->rx_buff.pos = 0;
group-onsemi 0:098463de4c5d 599 }
group-onsemi 0:098463de4c5d 600
group-onsemi 0:098463de4c5d 601 /**
group-onsemi 0:098463de4c5d 602 * Configure events
group-onsemi 0:098463de4c5d 603 *
group-onsemi 0:098463de4c5d 604 * @param obj The serial object
group-onsemi 0:098463de4c5d 605 * @param event The logical OR of the events to configure
group-onsemi 0:098463de4c5d 606 * @param enable Set to non-zero to enable events, or zero to disable them
group-onsemi 0:098463de4c5d 607 */
group-onsemi 0:098463de4c5d 608 static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
group-onsemi 0:098463de4c5d 609 {
group-onsemi 0:098463de4c5d 610 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 611
group-onsemi 0:098463de4c5d 612 // Shouldn't have to enable interrupt here, just need to keep track of the requested events.
group-onsemi 0:098463de4c5d 613 if (enable) {
group-onsemi 0:098463de4c5d 614 obj_s->events |= event;
group-onsemi 0:098463de4c5d 615 } else {
group-onsemi 0:098463de4c5d 616 obj_s->events &= ~event;
group-onsemi 0:098463de4c5d 617 }
group-onsemi 0:098463de4c5d 618 }
group-onsemi 0:098463de4c5d 619
group-onsemi 0:098463de4c5d 620
group-onsemi 0:098463de4c5d 621 /**
group-onsemi 0:098463de4c5d 622 * Get index of serial object TX IRQ, relating it to the physical peripheral.
group-onsemi 0:098463de4c5d 623 *
group-onsemi 0:098463de4c5d 624 * @param obj pointer to serial object
group-onsemi 0:098463de4c5d 625 * @return internal NVIC TX IRQ index of U(S)ART peripheral
group-onsemi 0:098463de4c5d 626 */
group-onsemi 0:098463de4c5d 627 static IRQn_Type serial_get_irq_n(serial_t *obj)
group-onsemi 0:098463de4c5d 628 {
group-onsemi 0:098463de4c5d 629 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 630 IRQn_Type irq_n;
group-onsemi 0:098463de4c5d 631
group-onsemi 0:098463de4c5d 632 switch (obj_s->index) {
group-onsemi 0:098463de4c5d 633 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 634 case 0:
group-onsemi 0:098463de4c5d 635 irq_n = USART1_IRQn;
group-onsemi 0:098463de4c5d 636 break;
group-onsemi 0:098463de4c5d 637 #endif
group-onsemi 0:098463de4c5d 638 #if defined(USART2_BASE)
group-onsemi 0:098463de4c5d 639 case 1:
group-onsemi 0:098463de4c5d 640 irq_n = USART2_IRQn;
group-onsemi 0:098463de4c5d 641 break;
group-onsemi 0:098463de4c5d 642 #endif
group-onsemi 0:098463de4c5d 643 #if defined(USART3_BASE)
group-onsemi 0:098463de4c5d 644 case 2:
group-onsemi 0:098463de4c5d 645 irq_n = USART3_IRQn;
group-onsemi 0:098463de4c5d 646 break;
group-onsemi 0:098463de4c5d 647 #endif
group-onsemi 0:098463de4c5d 648 #if defined(UART4_BASE)
group-onsemi 0:098463de4c5d 649 case 3:
group-onsemi 0:098463de4c5d 650 irq_n = UART4_IRQn;
group-onsemi 0:098463de4c5d 651 break;
group-onsemi 0:098463de4c5d 652 #endif
group-onsemi 0:098463de4c5d 653 #if defined(UART5_BASE)
group-onsemi 0:098463de4c5d 654 case 4:
group-onsemi 0:098463de4c5d 655 irq_n = UART5_IRQn;
group-onsemi 0:098463de4c5d 656 break;
group-onsemi 0:098463de4c5d 657 #endif
group-onsemi 0:098463de4c5d 658 #if defined(USART6_BASE)
group-onsemi 0:098463de4c5d 659 case 5:
group-onsemi 0:098463de4c5d 660 irq_n = USART6_IRQn;
group-onsemi 0:098463de4c5d 661 break;
group-onsemi 0:098463de4c5d 662 #endif
group-onsemi 0:098463de4c5d 663 #if defined(UART7_BASE)
group-onsemi 0:098463de4c5d 664 case 6:
group-onsemi 0:098463de4c5d 665 irq_n = UART7_IRQn;
group-onsemi 0:098463de4c5d 666 break;
group-onsemi 0:098463de4c5d 667 #endif
group-onsemi 0:098463de4c5d 668 #if defined(UART8_BASE)
group-onsemi 0:098463de4c5d 669 case 7:
group-onsemi 0:098463de4c5d 670 irq_n = UART8_IRQn;
group-onsemi 0:098463de4c5d 671 break;
group-onsemi 0:098463de4c5d 672 #endif
group-onsemi 0:098463de4c5d 673 default:
group-onsemi 0:098463de4c5d 674 irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 675 }
group-onsemi 0:098463de4c5d 676
group-onsemi 0:098463de4c5d 677 return irq_n;
group-onsemi 0:098463de4c5d 678 }
group-onsemi 0:098463de4c5d 679
group-onsemi 0:098463de4c5d 680
group-onsemi 0:098463de4c5d 681 /******************************************************************************
group-onsemi 0:098463de4c5d 682 * MBED API FUNCTIONS
group-onsemi 0:098463de4c5d 683 ******************************************************************************/
group-onsemi 0:098463de4c5d 684
group-onsemi 0:098463de4c5d 685 /**
group-onsemi 0:098463de4c5d 686 * Begin asynchronous TX transfer. The used buffer is specified in the serial
group-onsemi 0:098463de4c5d 687 * object, tx_buff
group-onsemi 0:098463de4c5d 688 *
group-onsemi 0:098463de4c5d 689 * @param obj The serial object
group-onsemi 0:098463de4c5d 690 * @param tx The buffer for sending
group-onsemi 0:098463de4c5d 691 * @param tx_length The number of words to transmit
group-onsemi 0:098463de4c5d 692 * @param tx_width The bit width of buffer word
group-onsemi 0:098463de4c5d 693 * @param handler The serial handler
group-onsemi 0:098463de4c5d 694 * @param event The logical OR of events to be registered
group-onsemi 0:098463de4c5d 695 * @param hint A suggestion for how to use DMA with this transfer
group-onsemi 0:098463de4c5d 696 * @return Returns number of data transfered, or 0 otherwise
group-onsemi 0:098463de4c5d 697 */
group-onsemi 0:098463de4c5d 698 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
group-onsemi 0:098463de4c5d 699 {
group-onsemi 0:098463de4c5d 700 // TODO: DMA usage is currently ignored
group-onsemi 0:098463de4c5d 701 (void) hint;
group-onsemi 0:098463de4c5d 702
group-onsemi 0:098463de4c5d 703 // Check buffer is ok
group-onsemi 0:098463de4c5d 704 MBED_ASSERT(tx != (void*)0);
group-onsemi 0:098463de4c5d 705 MBED_ASSERT(tx_width == 8); // support only 8b width
group-onsemi 0:098463de4c5d 706
group-onsemi 0:098463de4c5d 707 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 708 UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 709
group-onsemi 0:098463de4c5d 710 if (tx_length == 0) {
group-onsemi 0:098463de4c5d 711 return 0;
group-onsemi 0:098463de4c5d 712 }
group-onsemi 0:098463de4c5d 713
group-onsemi 0:098463de4c5d 714 // Set up buffer
group-onsemi 0:098463de4c5d 715 serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
group-onsemi 0:098463de4c5d 716
group-onsemi 0:098463de4c5d 717 // Set up events
group-onsemi 0:098463de4c5d 718 serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
group-onsemi 0:098463de4c5d 719 serial_enable_event(obj, event, 1); // Set only the wanted events
group-onsemi 0:098463de4c5d 720
group-onsemi 0:098463de4c5d 721 // Enable interrupt
group-onsemi 0:098463de4c5d 722 IRQn_Type irq_n = serial_get_irq_n(obj);
group-onsemi 0:098463de4c5d 723 NVIC_ClearPendingIRQ(irq_n);
group-onsemi 0:098463de4c5d 724 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 725 NVIC_SetPriority(irq_n, 1);
group-onsemi 0:098463de4c5d 726 NVIC_SetVector(irq_n, (uint32_t)handler);
group-onsemi 0:098463de4c5d 727 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 728
group-onsemi 0:098463de4c5d 729 // the following function will enable UART_IT_TXE and error interrupts
group-onsemi 0:098463de4c5d 730 if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
group-onsemi 0:098463de4c5d 731 return 0;
group-onsemi 0:098463de4c5d 732 }
group-onsemi 0:098463de4c5d 733
group-onsemi 0:098463de4c5d 734 return tx_length;
group-onsemi 0:098463de4c5d 735 }
group-onsemi 0:098463de4c5d 736
group-onsemi 0:098463de4c5d 737 /**
group-onsemi 0:098463de4c5d 738 * Begin asynchronous RX transfer (enable interrupt for data collecting)
group-onsemi 0:098463de4c5d 739 * The used buffer is specified in the serial object, rx_buff
group-onsemi 0:098463de4c5d 740 *
group-onsemi 0:098463de4c5d 741 * @param obj The serial object
group-onsemi 0:098463de4c5d 742 * @param rx The buffer for sending
group-onsemi 0:098463de4c5d 743 * @param rx_length The number of words to transmit
group-onsemi 0:098463de4c5d 744 * @param rx_width The bit width of buffer word
group-onsemi 0:098463de4c5d 745 * @param handler The serial handler
group-onsemi 0:098463de4c5d 746 * @param event The logical OR of events to be registered
group-onsemi 0:098463de4c5d 747 * @param handler The serial handler
group-onsemi 0:098463de4c5d 748 * @param char_match A character in range 0-254 to be matched
group-onsemi 0:098463de4c5d 749 * @param hint A suggestion for how to use DMA with this transfer
group-onsemi 0:098463de4c5d 750 */
group-onsemi 0:098463de4c5d 751 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
group-onsemi 0:098463de4c5d 752 {
group-onsemi 0:098463de4c5d 753 // TODO: DMA usage is currently ignored
group-onsemi 0:098463de4c5d 754 (void) hint;
group-onsemi 0:098463de4c5d 755
group-onsemi 0:098463de4c5d 756 /* Sanity check arguments */
group-onsemi 0:098463de4c5d 757 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 758 MBED_ASSERT(rx != (void*)0);
group-onsemi 0:098463de4c5d 759 MBED_ASSERT(rx_width == 8); // support only 8b width
group-onsemi 0:098463de4c5d 760
group-onsemi 0:098463de4c5d 761 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 762 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 763
group-onsemi 0:098463de4c5d 764 serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
group-onsemi 0:098463de4c5d 765 serial_enable_event(obj, event, 1);
group-onsemi 0:098463de4c5d 766
group-onsemi 0:098463de4c5d 767 // set CharMatch
group-onsemi 0:098463de4c5d 768 obj->char_match = char_match;
group-onsemi 0:098463de4c5d 769
group-onsemi 0:098463de4c5d 770 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
group-onsemi 0:098463de4c5d 771
group-onsemi 0:098463de4c5d 772 IRQn_Type irq_n = serial_get_irq_n(obj);
group-onsemi 0:098463de4c5d 773 NVIC_ClearPendingIRQ(irq_n);
group-onsemi 0:098463de4c5d 774 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 775 NVIC_SetPriority(irq_n, 0);
group-onsemi 0:098463de4c5d 776 NVIC_SetVector(irq_n, (uint32_t)handler);
group-onsemi 0:098463de4c5d 777 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 778
group-onsemi 0:098463de4c5d 779 // following HAL function will enable the RXNE interrupt + error interrupts
group-onsemi 0:098463de4c5d 780 HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
group-onsemi 0:098463de4c5d 781 }
group-onsemi 0:098463de4c5d 782
group-onsemi 0:098463de4c5d 783 /**
group-onsemi 0:098463de4c5d 784 * Attempts to determine if the serial peripheral is already in use for TX
group-onsemi 0:098463de4c5d 785 *
group-onsemi 0:098463de4c5d 786 * @param obj The serial object
group-onsemi 0:098463de4c5d 787 * @return Non-zero if the TX transaction is ongoing, 0 otherwise
group-onsemi 0:098463de4c5d 788 */
group-onsemi 0:098463de4c5d 789 uint8_t serial_tx_active(serial_t *obj)
group-onsemi 0:098463de4c5d 790 {
group-onsemi 0:098463de4c5d 791 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 792
group-onsemi 0:098463de4c5d 793 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 794 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 795
group-onsemi 0:098463de4c5d 796 return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
group-onsemi 0:098463de4c5d 797 }
group-onsemi 0:098463de4c5d 798
group-onsemi 0:098463de4c5d 799 /**
group-onsemi 0:098463de4c5d 800 * Attempts to determine if the serial peripheral is already in use for RX
group-onsemi 0:098463de4c5d 801 *
group-onsemi 0:098463de4c5d 802 * @param obj The serial object
group-onsemi 0:098463de4c5d 803 * @return Non-zero if the RX transaction is ongoing, 0 otherwise
group-onsemi 0:098463de4c5d 804 */
group-onsemi 0:098463de4c5d 805 uint8_t serial_rx_active(serial_t *obj)
group-onsemi 0:098463de4c5d 806 {
group-onsemi 0:098463de4c5d 807 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 808
group-onsemi 0:098463de4c5d 809 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 810 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 811
group-onsemi 0:098463de4c5d 812 return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
group-onsemi 0:098463de4c5d 813 }
group-onsemi 0:098463de4c5d 814
group-onsemi 0:098463de4c5d 815 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
group-onsemi 0:098463de4c5d 816 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 817 __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
group-onsemi 0:098463de4c5d 818 }
group-onsemi 0:098463de4c5d 819 }
group-onsemi 0:098463de4c5d 820
group-onsemi 0:098463de4c5d 821 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
group-onsemi 0:098463de4c5d 822 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
group-onsemi 0:098463de4c5d 823 volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
group-onsemi 0:098463de4c5d 824 } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
group-onsemi 0:098463de4c5d 825 volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
group-onsemi 0:098463de4c5d 826 } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
group-onsemi 0:098463de4c5d 827 volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
group-onsemi 0:098463de4c5d 828 } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
group-onsemi 0:098463de4c5d 829 volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
group-onsemi 0:098463de4c5d 830 }
group-onsemi 0:098463de4c5d 831 }
group-onsemi 0:098463de4c5d 832
group-onsemi 0:098463de4c5d 833 /**
group-onsemi 0:098463de4c5d 834 * The asynchronous TX and RX handler.
group-onsemi 0:098463de4c5d 835 *
group-onsemi 0:098463de4c5d 836 * @param obj The serial object
group-onsemi 0:098463de4c5d 837 * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
group-onsemi 0:098463de4c5d 838 */
group-onsemi 0:098463de4c5d 839 int serial_irq_handler_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 840 {
group-onsemi 0:098463de4c5d 841 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 842 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 843
group-onsemi 0:098463de4c5d 844 volatile int return_event = 0;
group-onsemi 0:098463de4c5d 845 uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
group-onsemi 0:098463de4c5d 846 uint8_t i = 0;
group-onsemi 0:098463de4c5d 847
group-onsemi 0:098463de4c5d 848 // TX PART:
group-onsemi 0:098463de4c5d 849 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 850 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
group-onsemi 0:098463de4c5d 851 // Return event SERIAL_EVENT_TX_COMPLETE if requested
group-onsemi 0:098463de4c5d 852 if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
group-onsemi 0:098463de4c5d 853 return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
group-onsemi 0:098463de4c5d 854 }
group-onsemi 0:098463de4c5d 855 }
group-onsemi 0:098463de4c5d 856 }
group-onsemi 0:098463de4c5d 857
group-onsemi 0:098463de4c5d 858 // Handle error events
group-onsemi 0:098463de4c5d 859 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
group-onsemi 0:098463de4c5d 860 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 861 return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 862 }
group-onsemi 0:098463de4c5d 863 }
group-onsemi 0:098463de4c5d 864
group-onsemi 0:098463de4c5d 865 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
group-onsemi 0:098463de4c5d 866 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 867 return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 868 }
group-onsemi 0:098463de4c5d 869 }
group-onsemi 0:098463de4c5d 870
group-onsemi 0:098463de4c5d 871 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
group-onsemi 0:098463de4c5d 872 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 873 return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 874 }
group-onsemi 0:098463de4c5d 875 }
group-onsemi 0:098463de4c5d 876
group-onsemi 0:098463de4c5d 877 HAL_UART_IRQHandler(huart);
group-onsemi 0:098463de4c5d 878
group-onsemi 0:098463de4c5d 879 // Abort if an error occurs
group-onsemi 0:098463de4c5d 880 if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
group-onsemi 0:098463de4c5d 881 return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
group-onsemi 0:098463de4c5d 882 return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
group-onsemi 0:098463de4c5d 883 return return_event;
group-onsemi 0:098463de4c5d 884 }
group-onsemi 0:098463de4c5d 885
group-onsemi 0:098463de4c5d 886 //RX PART
group-onsemi 0:098463de4c5d 887 if (huart->RxXferSize != 0) {
group-onsemi 0:098463de4c5d 888 obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
group-onsemi 0:098463de4c5d 889 }
group-onsemi 0:098463de4c5d 890 if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
group-onsemi 0:098463de4c5d 891 return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
group-onsemi 0:098463de4c5d 892 }
group-onsemi 0:098463de4c5d 893
group-onsemi 0:098463de4c5d 894 // Check if char_match is present
group-onsemi 0:098463de4c5d 895 if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
group-onsemi 0:098463de4c5d 896 if (buf != NULL) {
group-onsemi 0:098463de4c5d 897 for (i = 0; i < obj->rx_buff.pos; i++) {
group-onsemi 0:098463de4c5d 898 if (buf[i] == obj->char_match) {
group-onsemi 0:098463de4c5d 899 obj->rx_buff.pos = i;
group-onsemi 0:098463de4c5d 900 return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events);
group-onsemi 0:098463de4c5d 901 serial_rx_abort_asynch(obj);
group-onsemi 0:098463de4c5d 902 break;
group-onsemi 0:098463de4c5d 903 }
group-onsemi 0:098463de4c5d 904 }
group-onsemi 0:098463de4c5d 905 }
group-onsemi 0:098463de4c5d 906 }
group-onsemi 0:098463de4c5d 907
group-onsemi 0:098463de4c5d 908 return return_event;
group-onsemi 0:098463de4c5d 909 }
group-onsemi 0:098463de4c5d 910
group-onsemi 0:098463de4c5d 911 /**
group-onsemi 0:098463de4c5d 912 * Abort the ongoing TX transaction. It disables the enabled interupt for TX and
group-onsemi 0:098463de4c5d 913 * flush TX hardware buffer if TX FIFO is used
group-onsemi 0:098463de4c5d 914 *
group-onsemi 0:098463de4c5d 915 * @param obj The serial object
group-onsemi 0:098463de4c5d 916 */
group-onsemi 0:098463de4c5d 917 void serial_tx_abort_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 918 {
group-onsemi 0:098463de4c5d 919 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 920 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 921
group-onsemi 0:098463de4c5d 922 __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 923 __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
group-onsemi 0:098463de4c5d 924
group-onsemi 0:098463de4c5d 925 // clear flags
group-onsemi 0:098463de4c5d 926 __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
group-onsemi 0:098463de4c5d 927
group-onsemi 0:098463de4c5d 928 // reset states
group-onsemi 0:098463de4c5d 929 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 930 // update handle state
group-onsemi 0:098463de4c5d 931 if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
group-onsemi 0:098463de4c5d 932 huart->gState = HAL_UART_STATE_BUSY_RX;
group-onsemi 0:098463de4c5d 933 } else {
group-onsemi 0:098463de4c5d 934 huart->gState = HAL_UART_STATE_READY;
group-onsemi 0:098463de4c5d 935 }
group-onsemi 0:098463de4c5d 936 }
group-onsemi 0:098463de4c5d 937
group-onsemi 0:098463de4c5d 938 /**
group-onsemi 0:098463de4c5d 939 * Abort the ongoing RX transaction It disables the enabled interrupt for RX and
group-onsemi 0:098463de4c5d 940 * flush RX hardware buffer if RX FIFO is used
group-onsemi 0:098463de4c5d 941 *
group-onsemi 0:098463de4c5d 942 * @param obj The serial object
group-onsemi 0:098463de4c5d 943 */
group-onsemi 0:098463de4c5d 944 void serial_rx_abort_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 945 {
group-onsemi 0:098463de4c5d 946 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 947 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 948
group-onsemi 0:098463de4c5d 949 // disable interrupts
group-onsemi 0:098463de4c5d 950 __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 951 __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
group-onsemi 0:098463de4c5d 952 __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
group-onsemi 0:098463de4c5d 953
group-onsemi 0:098463de4c5d 954 // clear flags
group-onsemi 0:098463de4c5d 955 __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
group-onsemi 0:098463de4c5d 956 volatile uint32_t tmpval = huart->Instance->DR; // Clear error flags
group-onsemi 0:098463de4c5d 957
group-onsemi 0:098463de4c5d 958 // reset states
group-onsemi 0:098463de4c5d 959 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 960 // update handle state
group-onsemi 0:098463de4c5d 961 if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
group-onsemi 0:098463de4c5d 962 huart->RxState = HAL_UART_STATE_BUSY_TX;
group-onsemi 0:098463de4c5d 963 } else {
group-onsemi 0:098463de4c5d 964 huart->RxState = HAL_UART_STATE_READY;
group-onsemi 0:098463de4c5d 965 }
group-onsemi 0:098463de4c5d 966 }
group-onsemi 0:098463de4c5d 967
group-onsemi 0:098463de4c5d 968 #endif
group-onsemi 0:098463de4c5d 969
group-onsemi 0:098463de4c5d 970 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 971
group-onsemi 0:098463de4c5d 972 /**
group-onsemi 0:098463de4c5d 973 * Set HW Control Flow
group-onsemi 0:098463de4c5d 974 * @param obj The serial object
group-onsemi 0:098463de4c5d 975 * @param type The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS)
group-onsemi 0:098463de4c5d 976 * @param rxflow Pin for the rxflow
group-onsemi 0:098463de4c5d 977 * @param txflow Pin for the txflow
group-onsemi 0:098463de4c5d 978 */
group-onsemi 0:098463de4c5d 979 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 980 {
group-onsemi 0:098463de4c5d 981 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 982
group-onsemi 0:098463de4c5d 983 // Determine the UART to use (UART_1, UART_2, ...)
group-onsemi 0:098463de4c5d 984 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 985 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 986
group-onsemi 0:098463de4c5d 987 // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
group-onsemi 0:098463de4c5d 988 obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
group-onsemi 0:098463de4c5d 989 MBED_ASSERT(obj_s->uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 990
group-onsemi 0:098463de4c5d 991 if(type == FlowControlNone) {
group-onsemi 0:098463de4c5d 992 // Disable hardware flow control
group-onsemi 0:098463de4c5d 993 obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 994 }
group-onsemi 0:098463de4c5d 995 if (type == FlowControlRTS) {
group-onsemi 0:098463de4c5d 996 // Enable RTS
group-onsemi 0:098463de4c5d 997 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 998 obj_s->hw_flow_ctl = UART_HWCONTROL_RTS;
group-onsemi 0:098463de4c5d 999 obj_s->pin_rts = rxflow;
group-onsemi 0:098463de4c5d 1000 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 1001 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 1002 }
group-onsemi 0:098463de4c5d 1003 if (type == FlowControlCTS) {
group-onsemi 0:098463de4c5d 1004 // Enable CTS
group-onsemi 0:098463de4c5d 1005 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 1006 obj_s->hw_flow_ctl = UART_HWCONTROL_CTS;
group-onsemi 0:098463de4c5d 1007 obj_s->pin_cts = txflow;
group-onsemi 0:098463de4c5d 1008 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 1009 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 1010 }
group-onsemi 0:098463de4c5d 1011 if (type == FlowControlRTSCTS) {
group-onsemi 0:098463de4c5d 1012 // Enable CTS & RTS
group-onsemi 0:098463de4c5d 1013 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 1014 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 1015 obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
group-onsemi 0:098463de4c5d 1016 obj_s->pin_rts = rxflow;
group-onsemi 0:098463de4c5d 1017 obj_s->pin_cts = txflow;
group-onsemi 0:098463de4c5d 1018 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 1019 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 1020 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 1021 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 1022 }
group-onsemi 0:098463de4c5d 1023
group-onsemi 0:098463de4c5d 1024 init_uart(obj);
group-onsemi 0:098463de4c5d 1025 }
group-onsemi 0:098463de4c5d 1026
group-onsemi 0:098463de4c5d 1027 #endif
group-onsemi 0:098463de4c5d 1028
group-onsemi 0:098463de4c5d 1029 #endif